KR102211066B1 - Thin film Transistor Substrate For Flat Panel Display And Method For Manufacturing The Same - Google Patents

Abstract

The present invention relates to a thin film transistor substrate for a flat panel display device such as an organic light emitting diode display and a method of manufacturing the same. The thin film transistor substrate for a flat panel display device according to the present invention includes a scan wiring disposed on the substrate, a buffer layer covering the scan wiring, a semiconductor layer disposed on the buffer layer, a gate insulating film and a gate electrode disposed on the semiconductor layer, an anode electrode, and a gate electrode. And a covering intermediate insulating film and a data line disposed on the intermediate insulating film. The scan wires are disposed on the substrate in one direction of the pixel area. The gate insulating film covers the channel region, which is the central region of the semiconductor layer. The gate electrode overlaps the channel region on the gate insulating layer and is connected to the scan wiring. The anode electrode is disposed in the pixel area on the gate insulating layer. The intermediate insulating layer covers the gate electrode and exposes most of the center of the pixel electrode. The data lines are disposed on the intermediate insulating layer in the direction of the other side of the pixel area.

Description

Thin film transistor substrate for flat panel display and method for manufacturing the same

The present invention relates to a thin film transistor substrate for a flat panel display device such as an organic light emitting diode display and a method of manufacturing the same. In particular, the present invention relates to a thin film transistor substrate for a flat panel display device capable of high-speed driving by increasing insulation between scan wiring and data wiring, reducing parasitic capacitance, and a method of manufacturing the same.

Recently, various flat panel display devices capable of reducing the weight and volume, which are the disadvantages of a cathode ray tube, have been developed. Such flat panel displays include Liquid Crystal Display (LCD), Field Emission Display (FED), Plasma Display Panel (PDP), and Electroluminescence Device (EL). There is this.

Electroluminescent display devices are roughly classified into inorganic electroluminescent display devices and organic light emitting diode display devices according to the material of the light emitting layer. As a self-luminous device that emits light, it has a fast response speed, and has great luminous efficiency, luminance and viewing angle.

1 is a diagram showing the structure of a general organic light emitting diode. The organic light emitting diode includes an organic electroluminescent compound layer that emits light as shown in FIG. 1, and a cathode electrode and an anode electrode facing each other with the organic electroluminescent compound layer therebetween. The organic electroluminescent compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer. layer, EIL).

In the organic light emitting diode, excitons are formed during the excitation process when holes and electrons injected into the anode and cathode are recombined in the emission layer EML and emit light due to energy from the excitons. The organic light emitting diode display device displays an image by electrically controlling the amount of light emitted from the emission layer EML of the organic light emitting diode as shown in FIG. 1.

In the organic light emitting diode display (OLEDD) using the characteristics of the organic light emitting diode, which is an electroluminescent element, a passive matrix type organic light emitting diode display (PMOLED) and an active matrix It is roughly classified as an Active Matrix type Organic Light Emitting Diode display (AMOLED).

An active matrix type organic light emitting diode display (AMOLED) uses a thin film transistor (or "TFT") to control the current flowing through the organic light emitting diode to display an image. 2 is an example of an equivalent circuit diagram showing the structure of one pixel in a general organic light emitting diode display. 3 is a plan view illustrating a structure of one pixel in an organic light emitting diode display according to the prior art. FIG. 4 is a cross-sectional view showing the structure of an organic light emitting diode display according to the prior art, cut along the perforated line I-I' in FIG. 3.

2 to 3, the active matrix organic light emitting diode display includes a switching thin film transistor ST, a driving thin film transistor DT connected to the switching thin film transistor ST, and an organic light emitting diode connected to the driving thin film transistor DT. (OLE) included. The switching thin film transistor ST is formed at a portion where the scan line SL and the data line DL cross each other. The switching thin film transistor ST serves to select a pixel. The switching thin film transistor ST includes a gate electrode SG branching from the scan line SL, a semiconductor layer SA, a source electrode SS, and a drain electrode SD.

Further, the driving thin film transistor DT serves to drive the organic light emitting diode OLE of a pixel selected by the switching thin film transistor ST. The driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a semiconductor layer DA, a source electrode DS connected to the driving current line VDD, and a drain. It includes an electrode DD. The drain electrode DD of the driving TFT DT is connected to the anode electrode ANO of the organic light emitting diode OLE.

Referring to FIG. 4 for a more detailed look, in the active matrix organic light emitting diode display, gate electrodes SG and DG of the switching TFT ST and the driving TFT DT are formed on a transparent substrate SUB. have. In addition, the gate insulating film GI is covering the gate electrodes SG and DG. Semiconductor layers SA and DA are formed on a part of the gate insulating film GI overlapping the gate electrodes SG and DG. Source electrodes SS and DS and drain electrodes SD and DD are formed on the semiconductor layers SA and DA at regular intervals to face each other. The drain electrode SD of the switching thin film transistor ST contacts the gate electrode DG of the driving thin film transistor DT through the gate contact hole GH formed in the gate insulating layer GI. A protective layer PAS covering the switching thin film transistor ST and the driving thin film transistor DT having such a structure is applied on the entire surface.

In particular, when the semiconductor layers SA and DA are formed of an oxide semiconductor material, it is advantageous for high resolution and high speed driving in a large area thin film transistor substrate having a large charging capacity due to high charge mobility characteristics. However, it is preferable that the oxide semiconductor material further includes an etch stopper (SE, DE) for protection from an etchant on the upper surface in order to secure the stability of the device. Specifically, it protects the semiconductor layers (SA, DA) from being back etched from the etchant in contact with the exposed upper surface at the spaced portion between the source electrodes (SS, DS) and the drain electrodes (SD, DD). Etch stoppers (SE, DE) are formed so as to be.

The color filter CF is formed in a portion corresponding to the area of the anode electrode ANO to be formed later. It is preferable to form the color filter CF to occupy as large an area as possible. For example, it is preferable to form the data line DL, the driving current line VDD, and the plurality of regions of the scan line SL at the front end. In the substrate on which the color filter CF is formed as described above, the surface of the substrate on which the color filter CF is formed is not flat and has many steps. Accordingly, the overcoat layer OC is applied to the entire surface of the substrate SUB for the purpose of flattening the surface of the substrate.

In addition, the anode electrode ANO of the organic light emitting diode OLE is formed on the overcoat layer OC. Here, the anode electrode ANO is connected to the drain electrode DD of the driving TFT DT through the pixel contact hole PH formed in the overcoat layer OC and the protective layer PAS.

On the substrate on which the anode electrode ANO is formed, a bank BA is formed on the area where the switching thin film transistor ST, the driving thin film transistor DT, and various wires DL, SL, VDD are formed to define a pixel area. do. The anode electrode ANO exposed by the bank BA becomes a light emitting area.

An organic light emitting layer OL and a cathode electrode CAT are sequentially stacked on the anode electrode ANO exposed by the bank BA. When the organic light-emitting layer OL is made of an organic material emitting white light, the color assigned to each pixel by the color filter CF located below is displayed. The organic light emitting diode display device having the structure as shown in FIG. 4 becomes a bottom emission display device that emits light in a downward direction.

In the case of an organic light emitting diode display, the organic light emitting diode is driven using a relatively large current. Therefore, it is desirable that the characteristics of the thin film transistor are suitable for high current driving. In the case of an oxide semiconductor, it is suitable for such an organic light emitting diode display. However, as the need for high-density, highly integrated organic light-emitting diodes increases, characteristics of thin film transistors suitable for driving large currents at high speed are more required.

In particular, in the case of an oxide semiconductor, there is a disadvantage in that the characteristic change is severe due to light flowing from the surrounding. The organic light emitting diode display has a problem in that it is difficult to stabilize the characteristics of the device when light emitted from an organic layer emitting light as a self-luminous device flows into an oxide semiconductor layer of a thin film transistor.

In order to use an oxide semiconductor material as a channel layer and to drive at a high speed, a thin film transistor having a top gate structure different from the structure shown in FIG. 4 may be used. In the bottom gate structure illustrated in FIG. 4, since the gate metal is disposed on the side surface exposed to external light, the gate metal can block the influence of external light. However, in the top gate structure, since a channel layer is disposed on a side surface exposed to external light in a bottom-emitting type organic light emitting diode display, the channel layer may be affected by external light and device characteristics may be deteriorated.

An object of the present invention is an invention conceived to solve the problems of the prior art, and for a flat panel display device having a thin film transistor in which device characteristics are secured by arranging a light-shielding metal layer under the thin film transistor having a Tpo gate structure. It is to provide a thin film transistor substrate. In addition, the light blocking metal layer may have a double gate structure by providing a bottom gate function, and may be connected to other power sources as necessary and used for various purposes. Further, an object is to provide a method of manufacturing a thin film transistor substrate for a flat panel display device in which the process is simplified by forming an upper gate electrode on the same layer as a pixel electrode and made of the same material.

In order to achieve the object of the present invention, the thin film transistor substrate for a flat panel display device according to the present invention includes: a scan wiring disposed on the substrate, a buffer layer covering the scan wiring, a semiconductor layer disposed on the buffer layer, and a gate insulating film disposed on the semiconductor layer. And a gate electrode, an anode electrode, an intermediate insulating layer covering the gate electrode, and a data line disposed on the intermediate insulating layer. A plurality of pixel regions are defined on the substrate. The scan wires are disposed on the substrate in one direction of the pixel area. The gate insulating film covers the channel region, which is the central region of the semiconductor layer. The gate electrode overlaps the channel region on the gate insulating layer and is connected to the scan wiring. The anode electrode is disposed in the pixel area on the gate insulating layer. The intermediate insulating layer covers the gate electrode and exposes most of the center of the pixel electrode. In addition, the data lines are disposed on the intermediate insulating layer in the direction of the other side of the pixel area.

The thin film transistor substrate further includes a light blocking layer, a first storage capacitor electrode, a second storage capacitor electrode, a source electrode, a drain electrode, and a third storage capacitor electrode. The light blocking layer is made of the same material as the scan wiring and is disposed to overlap the semiconductor layer in the same layer. The first storage capacitor electrode is made of the same material as the scan wiring and is disposed at a position of the storage capacitor in the same layer. The second storage capacitor electrode includes the same material as the semiconductor layer, and is disposed at a position of the storage capacitor in the same layer. The source electrode includes the same material as the data line, and is branched from the data line in the same layer to contact one side of the semiconductor layer. The drain electrode is disposed to be spaced apart from the source electrode by a predetermined distance to contact the other side of the semiconductor layer. In addition, the third storage capacitor electrode extends from the drain electrode and overlaps the second storage capacitor electrode.

The thin film transistor substrate further includes a bank, an organic light emitting layer, and a cathode electrode. The bank covers the data line and defines an opening area exposing most of the central portion of the anode electrode. The organic light emitting layer is deposited on the anode electrode exposed above the bank. And the cathode electrode is stacked on the organic light emitting layer.

The gate electrode and the anode electrode are disposed on the same layer and contain a transparent conductive material such as indium-tin-oxide.

In addition, a method of manufacturing a thin film transistor substrate for a flat panel display according to the present invention includes: forming a scan wire on the substrate, forming a semiconductor layer, forming a gate insulating film, forming a gate electrode and an anode electrode , Forming an intermediate insulating layer, forming a data line, and forming a bank. In the forming of the semiconductor layer, a buffer layer is applied on the surface of the substrate on which the scan wiring is formed, and a semiconductor layer is formed on the buffer layer. The gate insulating layer is formed to cover the central portion and the pixel region of the semiconductor layer. The gate electrode is formed on the gate insulating layer so as to overlap the central portion of the semiconductor layer. At the same time, the anode electrode is disposed in the pixel area. The intermediate insulating film covers the gate electrode and the anode electrode. The data wiring is disposed on the intermediate insulating layer so as to cross the scan wiring. In addition, the bank is formed to cover the data line and expose most of the central portion of the anode electrode.

In the thin film transistor substrate for a flat panel display device according to the present invention, a two-layer insulating film including a buffer layer and an intermediate insulating film is interposed between a scan wire and a data wire defining a pixel region and which are orthogonal to each other on the substrate do. This can be achieved by forming the scan wiring in the same position as the light shielding layer. As a result, it is possible to suppress the generation of parasitic capacitance between the scan wiring and the data wiring. In addition, by preventing the occurrence of insulation breakdown at a portion where the data wiring passes over the scan wiring, the wiring is not deteriorated. In this structure, the gate electrode must be formed on a separate layer from the scan line. However, since the gate electrode is formed together when the anode electrode is formed, the number of mask processes is not increased.

1 is a diagram showing the structure of a general organic light emitting diode.
2 is an equivalent circuit diagram showing a structure of one pixel in a general organic light emitting diode display.
3 is a plan view showing a structure of one pixel in an organic light emitting diode display according to the prior art.
FIG. 4 is a cross-sectional view showing the structure of an organic light emitting diode display according to the prior art, cut along the perforated line I-I' in FIG. 3.
5 is a plan view showing a structure of one pixel in an organic light emitting diode display according to the present invention.
FIG. 6 is a cross-sectional view showing the structure of an organic light emitting diode display according to the present invention taken along the line II-II' in FIG. 5;
7A to 7G are cross-sectional views illustrating a method of manufacturing an organic light-emitting diode display device according to the present invention, taken along a line II-II' in FIG. 5.
8 is a flowchart schematically showing a manufacturing process of an organic light emitting diode display device according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. The same reference numerals throughout the specification mean substantially the same constituent elements. In the following description, when it is determined that a detailed description of a known technology or configuration related to the present invention may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 5 and 6. 5 is a plan view showing a structure of one pixel in an organic light emitting diode display according to the present invention. 6 is a cross-sectional view showing the structure of an organic light emitting diode display according to the present invention, taken along a line II-II' in FIG. 5.

The active matrix organic light emitting diode display according to an embodiment of the present invention includes a switching thin film transistor ST, a driving thin film transistor DT connected to the switching thin film transistor ST, and an organic light emitting diode connected to the driving thin film transistor DT. (OLE) included. The switching thin film transistor ST is formed at a portion where the scan line SL and the data line DL cross each other. The switching thin film transistor ST serves to select a pixel. The switching thin film transistor ST includes a gate electrode SG branching from the scan line SL, a semiconductor layer SA, a source electrode SS, and a drain electrode SD.

Further, the driving thin film transistor DT serves to drive the organic light emitting diode OLE of a pixel selected by the switching thin film transistor ST. The driving thin film transistor DT includes a gate electrode DG connected to the drain electrode SD of the switching thin film transistor ST, a semiconductor layer DA, a source electrode DS connected to the driving current line VDD, and a drain. It includes an electrode DD. The drain electrode DD of the driving TFT DT is connected to the anode electrode ANO of the organic light emitting diode OLE.

In the present invention, an oxide semiconductor material advantageous for high speed characteristics is used as the semiconductor layers SA and DA, and thin film transistors ST and DT having a top gate structure are applied. In addition, when the thin film transistors (ST, DT) of the top gate structure are applied to the bottom-emitting type organic light emitting diode display, light blocking layers (SLS, DLS) are used to protect the semiconductor layers (SA, DA) exposed to external light. It has more.

In particular, by forming the scan wiring SL together with the light blocking layers SLS and DLS so that two insulating films are interposed between the scan wiring SL and the data wiring DL, the scan wiring SL and the data wiring ( It minimizes parasitic capacitance between DL) and prevents damage due to insulation breakdown. In addition, if the first storage capacitor electrode ST1 is formed together with the light blocking layers SLS and DLS, the size of the storage capacitor can be further secured, thereby reducing the area of the storage capacitor and increasing the opening area.

Referring further to FIG. 6 for detailed description, the active matrix organic light emitting diode display includes a scan line SL made of an opaque metal material on a transparent substrate SUB. Meanwhile, a switching light blocking layer SLS and a driving light blocking layer DLS are formed at positions where the switching thin film transistor ST and the driving thin film transistor DT are to be formed. In addition, a first storage capacitor electrode ST1 is formed at a location where the storage capacitor STG is to be formed.

A buffer layer BUF is applied on the scan line SL, the switching light blocking layer SLS, the driving light blocking layer DLS, and the first storage capacitor electrode ST1 to cover the entire surface of the substrate SUB. A semiconductor layer is formed on the buffer layer BUF, and the channel region DA of the driving thin film transistor DT is driven so that the channel region SA of the switching thin film transistor ST is overlapped within the switching light blocking layer SLS region. It is disposed so as to overlap in the light blocking layer DLS area. In addition, a second storage capacitor electrode ST2 overlapping the first storage capacitor electrode ST1 is formed of the same material as the semiconductor layer at a location where the storage capacitor STG is to be formed. The second storage capacitor electrode ST2 may be formed to be floating in an island shape or may be connected to the semiconductor layer of the switching thin film transistor ST. In FIG. 5, the second storage capacitor electrode ST2 is connected to the semiconductor layer of the switching thin film transistor ST, and in particular, is shown in a structure extending from the drain region.

A gate insulating layer GI, a switching gate electrode SG, and a driving gate electrode DG are formed on each of the switching channel region SA and the driving channel region DA. In addition, a pixel electrode or an anode electrode ANO is formed in the pixel region. Since the pixel electrode or anode electrode ANO and the gate electrodes SG and DG are simultaneously formed, in the present invention, they are formed of a transparent conductive material. In this case, the switching gate electrode SG should be connected to the scan line SL. In the present invention, the switching gate electrode SG and the scan wiring SL are connected through the light blocking layer contact hole LH penetrating the buffer layer BUF. When the gate insulating layer GI is formed at a position where the gate electrode material is formed, the light blocking layer contact hole LH may be formed to penetrate the gate insulating layer GI and the buffer layer BUF.

An intermediate insulating layer IN is formed over the entire surface of the substrate SUB on the gate electrodes SG and DG and the anode electrode ANO. A data line DL and a driving current line VDD formed of a conductive material such as copper are disposed on the intermediate insulating layer IN. The data line DL and the driving current line VDD have a structure crossing the scan line SL, and define a pixel region. In particular, since the buffer layer BUF and the intermediate insulating film IN are stacked and interposed at a portion where the data wiring DL and the driving current wiring VDD cross the scan wiring SL, the insulation between the two wirings is excellent. And can suppress the occurrence of parasitic capacity. In particular, it is possible to prevent wiring disconnection or burning due to insulation breakdown at a portion where the data line DL passes through the scan line SL.

In addition, the switching source electrode SS branching from the data line DL and the switching drain electrode SD disposed opposite the switching source electrode SS are formed on the intermediate insulating layer IN, thereby forming the switching thin film transistor ST. ) Is formed. The switching source electrode SS is connected to one side of the switching channel region SA through the switching source contact hole SSH. The switching drain electrode SD is connected to the other side of the switching channel region SA through the switching drain contact hole SDH. Similarly, the driving source electrode DS branching from the driving current line VDD and the driving drain electrode DD disposed opposite to the driving source electrode DS are formed, thereby forming the driving thin film transistor DT. The driving source electrode DS is connected to one side of the driving channel region DA through the driving source contact hole DSH. The driving drain electrode DD is connected to the other side of the driving channel region DA through the driving drain contact hole DTH. Meanwhile, the switching drain electrode SD is connected to the driving gate electrode DG through the gate contact hole GH.

A passivation layer PAS or bank BN is applied on the entire surface of the substrate SUB on which the source-drain elements are formed. As another example, the passivation layer PAS and the bank BA may be sequentially stacked. An opening defining a light emitting area in the anode electrode ANO is formed in the passivation layer PAS or the intermediate insulating layer IN covering the bank BN and the anode electrode ANO.

In the case of an organic light emitting diode display, an organic light emitting layer OL and a cathode electrode CAT are sequentially stacked on an anode electrode ANO in a substrate SUB on which banks BN are formed. That is, the organic light emitting diode OLE is connected to the driving thin film transistor DT by a stacked structure of the anode electrode ANO, the organic light emitting layer OL, and the cathode electrode CAT.

In the description of the present invention, no reference is made to the color filter. In the case of a bottom emission type while using a color filter, it is preferable to form a color filter under the anode electrode ANO. In the case of a top emission type, it is preferable to form on the anode electrode ANO. In some cases, the organic light-emitting layer OL may have a structure in which a color filter is not applied by using a light-emitting material that expresses any one of red, green, and blue, and is independently disposed in each pixel area.

In FIG. 5 for explaining an embodiment of the present invention, the switching light-shielding layer SLS and the driving light-shielding layer DLS are illustrated in an island shape in separate forms. However, if necessary, it may be connected to the gate electrodes SG and DG to have a double gate structure. For example, the switching light blocking layer SLS may be formed to extend from the scan line SL. On the other hand, the driving light blocking layer DLS may be connected to the driving gate electrode DG through a separate contact hole (not shown).

Hereinafter, a method of manufacturing an organic light emitting diode display according to the present invention will be described with reference to FIGS. 7A to 7G and FIG. 8. 7A to 7G are cross-sectional views illustrating a method of manufacturing an organic light-emitting diode display device according to the present invention, taken along a line II-II' in FIG. 5. 8 is a flowchart schematically illustrating a manufacturing process of an organic light emitting diode display according to the present invention.

First, an opaque metal material having excellent conductivity is applied on the substrate SUB. The metal material is patterned by a first mask process to form the scan line SL, the light blocking layers SLS and DLS, and the first storage capacitor electrode ST1 (S100 in FIG. 8). The scan line SL is a substrate. Arrange to proceed in the uniaxial direction of (SUB). It is preferable to arrange the light shielding layer so as to overlap with the semiconductor layer of the thin film transistor to be formed later, in particular, the channel region. For example, the switching light blocking layer SLS is disposed at a position where the switching thin film transistor ST is to be formed, and the driving light blocking layer DLS is disposed at a position where the driving thin film transistor ST is formed. In addition, a first storage capacitor electrode ST1 is formed at a position where the storage capacitor STG is to be formed. (Fig. 7a)

The buffer layer BUF is applied on the entire surface of the substrate SUB on which the scan wiring SL, the light blocking layers SLS and DLS, and the first storage capacitor electrode ST1 are formed. A metal oxide semiconductor material such as Indium-Galium-Zinc-Oxide (IGZO) is sequentially coated on the buffer layer BUF. The oxide semiconductor material is patterned by fixing the second mask to form the semiconductor layer SE and the second storage capacitor electrode ST2. (S200 of FIG. 8) The semiconductor layer SE is preferably formed at a position where the switching thin film transistor ST and the driving thin film transistor DT are to be formed. It is preferable to arrange the second storage capacitor electrode ST2 to overlap the first storage capacitor electrode ST1. In particular, the second storage capacitor electrode ST2 may be formed to extend from the semiconductor layer disposed on the switching thin film transistor ST. (Fig. 7b)

An insulating material is coated on the entire surface of the substrate SUB on which the semiconductor layer SE and the second storage capacitor electrode ST2 are formed. An insulating material is patterned by a third mask process to form a gate insulating layer GI. In particular, the gate insulating layer GI is formed to cover the central portion of the semiconductor layer SE and expose both side portions. In this process, both sides of the exposed semiconductor layer SE are conductive. On the other hand, the central portion remains in a semiconductor state and is defined as a channel region. That is, the switching channel region SA is defined at the position of the switching thin film transistor ST, and the driving channel region DA is defined at the position of the driving thin film transistor DT. In this case, it is preferable to remove the insulating material on the second storage capacitor electrode ST2 to form a conductor. In order to allow the gate electrode formed on the gate insulating layer GI to be connected to the scan line SL, a light blocking layer contact hole LH exposing a part of the scan line SL is formed. (300 in FIG. 8) In order to simultaneously pattern the gate insulating film GI and the buffer layer BUF having similar properties, it is preferable to use a half-tone mask if necessary. (Fig. 7c)

A transparent conductive material such as Indium-Tin-Oxide (ITO) is coated on the entire surface of the substrate SUB on which the gate insulating layer GI is formed. A transparent conductive material is patterned by a fourth mask process to form gate electrodes SG and DG and anode electrodes ANO. (400 of FIG. 8) The switching gate electrode SG is preferably formed on the gate insulating film GI defining the switching channel region SA. Similarly, the driving gate electrode DG is preferably formed on the gate insulating film GI defining the driving channel region DA. Meanwhile, the switching gate electrode SG extends to overlap the scan line SL and contacts the scan line SL through the light blocking layer contact hole LH. In addition, an anode electrode ANO is formed in the pixel area. By simultaneously forming the anode electrode ANO and the gate electrodes SG and DG using a transparent conductive material, it is possible to reduce the number of mask processes. (Fig. 7d)

The intermediate insulating layer IN is formed by applying an insulating material on the entire surface of the substrate SUB on which the transparent conductive layer elements are formed. The intermediate insulating layer IN is patterned by a fifth mask process to form necessary contact holes. (500 of FIG. 8) For example, a switching source contact hole SSH and a switching drain contact hole SDH are formed exposing the conductive regions on both sides of the switching channel region SA. Similarly, a driving source contact hole DSH and a driving drain contact hole DTH exposing the conductive regions on both sides of the driving channel region DA are formed. Also, a gate contact hole GH exposing a part of the driving gate electrode DG is formed. (Fig. 7e)

A metal material having excellent conductivity is coated on the entire surface of the substrate SUB in which the contact holes are formed. It is preferable that the metal material having excellent conductivity includes copper or aluminum. If necessary, it may have a structure in which triple or double metals are laminated, such as molybdenum/copper/molybdenum. A source-drain element is formed by patterning a metal material in a sixth mask process. (600 of FIG. 8) In the source-drain element, a data line DL and a driving current line VDD extending in the other direction of the substrate SUB, a switching source electrode SS branching from the data line DL, and driving A driving source electrode DS branching from the current line VDD, a switching drain electrode SD facing the switching source electrode SS, and a driving drain electrode DD facing the driving source electrode DS.

The switching source electrode SS is connected to one side of the switching channel region SA through the switching source contact hole SSH. The switching drain electrode SD is connected to the other side of the switching channel region SA through the switching drain contact hole SDH. Likewise, the driving source electrode DS is connected to one side of the driving channel area DA through the driving source contact hole DSH. The driving drain electrode DD is connected to the other side of the driving channel region DA through the driving drain contact hole DTH. (Fig. 7f)

An insulating material is applied over the entire surface of the substrate SUB on which the source-drain elements are formed. Here, the insulating material may include an inorganic insulating material or an organic insulating material. In some cases, an inorganic insulating material and an organic insulating material may be sequentially stacked. In the case of an organic light emitting diode display, a photosensitive organic insulating material may be applied. An insulating material is patterned in the seventh mask process to form banks BN defining openings exposing most of the anode electrode ANO. (700 in Fig. 8) (Fig. 7g)

Thereafter, although not shown in the drawing, when the organic light emitting layer OL and the cathode electrode CAT are sequentially applied on the entire surface of the substrate SUB on which the banks BN are formed, the organic light emitting diode display having the structure as shown in FIG. 6 You can complete the device. Here, the process of manufacturing the thin film transistor substrate has been mainly described.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the spirit of the present invention. Accordingly, the present invention should not be limited to the content described in the detailed description, but should be defined by the claims.

DL: Data wiring SL: Scan wiring
VDD: drive current wiring ST: switching TFT
DT: Driving TFT OLED: Organic Light-Emitting Diode
CAT: cathode electrode (layer) ANO: anode electrode (layer)
BN: Bank CF: Color filter
OLE: (white) organic light emitting layer SUB: substrate
PAS: protective film OC: overcoat layer
SG, DG: gate electrode SE: semiconductor layer
SS, DS: source electrode SD, DD: drain electrode
BUF: buffer layer PH: pixel contact hole
SLS: switching light-shielding layer DLS: driving light-shielding layer
STG: storage capacitor SG1: first storage capacitor electrode
SG2: second storage capacitor electrode SG3: third storage capacitor electrode

Claims (5)

A substrate on which a plurality of pixel regions are defined;
A scan line disposed on the substrate in a direction of one side of the pixel area;
A buffer layer covering the scan wiring;
A semiconductor layer disposed on the buffer layer;
A gate insulating layer covering a channel region that is a central region of the semiconductor layer;
A gate electrode overlapping the channel region on the gate insulating layer and connected to the scan line;
An anode electrode disposed in the pixel area on the gate insulating layer;
An intermediate insulating layer covering the gate electrode and exposing most of the center of the anode electrode; And
A thin film transistor substrate comprising a data line disposed on the intermediate insulating layer in a direction to the other side of the pixel region.
The method of claim 1,
A first storage capacitor electrode that includes the same material as the scan wiring and is disposed at a position of a light blocking layer and an auxiliary capacitor disposed to overlap the semiconductor layer in the same layer;
A second storage capacitor electrode comprising the same material as the semiconductor layer and disposed at a position of the storage capacitor in the same layer; And
A source electrode comprising the same material as the data line, branching from the data line on the same layer and contacting one side of the semiconductor layer, and a predetermined distance apart from the source electrode to contact the other side of the semiconductor layer. A thin film transistor substrate further comprising a drain electrode and a third storage capacitor electrode extending from the drain electrode and overlapping the second storage capacitor electrode.
The method of claim 1,
A bank covering the data line and defining an opening area exposing most of the central portion of the anode electrode;
An organic light emitting layer stacked on the exposed anode electrode on the bank; And
A thin film transistor substrate further comprising a cathode electrode stacked on the organic emission layer.
The method of claim 1,
The gate electrode and the anode electrode are disposed on the same layer and include a transparent conductive material such as indium-tin-oxide.
Forming scan wirings on the substrate;
Applying a buffer layer on the surface of the substrate on which the scan wiring is formed, and forming a semiconductor layer on the buffer layer;
Forming a gate insulating layer covering a central portion and a pixel region of the semiconductor layer;
Forming a gate electrode overlapping the central portion of the semiconductor layer and an anode electrode disposed in the pixel region on the gate insulating layer;
Forming an intermediate insulating layer covering the gate electrode and the anode electrode;
Forming a data line crossing the scan line on the intermediate insulating layer; And
And forming a bank covering the data line and exposing most of the central portion of the anode electrode.

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