KR102199143B1 - Memory cell unit and memory cell array including the same - Google Patents

Abstract

The unit memory cell includes a high threshold voltage transistor and a normal threshold voltage transistor. The high threshold voltage transistor includes a first node connected to the write bit line to receive write data, a second node connected to the data node to transfer write data, a gate node connected to the write word line, and a body bias whose voltage level is adjusted. Includes voltage nodes. The normal threshold voltage transistor is a first node connected to a read bit line to receive a read current, a second node connected to a read word line to transfer a read current, a gate node connected to a data node, and a body bias whose voltage level is adjusted Includes voltage nodes. According to the unit memory cell, a leakage current of a transistor may be reduced and a retention time may be increased by adjusting a threshold voltage and a body bias voltage of the transistor.

Description

A unit memory cell and a memory cell array including the same

The present invention relates to a memory device, and more particularly, to a unit memory cell included in the memory device and a memory cell array including the same.

As mobile devices become smaller, it is becoming an important issue to reduce the size of embedded memory included in mobile devices.

Reducing the size of an embedded memory included in a mobile device is closely related to reducing the number of transistors in a memory cell included in the embedded memory device. When a memory cell is implemented by reducing the number of transistors, the leakage current of the transistor increases, thereby limiting the retention time.

An object of the present invention for solving the above problems is to provide a unit memory cell that reduces a leakage current of a transistor and increases a retention time by adjusting a threshold voltage and a body bias voltage of a transistor.

An object of the present invention for solving the above problems is to provide a memory cell array that reduces a leakage current of a transistor and increases a retention time by adjusting a threshold voltage and a body bias voltage of a transistor.

In order to achieve an object of the present invention, a unit memory cell according to an embodiment of the present invention includes a high threshold voltage transistor and a normal threshold voltage transistor. The high threshold voltage transistor includes a first node connected to a write bit line to receive write data, a second node connected to a data node to transfer write data, a gate node connected to a write word line, and a voltage level. Includes a body bias voltage node. The normal threshold voltage transistor is a first node connected to a read bit line to receive a read current, a second node connected to a read word line to transfer the read current, a gate node connected to the data node, and a voltage level are adjusted. Body bias voltage node.

In an exemplary embodiment, a threshold voltage value of the high threshold voltage transistor is greater than a threshold voltage value of a normal threshold voltage transistor, and a voltage of the body bias voltage node of the high threshold voltage transistor and the normal threshold voltage transistor is the unit memory It may be determined according to the operation mode of the memory device including the cell.

In an exemplary embodiment, when the memory device is operated in a write mode, a voltage applied to the write word line to turn on the high threshold voltage transistor is a power supply voltage and a threshold voltage of the high threshold voltage transistor. May be greater than the summed value.

In an exemplary embodiment, the voltages of the body bias voltage nodes of the high threshold voltage transistor and the normal threshold voltage transistor may maintain a negative voltage for a predetermined period of the entire period operating in the write mode.

In an exemplary embodiment, the body bias voltage node and the body bias voltage node and the voltage of the body bias voltage node of the high threshold voltage transistor and the normal threshold voltage transistor transition to a ground voltage after maintaining a negative voltage for the predetermined period. The voltage of the data node may be boosted based on the parasitic capacitor between the data nodes.

In an exemplary embodiment, voltages of the body bias voltage nodes of the high threshold voltage transistor and the normal threshold voltage transistor may have the same voltage value.

In an exemplary embodiment, when the memory device is operated in a read mode, voltages of the body bias voltage nodes of the high threshold voltage transistor and the normal threshold transistor may maintain a ground voltage.

In an exemplary embodiment, when the voltage of the data node is at the first level, the read current is transferred to the read word line by turning on the normal threshold voltage transistor, and the voltage of the data node is at the second level. In this case, the read current may be blocked by turning off the normal threshold voltage transistor.

In an exemplary embodiment, when the memory device operates in a standby mode, voltages of the body bias voltage nodes of the high threshold voltage transistor and the normal threshold transistor may maintain a ground voltage.

In order to achieve an object of the present invention, a memory cell array according to an embodiment of the present invention includes a plurality of write bit lines, a plurality of write word lines, a plurality of read bit lines, a plurality of read word lines, and a plurality of read word lines. It includes unit memory cells of. Each of the plurality of unit memory cells includes a high threshold voltage transistor and a normal threshold voltage transistor. The high threshold voltage transistor is a first node connected to a corresponding write bit line among the plurality of write bit lines to receive write data, a second node connected to a data node to transfer the write data, and the plurality of write bit lines Among the word lines, a gate node connected to a corresponding write word line and a body bias voltage node whose voltage level is adjusted are included. The normal threshold voltage transistor is connected to a first node to receive a read current by being connected to a corresponding read bit line among the plurality of read bit lines, and to a corresponding read word line from among the plurality of read word lines to receive the read current. And a second node that transmits a signal, a gate node connected to the data node, and a body bias voltage node whose voltage level is adjusted.

1 is a block diagram illustrating a unit memory cell according to embodiments of the present invention.
2 is a timing diagram illustrating a write mode of a memory device including a unit memory cell of FIG. 1.
3 is a diagram illustrating a parasitic capacitor between a data node and a body bias voltage node included in the unit memory cell of FIG. 1.
4 is a diagram illustrating a parasitic capacitor between a data node included in the unit memory cell of FIG. 1 and a gate node of a high threshold voltage transistor.
5 is a timing diagram illustrating a read mode of a memory device including a unit memory cell of FIG. 1.
6 is a timing diagram illustrating a standby mode of a memory device including a unit memory cell of FIG. 1.
7 is a block diagram illustrating a memory cell array according to example embodiments.
8 is a block diagram illustrating an example in which a memory device including a memory cell array according to example embodiments is applied to a mobile device.
9 is a block diagram illustrating an example in which a memory module including a memory cell array according to embodiments of the present invention is applied to a computing system.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions have been exemplified only for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be implemented in various forms. It is not to be construed as being limited to the embodiments described in.

Since the present invention can apply various changes and have various forms, specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific form of disclosure, it is to be understood as including all changes, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it may be directly connected or connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle. Other expressions describing the relationship between components, such as "between" and "just between" or "adjacent to" and "directly adjacent to" should be interpreted as well.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate the presence of a set feature, number, step, action, component, part, or combination thereof, and one or more other features or numbers It is to be understood that the possibility of addition or presence of, steps, actions, components, parts, or combinations thereof is not preliminarily excluded.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning of the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this application. .

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions for the same elements are omitted.

1 is a block diagram illustrating a unit memory cell according to example embodiments.

Referring to FIG. 1, a unit memory cell 10 includes a high threshold voltage transistor 100 and a normal threshold voltage transistor 200. The high threshold voltage transistor 100 includes a first node N1_M1, a second node N2_M1, a gate node G_M1, and a body bias voltage node BBN_M1, and the normal threshold voltage transistor 200 is a first node. (N1_M2), a second node (N2_M2), a gate node (G_M2), and a body bias voltage node (BBN_M2).

The first node N1_M1 of the high threshold voltage transistor may be connected to a write bit line (WBL) to receive write data. The second node N2_M1 of the high threshold voltage transistor 100 may be connected to the data node DN to transmit write data to the data node DN. The gate node G_M1 of the high threshold voltage transistor 100 may be connected to a write word line (WWL). The voltage level of the body bias voltage node BBN_M1 of the high threshold voltage transistor 100 may be adjusted.

When a memory device including the unit memory cell 10 operates in a write mode, the high threshold voltage transistor 100 may be turned on to write data to the unit memory cell 10. For example, when the data value of the write bit line WBL is 0 and the value of the write word line WWL is kept logic high, the high threshold voltage transistor 100 is turned on and the write bit line WBL is The data value 0 may be transferred to the second node N2_M1 of the high threshold voltage transistor 100 to store the data 0 in the data node DN. When the data value of the write bit line WBL is 1 and the value of the write word line WWL remains logic high, the high threshold voltage transistor is turned on to increase the data value 1 of the write bit line WBL to a high threshold. Data 1 may be stored in the data node DN by transferring it to the second node N2_M1 of the voltage transistor 100. Data stored in the data node DN may be stored in the parasitic capacitor 500 between the data node DN and the ground node.

When a memory device including the unit memory cell 10 operates in a write mode, a value of a read word line (RWL) may maintain a logic high. For example, when the value of the read word line RWL maintains a logic high, the value of the second node N2_M2 of the normal threshold voltage transistor 200 may be a logic high. The normal threshold voltage transistor must have a voltage difference greater than or equal to the threshold voltage of the normal threshold voltage transistor 200 between the gate node G_M2 of the normal threshold voltage transistor 200 and the second node N2_M2 of the normal threshold voltage transistor 200. 200) can be turned on. When the second node N2_M2 of the normal threshold voltage transistor 200 maintains a logic high, even if the value of the gate node G_M2 of the normal threshold voltage transistor 200 remains logic high, the normal threshold voltage transistor 200 is May not turn on. When the second node N2_M2 of the normal threshold voltage transistor 200 maintains a logic high, even if the value of the gate node G_M2 of the normal threshold voltage transistor 200 remains logic low, the normal threshold voltage transistor 200 is May not turn on. Therefore, if the value of the read word line RWL is kept at logic high while the memory device is operating in the write mode, it is possible to block simultaneous read operations while the memory device performs a write operation.

The first node N1_M2 of the normal threshold voltage transistor 200 may be connected to a read bit line (RBL) to receive a read current IRD. The second node N2_M2 of the normal threshold voltage transistor 200 is connected to the read word line RWL to transfer the read current IRD to the read word line RWL. The gate node G_M2 of the normal threshold voltage transistor 200 may be connected to the data node DN. The voltage level of the body bias voltage node BBN_M2 of the normal threshold voltage transistor 200 may be adjusted.

When a memory device including the unit memory cell 10 operates in a read mode, the normal threshold voltage transistor 200 may be turned on to read data from the unit memory cell 10. For example, when the value of the read word line RWL is 0 and the value of the data node DN is 1, the normal threshold voltage transistor 200 may be turned on. When the normal threshold voltage transistor 200 is turned on, a conduction path may be formed from the first node N1_M2 of the normal threshold voltage transistor 200 to the second node N2_M2 of the normal threshold voltage transistor 200. The read current IRD may be transmitted through a conduction path connected from the first node N1_M2 of the normal threshold voltage transistor 200 to the second node N2_M2 of the normal threshold voltage transistor 200. When the normal threshold voltage transistor 200 is turned on, a voltage value of the read bit line RBL may be lowered.

When the value of the read word line RWL is 0 and the value of the data node DN is 0, the normal threshold voltage transistor 200 may be turned off. When the normal threshold voltage transistor 200 is turned off, a conduction path may be blocked from the first node N1_M2 of the normal threshold voltage transistor 200 to the second node N2_M2 of the normal threshold voltage transistor 200. The read current IRD cannot be transmitted through a conduction path connected from the first node N1_M2 of the normal threshold voltage transistor 200 to the second node N2_M2 of the normal threshold voltage transistor 200. When the normal threshold voltage transistor 200 is turned off, the voltage value of the read bit line RBL may be kept constant. In this case, the voltage value of the read bit line RBL may be maintained as the power voltage.

When the memory device including the unit memory cell 10 operates in the read mode, the value of the write word line WWL may maintain a logic low. For example, when the value of the write word line WWL maintains a logic low, the high threshold voltage transistor 100 may be turned off. Therefore, if the value of the write word line WWL is kept at a logic low while the memory device is operating in the read mode, it is possible to block simultaneous write operations while the memory device performs a read operation.

The threshold voltage value of the high threshold voltage transistor 100 is greater than the threshold voltage value of the normal threshold voltage transistor 200, and the voltage of the body bias voltage node BBN_M2 of the high threshold voltage transistor and the normal threshold voltage transistor 200 is unit It may be determined according to the operation mode of the memory device including the memory cell 10. The threshold voltage of the high threshold voltage transistor 100 may be higher than the threshold voltage of the normal threshold voltage transistor 200. When the threshold voltage of the transistor is high, the leakage current generated in the transistor may decrease.

A memory device including the unit memory cell 10 may include a write mode, a read mode, and a standby mode. The body bias voltage (VBB) of the high threshold voltage transistor 100 and the body bias voltage (VBB) of the normal threshold voltage transistor 200 may be adjusted according to an operation mode of the memory device. When the body bias voltage VBB of the high threshold voltage transistor 100 and the body bias voltage VBB of the normal threshold voltage transistor 200 are adjusted, the retention time may be increased as described later.

The unit memory cell 10 according to the exemplary embodiments of the present invention may reduce a leakage current of a transistor and increase a retention time by adjusting a threshold voltage and a body bias voltage VBB of the transistor.

2 is a timing diagram illustrating a write mode of a memory device including a unit memory cell of FIG. 1.

Referring to FIG. 2, when a memory device including a unit memory cell 10 operates in a write mode, a voltage applied to the write word line WWL to turn on the high threshold voltage transistor 100 is a power supply. It may be greater than the sum of the voltage VDD and the threshold voltage of the high threshold voltage transistor 100.

For example, when the data value of the write bit line WBL is 1 and the value of the write word line WWL is kept logic high, the high threshold voltage transistor 100 is turned on to turn on the write bit line WBL. The data value 1 of is transmitted to the second node N2_M1 of the high threshold voltage transistor 100 to store the data 1 in the data node DN. In this case, if the voltage value corresponding to data 1 of the write bit line WBL is the power supply voltage VDD, the voltage value of data 1 stored in the data node DN is the high threshold voltage transistor at the power supply voltage VDD. It may be a voltage value obtained by subtracting the threshold voltage (Vth) of 100). Therefore, in order for the voltage value corresponding to data 1 stored in the data node DN to become the power supply voltage VDD, the voltage value applied to the write word line WWL is higher than the power supply voltage VDD, and the threshold voltage transistor 100 It may be greater than the sum of the threshold voltage Vth of.

3 is a diagram illustrating a parasitic capacitor between a data node and a body bias voltage node included in the unit memory cell of FIG. 1, and FIG. 4 is a data node included in the unit memory cell of FIG. 1 and a gate node of a high threshold voltage transistor. It is a diagram showing the parasitic capacitor between.

2, 3, and 4, the voltage of the body bias voltage node BBN_M2 of the high threshold voltage transistor 100 and the normal threshold voltage transistor 200 is negative for a certain period of the entire period operating in the write mode. The voltage of can be maintained.

In an exemplary embodiment, the voltage of the body bias voltage node BBN_M2 of the high threshold voltage transistor 100 and the normal threshold voltage transistor 200 maintains a negative voltage for a predetermined period and then transitions to the ground voltage VSS. Accordingly, the voltage of the data node DN may be boosted based on the parasitic capacitor C_DB 510 between the body bias voltage node BBN and the data node DN.

When the memory device operates in the write mode, the body bias voltage VBB of the high threshold voltage transistor 100 and the body bias voltage VBB of the normal threshold voltage transistor 200 change from the ground voltage VSS to a negative voltage. Transition is possible. When the body bias voltage VBB of the high threshold voltage transistor 100 and the body bias voltage VBB of the normal threshold voltage transistor 200 transition to a negative voltage, the body bias voltage node BBN and the data node DN The voltage value of the data node DN may be lowered by the parasitic capacitor 510 between ). Next, when the voltage value of the write word line WWL is higher than the power supply voltage VDD and transitions above the threshold voltage of the threshold voltage transistor 100, the high threshold voltage transistor 100 is turned on to turn on the write bit line WBL. Data can be delivered to the data node (DN). For example, when the high threshold voltage transistor 100 is turned on and the write data is 1, the voltage value of the data node DN may transition to the power voltage VDD. When the high threshold voltage transistor 100 is turned on and the write data is 0, the voltage value of the data node DN may transition to the ground voltage VSS.

Next, when the voltage value of the write word line WWL transitions to the ground voltage VSS from the power voltage VDD plus the threshold voltage of the high threshold voltage transistor 100, the data node DN and the high threshold The voltage value of the data node DN may be lowered by the parasitic capacitor C_DG 530 between the gate node G_M1 of the voltage transistor 100. Next, when the body bias voltage VBB of the high threshold voltage transistor 100 and the body bias voltage VBB of the normal threshold voltage transistor 200 transition from the negative voltage to the ground voltage VSS, the body bias voltage node The voltage value of the data node DN may increase due to the parasitic capacitor 510 between the BBN and the data node DN. A voltage drop may occur in the data node DN while transitioning from the voltage value of the write word line WWL added by the power voltage VDD to the threshold voltage of the high threshold voltage transistor 100 to the ground voltage VSS. . In addition, while the body bias voltage VBB transitions from the negative voltage to the ground voltage VSS, the voltage at the data node DN may increase. The voltage drop occurring when the voltage value of the write word line WWL transitions to the ground voltage VSS from the power voltage VDD plus the threshold voltage of the high threshold voltage transistor 100 is the body bias voltage VBB. It may be compensated by increasing the voltage at the data node DN while transitioning from the negative voltage to the ground voltage VSS. Accordingly, according to the unit memory cell 10 according to the present invention, the voltage applied to the write word line WWL is set to a value greater than the value obtained by adding the threshold voltage of the high threshold voltage transistor 100 to the power supply voltage VDD. Data 1 corresponding to the power supply voltage VDD can be written in (DN).

In an exemplary embodiment, the voltages of the body bias voltage node BBN_M2 of the high threshold voltage transistor 100 and the normal threshold voltage transistor 200 may have the same voltage value. The body bias voltage node BBN_M1 of the high threshold voltage transistor 100 and the body bias voltage node BBN_M2 of the normal threshold voltage transistor 200 may be connected to each other and adjusted to the same voltage. In this case, the high threshold voltage transistor 100 and the normal threshold voltage transistor 200 may be configured as triple wells to be separated from the ground voltage VSS.

The unit memory cell 10 according to the exemplary embodiments of the present invention may reduce a leakage current of a transistor and increase a retention time by adjusting a threshold voltage and a body bias voltage VBB of the transistor.

5 is a timing diagram illustrating a read mode of a memory device including a unit memory cell of FIG. 1.

Referring to FIGS. 1 and 5, when the memory device operates in a read mode, the voltages of the body bias voltage nodes BBN_M1 and BBN_M2 of the high threshold voltage transistor 100 and the normal threshold transistor 200 are the ground voltage VSS ) Can be maintained.

When a memory device including the unit memory cell 10 operates in a read mode, the normal threshold voltage transistor 200 may be turned on to read data from the unit memory cell 10. For example, when the value of the read word line RWL is 0 and the value of the data node DN is 1, the normal threshold voltage transistor 200 may be turned on. When the normal threshold voltage transistor 200 is turned on, a conduction path may be formed from the first node N1_M2 of the normal threshold voltage transistor 200 to the second node N2_M2 of the normal threshold voltage transistor 200. The read current IRD may be transmitted through a conduction path connected from the first node N1_M2 of the normal threshold voltage transistor 200 to the second node N2_M2 of the normal threshold voltage transistor 200. When the normal threshold voltage transistor 200 is turned on, a voltage value of the read bit line RBL may be lowered. The voltage value of the read bit line RBL may be lower than the power voltage VDD by the threshold voltage of the normal threshold voltage transistor 200.

When the value of the read word line RWL is 0 and the value of the data node DN is 0, the normal threshold voltage transistor 200 may be turned off. When the normal threshold voltage transistor 200 is turned off, a conduction path may be blocked from the first node N1_M2 of the normal threshold voltage transistor 200 to the second node N2_M2 of the normal threshold voltage transistor 200. The read current IRD cannot be transmitted through a conduction path connected from the first node N1_M2 of the normal threshold voltage transistor 200 to the second node N2_M2 of the normal threshold voltage transistor 200. When the normal threshold voltage transistor 200 is turned off, the voltage value of the read bit line RBL may be kept constant. In this case, the voltage value of the read bit line RBL may be maintained as the power voltage VDD.

In an exemplary embodiment, when the voltage of the data node DN is at the first level, the normal threshold voltage transistor 200 is turned on to transmit the read current IRD to the read word line RWL, and the data When the voltage of the node DN is at the second level, the normal threshold voltage transistor 200 is turned off to block the read current IRD. For example, the first level can be logic high and the second level can be logic low.

6 is a timing diagram illustrating a standby mode of a memory device including a unit memory cell of FIG. 1.

Referring to FIG. 6, when the memory device operates in the standby mode, the voltages of the body bias voltage nodes BBN_M1 and BBN_M2 of the high threshold voltage transistor 100 and the normal threshold transistor 200 maintain the ground voltage VSS. I can. The memory device operates in the standby mode except when performing an operation of writing data to the memory device or performing an operation of reading data from the memory device. In this case, the body bias voltage VBB maintains the ground voltage VSS, and data stored in the data node DN does not change.

7 is a block diagram illustrating a memory cell array according to example embodiments.

1 and 7, the memory cell array 20 includes a plurality of write bit lines WBL1 and WBL2, a plurality of write word lines WWL1 to WWL3, and a plurality of read bit lines RBL1 and RBL2. ), a plurality of read word lines RWL1 to RWL3, and a plurality of unit memory cells 10. Each unit memory cell 10 among the plurality of unit memory cells 10 includes a high threshold voltage transistor 100 and a normal threshold voltage transistor 200.

The first node N1_M1 of the high threshold voltage transistor 100 may be connected to a corresponding write bit line among the plurality of write bit lines WBL1 to WBL3 to receive write data. The second node N2_M1 of the high threshold voltage transistor 100 may be connected to the data node DN to transmit write data. The gate node G_M1 of the high threshold voltage transistor 100 may be connected to a corresponding write word line among the plurality of write word lines. The voltage level of the body bias voltage node BBN_M1 of the high threshold voltage transistor 100 may be adjusted.

When a memory device including the unit memory cell 10 operates in a write mode, the high threshold voltage transistor 100 may be turned on to write data to the unit memory cell 10. For example, when the data value of the write bit line is 0 and the value of the write word line is kept logic high, the high threshold voltage transistor 100 is turned on to increase the data value of the write bit line 0, and the threshold voltage transistor ( Data 0 may be stored in the data node DN by transferring it to the second node N2_M1 of 100). When the data value of the write bit line is 1 and the value of the write word line is kept logic high, the high threshold voltage transistor 100 is turned on to change the data value 1 of the write bit line to the high threshold voltage transistor 100. Data 1 may be stored in the data node DN by transferring it to the second node N2_M1.

When the memory device including the unit memory cell 10 operates in the write mode, the value of the read word line may maintain a logic high. For example, when the value of the read word line is kept at logic high, the value of the second node N2_M2 of the normal threshold voltage transistor 200 may be logic high. The normal threshold voltage transistor must have a voltage difference greater than or equal to the threshold voltage of the normal threshold voltage transistor 200 between the gate node G_M2 of the normal threshold voltage transistor 200 and the second node N2_M2 of the normal threshold voltage transistor 200. 200) can be turned on. When the second node N2_M2 of the normal threshold voltage transistor 200 maintains a logic high, even if the value of the gate node G_M2 of the normal threshold voltage transistor 200 remains logic high, the normal threshold voltage transistor 200 is May not turn on. When the second node N2_M2 of the normal threshold voltage transistor 200 maintains a logic high, even if the value of the gate node G_M2 of the normal threshold voltage transistor 200 remains logic low, the normal threshold voltage transistor 200 is May not turn on. Therefore, if the value of the read word line is kept at logic high while the memory device is operating in the write mode, it is possible to block simultaneous read operations while the memory device performs a write operation.

The first node N1_M2 of the normal threshold voltage transistor 200 may be connected to a corresponding read bit line among the plurality of read bit lines RBL1 and RBL2 to receive the read current IRD. The second node N2_M2 of the normal threshold voltage transistor 200 may be connected to a corresponding read word line among the plurality of read word lines to transmit the read current IRD. The gate node G_M2 of the normal threshold voltage transistor 200 may be connected to the data node DN. The voltage level of the body bias voltage node BBN_M2 of the normal threshold voltage transistor 200 may be adjusted.

When a memory device including the unit memory cell 10 operates in a read mode, the normal threshold voltage transistor 200 may be turned on to read data from the unit memory cell 10. For example, when the value of the read word line is 0 and the value of the data node DN is 1, the normal threshold voltage transistor 200 may be turned on. When the normal threshold voltage transistor 200 is turned on, a conduction path may be formed from the first node N1_M2 of the normal threshold voltage transistor 200 to the second node N2_M2 of the normal threshold voltage transistor 200. The read current IRD may be transmitted through a conduction path connected from the first node N1_M2 of the normal threshold voltage transistor 200 to the second node N2_M2 of the normal threshold voltage transistor 200. When the normal threshold voltage transistor 200 is turned on, the voltage value of the read bit line may decrease.

When the value of the read word line is 0 and the value of the data node DN is 0, the normal threshold voltage transistor 200 may be turned off. When the normal threshold voltage transistor 200 is turned off, a conduction path may be blocked from the first node N1_M2 of the normal threshold voltage transistor 200 to the second node N2_M2 of the normal threshold voltage transistor 200. The read current IRD cannot be transmitted through a conduction path connected from the first node N1_M2 of the normal threshold voltage transistor 200 to the second node N2_M2 of the normal threshold voltage transistor 200. When the normal threshold voltage transistor 200 is turned off, the voltage value of the read bit line may be kept constant. In this case, the voltage value of the read bit line may be maintained as the power supply voltage VDD.

When a memory device including the unit memory cell 10 operates in a read mode, a value of the write word line may maintain a logic low. For example, when the value of the write word line remains at a logic low, the high threshold voltage transistor 100 may be turned off. Therefore, if the value of the write word line is kept at a logic low while the memory device is operating in the read mode, it is possible to block simultaneous write operations while the memory device performs a read operation.

The threshold voltage value of the high threshold voltage transistor 100 is greater than the threshold voltage value of the normal threshold voltage transistor 200, and the body bias voltage node BBN_M2 of the high threshold voltage transistor 100 and the normal threshold voltage transistor 200 is The voltage may be determined according to an operation mode of the memory device including the unit memory cell 10. The threshold voltage of the high threshold voltage transistor 100 may be higher than the threshold voltage of the normal threshold voltage transistor 200. When the threshold voltage of the transistor is high, the leakage current generated in the transistor may decrease.

A memory device including the unit memory cell 10 may include a write mode, a read mode, and a standby mode. The body bias voltage VBB of the high threshold voltage transistor 100 and the body bias voltage VBB of the normal threshold voltage transistor 200 may be adjusted according to an operation mode of the memory device. When the body bias voltage VBB of the high threshold voltage transistor 100 and the body bias voltage VBB of the normal threshold voltage transistor 200 are adjusted, the retention time may be increased as described later.

The memory cell array 20 according to embodiments of the present invention may reduce a leakage current of a transistor and increase a retention time by adjusting a threshold voltage and a body bias voltage VBB of the transistor.

8 is a block diagram illustrating an example in which a memory device including a memory cell array according to example embodiments is applied to a mobile device.

Referring to FIG. 8, the mobile device 700 may include a processor 710, a memory device 720, a storage device 730, an image sensor 760, a display device 740, and a power supply 750. have. The mobile device 700 may further include ports capable of communicating with a video card, a sound card, a memory card, a USB device, or the like, or with other electronic devices.

The processor 710 may perform specific calculations or tasks. Depending on the embodiment, the processor 710 may be a micro-processor or a central processing unit (CPU). The processor 710 may communicate with the memory device 720, the storage device 730, and the display device 740 through an address bus, a control bus, and a data bus. have. Depending on the embodiment, the processor 710 may also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus. The memory device 720 may store data necessary for the operation of the mobile device 700. For example, the memory device 720 is implemented by including DRAM, mobile DRAM, SRAM, PRAM, FRAM, RRAM, and/or MRAM. Can be. The storage device 730 may include a solid state drive, a hard disk drive, a CD-ROM, or the like. The mobile device 700 may further include an input means such as a keyboard, a keypad, and a mouse, and an output means such as a printer. The power supply 750 may supply an operating voltage required for the operation of the mobile device 700.

The memory cell array 20 according to embodiments of the present invention may reduce a leakage current of a transistor and increase a retention time by adjusting a threshold voltage and a body bias voltage VBB of the transistor.

The image sensor 760 may be connected to the processor 710 through the buses or other communication links to perform communication. The image sensor 900 may be integrated on one chip together with the processor 710 or may be integrated on different chips.

Components of the mobile device 700 may be implemented in various types of packages. For example, at least some of the components of the mobile device 700 are PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package. (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board(COB), Ceramic Dual In-Line Package(CERDIP), Plastic Metric Quad Flat Pack(MQFP), Thin Quad Flatpack(TQFP), Small Outline( SOIC), Shrink Small Outline Package(SSOP), Thin Small Outline(TSOP), Thin Quad Flatpack(TQFP), System In Package(SIP), Multi Chip Package(MCP), Wafer-level Fabricated Package(WFP), Wafer- It can be implemented using packages such as Level Processed Stack Package (WSP).

Meanwhile, the mobile device 700 should be interpreted as any computing system using the memory system according to the embodiments of the present invention. For example, the mobile device 700 may include a digital camera, a mobile phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a smart phone, and the like.

9 is a block diagram illustrating an example in which a memory system according to embodiments of the present invention is applied to a computing system.

Referring to FIG. 9, the computing system 800 includes a processor 810, an input/output hub 820, an input/output controller hub 830, at least one memory module 840, and a graphics card 850. Depending on the embodiment, the computing system 800 is a personal computer (PC), a server computer (Server Computer), a workstation (Workstation), a laptop (Laptop), a mobile phone (Mobile Phone), a smart phone (Smart Phone) , Personal digital assistant (PDA), portable multimedia player (PMP), digital camera, digital TV, set-top box, music player (Music Player), portable game console (portable game console), may be any computing system such as a navigation (Navigation) system.

Processor 810 may perform various computing functions, such as specific calculations or tasks. For example, the processor 810 may be a microprocessor or a central processing unit (CPU). Depending on the embodiment, the processor 810 may include one processor core (Single Core), or may include a plurality of processor cores (Multi-Core). For example, the processor 1510 may include a multi-core such as a dual-core, a quad-core, and a hexa-core. In addition, although the computing system 800 including one processor 810 is illustrated in FIG. 18, the computing system 800 may include a plurality of processors according to an embodiment. Also, according to an embodiment, the processor 810 may further include a cache memory located inside or outside.

The processor 810 may include a memory controller 811 that controls the operation of the memory module 840. The memory controller 811 included in the processor 810 may be referred to as an integrated memory controller (IMC). The memory interface between the memory controller 811 and the memory module 840 may be implemented as one channel including a plurality of signal lines, or may be implemented as a plurality of channels. In addition, one or more memory modules 840 may be connected to each channel. According to an embodiment, the memory controller 811 may be located in the input/output hub 820. The input/output hub 820 including the memory controller 811 may be referred to as a memory controller hub (MCH).

The memory module 840 may include a plurality of memory devices that store data provided from the memory controller 811. The memory devices are connected to the memory controller 811 via a first set of memory devices constituting a first rank directly connected to the memory controller 811 and the memory devices of the first set, and at least a second rank And a second set of memory devices constituting a. Therefore, since the memory controller 811 only needs to load the memory devices corresponding to the first rank RNK0, the number of ranks can be increased without reducing the operating speed of the memory module 840.

The input/output hub 820 may manage data transmission between devices such as the graphics card 850 and the processor 810. The input/output hub 820 may be connected to the processor 810 through various types of interfaces. For example, the input/output hub 820 and the processor 810 may include a front side bus (FSB), a system bus, a hypertransport, and a lightning data transport; LDT), QuickPath Interconnect (QPI), and Common System Interface (CSI).

The input/output hub 820 may provide various interfaces with devices. For example, the input/output hub 820 includes an Accelerated Graphics Port (AGP) interface, a Peripheral Component Interface-Express (PCIe), a Communication Streaming Architecture (CSA) interface, etc. Can provide.

The graphics card 850 may be connected to the input/output hub 820 through AGP or PCIe. The graphic card 850 may control a display device (not shown) for displaying an image. The graphics card 850 may include an internal processor for processing image data and an internal semiconductor memory device. Depending on the embodiment, the input/output hub 820 may include a graphic device inside the input/output hub 820 with the graphic card 850 located outside the input/output hub 820 or instead of the graphic card 850. I can. The graphic device included in the input/output hub 820 may be referred to as integrated graphics. Further, the input/output hub 820 including a memory controller and a graphic device may be referred to as a graphics and memory controller hub (GMCH).

The input/output controller hub 830 may perform data buffering and interface arbitration so that various system interfaces operate efficiently. The input/output controller hub 830 may be connected to the input/output hub 820 through an internal bus. For example, the input/output hub 820 and the input/output controller hub 830 may be connected through a direct media interface (DMI), a hub interface, an Enterprise Southbridge Interface (ESI), PCIe, or the like. .

The input/output controller hub 830 may provide various interfaces with peripheral devices. For example, the input/output controller hub 830 includes a Universal Serial Bus (USB) port, a Serial Advanced Technology Attachment (ATA) port, a General Purpose Input/Output (GPIO), and a low pin count. (Low Pin Count; LPC) bus, Serial Peripheral Interface (SPI), PCI, PCIe, etc. can be provided.

Depending on the embodiment, the processor 810, the input/output hub 820, and the input/output controller hub 830 are each implemented as separate chipsets or integrated circuits, or the processor 810, the input/output hub 820, or the input/output controller hub Two or more of the components 830 may be implemented as one chipset.

The memory cell array 20 according to embodiments of the present invention may reduce a leakage current of a transistor and increase a retention time by adjusting a threshold voltage and a body bias voltage VBB of the transistor.

The memory cell array according to the exemplary embodiments of the present invention can reduce a leakage current of a transistor and increase a retention time, and thus can be applied to semiconductor devices using a memory cell array.

In the above, the present invention has been described with reference to preferred embodiments, but those skilled in the art will be able to variously modify and change the present invention within the scope not departing from the spirit and scope of the present invention described in the following claims. You will understand that you can.

Claims (10)

A high threshold voltage transistor connected between a write bit line receiving write data and a data node, and having a gate connected to the write word line; And
A normal threshold voltage transistor connected between a read bit line receiving a read current and a read word line, a gate connected to the data node, and having a threshold voltage less than a threshold voltage of the high threshold voltage transistor,
A unit memory cell, characterized in that the body bias voltage of the high threshold voltage transistor and the body bias voltage of the normal threshold voltage transistor are determined according to an operation mode of a memory device including the high threshold voltage transistor and the normal threshold voltage transistor. . delete The method of claim 1, wherein when operating in a write mode,
A unit memory cell, wherein a voltage applied to the write word line to turn on the high threshold voltage transistor is greater than a sum of a power supply voltage and a threshold voltage of the high threshold voltage transistor. The method of claim 1,
The unit memory cell, wherein the body bias voltage of the high threshold voltage transistor and the body bias voltage of the normal threshold voltage transistor maintain negative voltages during at least a partial period of an entire period operating in a write mode. The method of claim 4,
And boosting a voltage of the data node as the body bias voltage of the high threshold voltage transistor and the body bias voltage of the normal threshold voltage transistor maintain the negative voltage and then transition to a ground voltage. Cell. The method of claim 5,
The unit memory cell, wherein the body bias voltage of the high threshold voltage transistor and the body bias voltage of the normal threshold voltage transistor are the same. The method of claim 1, wherein when operating in a read mode,
And a body bias voltage of the high threshold voltage transistor and a body bias voltage of the normal threshold voltage transistor maintain a ground voltage. The method of claim 7,
When the voltage of the data node is at the first level, the normal threshold voltage transistor is turned on so that the read current is transferred to the read word line,
When the voltage of the data node is at the second level, the normal threshold voltage transistor is turned off to block the read current. The method of claim 1, wherein when operating in a standby mode,
A unit memory cell, wherein the body bias voltage of the high threshold voltage transistor and the body bias voltage of the normal threshold transistor maintain a ground voltage. A plurality of write bit lines;
A plurality of write word lines;
A plurality of read bit lines;
A plurality of read word lines; And
Including a plurality of unit memory cells,
Each of the plurality of unit memory cells is
A high threshold voltage transistor connected between a write bit line receiving write data and a data node, and having a gate connected to the write word line; And
A normal threshold voltage transistor connected between a read bit line receiving a read current and a read word line, a gate connected to the data node, and having a threshold voltage less than a threshold voltage of the high threshold voltage transistor,
And a body bias voltage of the high threshold voltage transistor and a body bias voltage of the normal threshold voltage transistor are determined according to an operation mode of a memory device including the unit memory cell.

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