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KR102196385B1 - 반도체 패키지 - Google Patents

반도체 패키지 Download PDF

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Publication number
KR102196385B1
KR102196385B1 KR1020200053229A KR20200053229A KR102196385B1 KR 102196385 B1 KR102196385 B1 KR 102196385B1 KR 1020200053229 A KR1020200053229 A KR 1020200053229A KR 20200053229 A KR20200053229 A KR 20200053229A KR 102196385 B1 KR102196385 B1 KR 102196385B1
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South Korea
Prior art keywords
metal
layer
conductor
metal layer
conductive metal
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KR1020200053229A
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English (en)
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최윤화
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제엠제코(주)
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Priority to KR1020200053229A priority Critical patent/KR102196385B1/ko
Application granted granted Critical
Publication of KR102196385B1 publication Critical patent/KR102196385B1/ko
Priority to CN202011619333.4A priority patent/CN113611683B/zh
Priority to US17/144,057 priority patent/US11393744B2/en
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Abstract

본 발명은, 전기적 연결이 가능하도록 특정 패턴이 형성된 하나 이상의 기판; 상기 기판 상부에 마련되며, 1차 전도성 금속층이 있는 하면과, 2차 전도성 금속층이 있는 상면을 포함하는 하나 이상의 반도체 칩; 일단은 상기 1차 전도성 금속층 또는 상기 2차 전도성 금속층과 전기적으로 연결되고, 타단은 터미널단자와 전기적으로 연결되며, 최외각 접촉면의 적어도 한 면 이상에 전도체 도금층이 도금된, 전도체; 상기 1차 전도성 금속층 또는 상기 2차 전도성 금속층에 접촉하도록 형성된 하나 이상의 금속분말층; 및 상기 터미널단자를 외부로 노출시키고, 상기 기판과 상기 반도체 칩과 상기 전도체와 상기 금속분말층을 패키징하는 패키지 하우징;을 포함하고, 상기 전도체는 상기 1차 전도성 금속층이 있는 상기 반도체 칩의 하면 또는 상기 2차 전도성 금속층이 있는 상기 반도체 칩의 상면과 전기적으로 연결되어 상기 기판 또는 터미널단자와 전기적으로 연결하여서, 기판 및 전도체와 열팽창특성이 유사한 금속분말층을 사용한 접합구조를 형성하여 접합부의 신뢰성을 향상시키는, 반도체 패키지를 개시한다.

Description

반도체 패키지{SEMICONDUCTOR PACKAGE}
본 발명은 기판 및 전도체와 유사한 열팽창계수를 갖는 금속분말층을 이루는 금속알갱이를 통해 접합구조를 형성하여서, 크랙발생을 최소화하여 접합부의 신뢰성을 향상시킬 수 있는, 반도체 패키지에 관한 것이다.
일반적으로, 반도체 패키지는, 기판 상에 반도체 칩, 반도체 칩 상에 접착되는 메탈포스트인 전도체, Cu로 구성되는 리드프레임 및 봉지재로 몰딩된 하우징을 포함하여 구성되며, 반도체 칩은 리드프레임 패드 상에 부착되고, 리드프레임 리드와는 Ag로 구성되는 도금층을 개재하여 신호선인 본딩 와이어에 의해 반도체 칩의 패드와 전기적으로 연결된다.
한편, 반도체 칩은 기판 및 전도체와 각각 솔더를 개재하여 접합되는데, 각 소재의 상이한 열팽창계수(CTE;Coefficient of Thermal Expansion)로 인해 접합부에서 크랙(crack)이 발생하는 문제점이 있다.
도 7은 종래기술에 의한 솔더를 사용한 반도체 패키지 접합구조에서 발생하는 크랙의 SEM 사진을 예시한 것으로, 반도체 패키지는 동작여부에 따라 발열과 냉각을 반복하여 소재별 열팽창계수의 차이로 인해, 도 7의 오른쪽 SEM 사진과 같이 크랙이 발생한다.
즉, 구리를 포함하는 기판(10)과 반도체 칩(20) 사이에 개재된 솔더(30)의 신뢰성이 부족하여 솔더로 이루어진 접합부가 깨져 전기적 특성이 저하된다.
이에, 접합구조를 개선하여 크랙발생을 최소화하여서 접합부의 신뢰성을 향상시킬 수 있는 기술이 요구된다.
한국 등록특허공보 제1643332호 (초음파 웰딩을 이용한 클립 본딩 반도체 패키지 및 그 제조 방법, 2016.07.21) 한국 등록특허공보 제10-0867573호 (열방출 능력이 개선된 전력용 모듈 패키지 및 그 제조 방법, 2008.11.10) 한국 공개특허공보 제2001-0111736호 (리드프레임의 배면에 직접 부착되는 절연방열판을구비하는 전력 모듈 패키지, 2001.12.20)
본 발명의 사상이 이루고자 하는 기술적 과제는, 기판 및 전도체와 유사한 열팽창계수를 갖는 금속분말층을 이루는 금속알갱이를 통해 접합구조를 형성하여서, 크랙발생을 최소화하여 접합부의 신뢰성을 향상시킬 수 있는, 반도체 패키지를 제공하는데 있다.
전술한 목적을 달성하고자, 본 발명의 일 실시예는, 전기적 연결이 가능하도록 특정 패턴이 형성된 하나 이상의 기판; 상기 기판 상부에 마련되며, 1차 전도성 금속층이 있는 하면과, 2차 전도성 금속층이 있는 상면을 포함하는 하나 이상의 반도체 칩; 일단은 상기 1차 전도성 금속층 또는 상기 2차 전도성 금속층과 전기적으로 연결되고, 타단은 터미널단자와 전기적으로 연결되며, 최외각 접촉면의 적어도 한 면 이상에 전도체 도금층이 도금된, 전도체; 상기 1차 전도성 금속층 또는 상기 2차 전도성 금속층에 접촉하도록 형성된 하나 이상의 금속분말층; 및 상기 터미널단자를 외부로 노출시키고, 상기 기판과 상기 반도체 칩과 상기 전도체와 상기 금속분말층을 패키징하는 패키지 하우징;을 포함하고, 상기 전도체는 상기 1차 전도성 금속층이 있는 상기 반도체 칩의 하면 또는 상기 2차 전도성 금속층이 있는 상기 반도체 칩의 상면과 전기적으로 연결되어 상기 기판 또는 터미널단자와 전기적으로 연결되는, 반도체 패키지를 제공한다.
여기서, 상기 금속분말층은 금속분말을 포함하고, 상기 1차 전도성 금속층과 전기적으로 연결되도록 접촉하는 1차 금속분말층과, 상기 2차 전도성 금속층과 전기적으로 연결되도록 접촉하는 2차 금속분말층을 포함할 수 있다.
또한, 상기 금속분말층을 이루는 금속분말은 금속알갱이일 수 있다.
여기서, 상기 금속알갱이는 Ag 또는 Cu의 단일 소재로 구성되거나, Ag, Au, Cu 및 Ni 중 어느 하나 이상이 70% 이상으로 포함될 수 있다.
또한, 상기 금속알갱이들 사이에는 다른 금속물질이 채워지지 않은 하나 이상의 공극이 존재할 수 있다.
여기서, 상기 공극의 크기는 1㎛ 이하인 것이 하나 이상일 수 있다.
또한, 하나 이상의 상기 기판은 하나 이상의 절연층을 포함할 수 있다.
또한, 상기 1차 전도성 금속층 또는 상기 2차 전도성 금속층은 1층 이상의 금속층으로 적층 형성되고, 상기 금속층은 Al, Ag, Au, Pd, Ni 또는 Cu의 단일 소재이거나, Al, Ag, Au, Pd, Ni 및 Cu 중 어느 하나 이상의 성분이 70% 이상 함유된 합금일 수 있다.
여기서, 상기 금속분말층과 접촉하는 상기 1차 전도성 금속층 또는 상기 2차 전도성 금속층의 최외각 금속층은 Ni, Ag, Au, Al 또는 Cu의 단일 소재이거나, Ni, Ag, Au, Al 및 Cu 중 어느 하나 이상의 성분이 10% 내지 80% 이상 함유된 합금일 수 있다.
또한, 상기 전도체는 금속분말 형태의 금속알갱이 또는 비금속분말 형태의 비금속알갱이로 이루어질 수 있다.
여기서, 상기 금속알갱이 또는 상기 비금속알갱이는 Mo, Cu, Mn, Al 또는 SiC의 단일 소재로 구성되거나, Mo, Cu, Mn, Al 및 SiC 중 어느 하나 이상의 소재의 금속알갱이 또는 비금속알갱이가 혼합된 분말 형태로 이루어질 수 있다.
또한, 상기 전도체는, 1㎛ 내지 50㎛ 크기의 분말 형태의 금속알갱이를 70% 이상 함유하거나, 1㎛ 내지 50㎛ 크기의 분말 형태의 비금속알갱이를 70% 이상 함유할 수 있다.
또한, 상기 전도체 도금층은 Ag, Au, Ni, Cu 또는 Sn의 단일 소재로 구성되거나, Ag, Au, Ni, Cu 및 Sn 중 어느 하나 이상을 50% 이상 함유한 합금일 수 있다.
또한, 상기 전도체 도금층은 1층 이상으로 적층형성될 수 있다.
여기서, 상기 전도체 도금층의 두께는 2㎛ 이상일 수 있다.
또한, 상기 1차 금속분말층은, 상기 1차 전도성 금속층과 상기 반도체 칩의 하면을 감싸도록 형성되고, 상기 반도체 칩 측면에 5㎛ 이상의 높이로 붙어 있을 수 있다.
또한, 상기 2차 금속분말층은, 상기 전도체의 하면을 감싸도록 형성되고, 상기 전도체 측면에 5㎛ 이상의 높이로 붙어 있을 수 있다.
또한, 상기 금속분말층은, 상기 금속알갱이가 상기 하나 이상의 반도체 칩의 하면의 상기 1차 전도성 금속층과 접촉하는 1차 금속분말층을 포함할 수 있다.
또한, 상기 금속분말층은, 상기 금속알갱이가 상기 하나 이상의 반도체 칩의 상면의 상기 2차 전도성 금속층과 접촉하는 2차 금속분말층을 포함할 수 있다.
또한, 상기 금속알갱이는 가로직경과 세로직경이 서로 다르게 형성될 수 있다.
여기서, 상기 금속알갱이의 가로직경과 세로직경 중 짧은 쪽의 직경이 2㎛ 이하인 금속알갱이가 전체 금속알갱이 수의 20% 이상으로 형성될 수 있다.
본 발명에 의하면, 종래의 솔더를 사용한 반도체 패키지 접합구조에 비해서, Cu 성분을 대부분 함유하여 기판 및 전도체와 유사한 열팽창계수를 갖는 금속분말층을 이루는 금속알갱이를 통해 접합구조를 형성하여서, 기판과 1차 전도성 금속층 사이, 및 2차 전도성 금속층과 전도체 사이의 크랙발생을 최소화하여 접합부의 신뢰성을 향상시킬 수 있는 효과가 있다.
도 1은 본 발명의 일 실시예에 의한 반도체 패키지의 단면구조를 각각 도시한 것이다.
도 2는 도 1의 반도체 패키지의 접합부의 단면구조를 분리 도시한 것이다.
도 3은 도 2의 반도체 패키지의 금속분말층의 SEM 사진을 예시한 것이다.
도 4는 도 2의 반도체 패키지의 단면구조의 SEM 사진을 예시한 것이다.
도 5는 도 2의 반도체 패키지의 반도체 칩과 전도체의 접합구조의 SEM 사진을 예시한 것이다.
도 6은 도 2의 반도체 패키지의 반도체 칩과 금속분말층의 접합구조의 FIB 사진을 예시한 것이다.
도 7은 종래기술에 의한 솔더를 사용한 반도체 패키지 접합구조에서 발생하는 크랙의 SEM 사진을 예시한 것이다.
이하, 첨부한 도면을 참고로 하여 본 발명의 실시예에 대하여 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 용이하게 실시할 수 있도록 상세히 설명한다. 본 발명은 여러 가지 상이한 형태로 구현될 수 있으며 여기에서 설명하는 실시예에 한정되지 않는다.
본 발명은 특정 패턴이 형성된 하나 이상의 기판, 기판 상부에 마련되며, 1차 전도성 금속층이 있는 하면과, 2차 전도성 금속층이 있는 상면을 포함하는 하나 이상의 반도체 칩, 일단은 1차 전도성 금속층 또는 2차 전도성 금속층과 전기적으로 연결되고, 타단은 터미널단자와 전기적으로 연결되며, 최외각 접촉면의 적어도 한 면 이상에 전도체 도금층이 도금된, 전도체, 1차 전도성 금속층 또는 상기 2차 전도성 금속층에 접촉하도록 형성된 하나 이상의 금속분말층, 그리고 터미널단자를 외부로 노출시키고, 기판과 반도체 칩과 전도체와 금속분말층을 패키징하는 패키지 하우징을 포함하고, 전도체는 1차 전도성 금속층이 있는 반도체 칩의 하면 또는 2차 전도성 금속층이 있는 반도체 칩의 상면과 전기적으로 연결되어 기판 또는 터미널단자와 전기적으로 연결되는, 반도체 패키지를 제공한다.
도 1 내지 도 6을 참조하면, 본 발명의 일 실시예에 의한 반도체 패키지는, 전체적으로, 패턴이 형성된 기판(110)과, 기판(110) 상에 마련되며 1차 전도성 금속층(130)이 있는 하면과, 2차 전도성 금속층(150)이 있는 상면을 포함하는 반도체 칩(140)과, 일단은 1차 전도성 금속층(130) 또는 2차 전도성 금속층(150)과 전기적으로 연결되고, 타단은 터미널단자와 전기적으로 연결되며, 최외각 접촉면의 적어도 한 면 이상에 전도체 도금층(172)이 도금된, 전도체(170)와, 반도체 칩(140)의 하면에 형성된 1차 전도성 금속층(130) 또는 상면에 형성된 2차 전도성 금속층(150)에 접촉하도록 형성된 금속분말층(120, 160)과, 터미널단자를 외부로 노출시키면서 기판(110)과 반도체 칩(140)과 전도체(170)과 금속분말층(120, 160)을 패키징하는 패키지 하우징을 포함하고, 전도체(170)는 1차 전도성 금속층(130)이 있는 반도체 칩(140)의 하면 또는 2차 전도성 금속층(150)이 있는 반도체 칩의 상면과 전기적으로 연결하도록 구성한다.
이때 금속분말층은 금속분말을 포함하고 1차 전도성 금속층(130)과 전기적으로 연결되도록 접촉하는 1차 금속분말층(120)과, 2차 전도성 금속층(150)과 전기적으로 연결되도록 접촉하는 2차 금속분말층(160)으로 구성될 수 있다. 이를 통해 기판(110) 및 전도체(170)와 열팽창특성이 유사한 금속분말층(120,160)을 사용한 접합구조를 형성하여 접합부의 신뢰성을 향상시키는 것을 요지로 한다.
구체적으로, 금속분말층은, 금속알갱이가 하나 이상의 반도체 칩(140)의 하면의 1차 전도성 금속층(130)과 접촉하도록 구성된 1차 금속분말층(120)과, 금속알갱이가 하나 이상의 반도체 칩(140)의 상면의 2차 전도성 금속층(150)과 접촉하도록 구성된 2차 금속분말층(160)을 포함한다.
우선, 기판(110)은 하나 이상으로 구성되며 하나 이상의 절연층을 포함하고, 기판(110)에는 반도체 칩(140)과 전기적 연결이 가능하도록 특정 패턴이 분할 형성된다.
예컨대, 기판(110)은 절연층을 포함하되, 단층구조의 절연기판이거나, 1층 이상의 금속패턴층이 형성된 다층구조의 금속절연기판일 수 있고, 금속패턴층은 Cu 또는 Al의 단일 금속으로 형성되거나, Al-Cu 합금형태의 금속 전도체로 형성될 수 있다.
한편, 도 1의 (a)에 도시된 바와 같이, 하부 금속절연기판(110A) 상에 하나 이상의 반도체 칩(140)을 1차 금속분말층(120)을 개재하여 접합한 후, 메탈포스트인 전도체(170)를 2차 금속분말층(160)을 개재하여 반도체 칩(140) 상에 접합하고, 상부 금속절연기판(110B)을 전도체(170)에 접착하여, 한쪽 기판에만 반도체 칩(140)을 부착하는 양면 기판 패키지 구조로 이루어지거나, 도 1의 (b)에 도시된 바와 같이, 하부 금속절연기판(110A) 상에 반도체 칩(140)이 1차 금속분말층(120)을 개재하여 접합되고 전도체(170)는 2차 금속분말층(160)을 개재하여 반도체 칩(140) 상에 접합되고, 상부 금속절연기판(110B) 상에 반도체 칩(140)이 1차 금속분말층(120)을 개재하여 접합되고 전도체(170)는 2차 금속분말층(160)을 개재하여 반도체 칩(140) 상에 접합되어, 양쪽 기판에 반도체 칩을 상호 교차하여 부착하는 양면 기판 패키지 구조로 이루어지거나, 도 1의 (c)에 도시된 바와 같이, 기판(110) 상에 1차 금속분말층(120), 반도체 칩 하면의 1차 전도성 금속층(130) 및 반도체 칩(140)이 순차적으로 적층되고, 반도체 칩(140) 상면의 2차 전도성 금속층(150), 2차 금속분말층(160) 및 전도체(170)가 순차적으로 적층되어 접합 구조를 형성하는 QFN(Quad Flat Non-lead) 패키지 구조로 이루어질 수 있다.
즉, 후술하는 1차 금속분말층(120) 및 2차 금속분말층(160)은 앞서 언급한 양면 기판 패키지 구조 및 QFN 패키지 구조에 모두 적용될 수 있다.
다음, 1차 금속분말층(120)은 접합층으로서, 기판(110)의 패턴 상에 도포되어 적층되고, 기판(110)과 반도체 칩(140) 하면의 1차 전도성 금속층(130)을 전기적으로 연결하면서 기판(110) 상에 반도체 칩(140)을 접합하는 역할을 한다.
한편, 도 4 및 도 6을 참고하면, 1차 금속분말층(120)은, 1차 전도성 금속층(130)과 반도체 칩(140)의 하면과 측면을 감싸도록 형성되고, 반도체 칩(140) 측면에 5㎛ 이상의 높이로 붙어 있도록 형성하여 접합강도를 높일 수 있다.
또한, 하나 이상의 1차 전도성 금속층(130)은 하나 이상의 1차 금속분말층(120)과 접촉할 수 있다.
다음, 반도체 칩(140)의 하면에 마련된 1차 전도성 금속층(130)은, 도 6에 예시된 바와 같이, 1차 금속분말층(120) 상에 적층 형성되어, 1차 금속분말층(120)과 반도체 칩(140)을 전기적으로 연결하는 역할을 한다.
도 4를 참고하면, 1차 전도성 금속층(130)은 상이한 금속으로 형성된 2레이어 적층구조(130A,B)로 형성될 수도 있다.
다음, 반도체 칩(140)은 1차 전도성 금속층(130) 상에 부착되어 접합하여 기판(110)과 전기적으로 연결된다.
한편, 1차 금속분말층(120) 또는 2차 금속분말층(160)과 접촉하는 반도체 칩(140)의 상면 및 하면의 최외각 금속층은 Ni, Ag, Au, Al 또는 Cu의 단일 소재이거나 이들 소재 중 어느 하나 이상의 성분이 10% 내지 80% 이상 함유된 합금일 수 있다.
여기서, 반도체 칩(140)은 실리콘 제어 정류기(SCR), 전력 트랜지스터, 절연게이트 양극트랜지스터(IGBT), 금속산화막 반도체 전계효과 트랜지스터(MOSFET), 전력 정류기, 전력 레귤레이터, 또는 그 조합체의 전력 반도체로 구성되어, 전기차, 수소전기차, 인버터 또는 컨버터에 사용될 수 있다.
다음, 2차 전도성 금속층(150)은 반도체 칩(140) 상면에 적층 형성되어, 반도체 칩(140)과 2차 금속분말층(160)을 전기적으로 연결하는 역할을 한다.
여기서, 1차 전도성 금속층(130) 또는 2차 전도성 금속층(150)은 Al, Ag, Au, Pd, Ni 또는 Cu의 단일 소재로 구성되거나, Al, Ag, Au, Pd, Ni 및/또는 Cu를 70% 이상 함유한 합금일 수 있고, 1차 전도성 금속층(130) 또는 2차 전도성 금속층(150)은 1층 이상의 금속층으로 적층되어 형성될 수 있다.
다음, 2차 금속분말층(160)은 접합층으로서, 2차 전도성 금속층(150) 상에 도포되어 적층되고, 2차 전도성 금속층(150)과 전도체(170)를 전기적으로 연결하면서 반도체 칩(140) 상에 전도체(170)를 접합하는 역할을 한다.
또한, 하나 이상의 2차 전도성 금속층(150)은 하나 이상의 2차 금속분말층(160)과 접촉할 수 있다.
여기서, 도 3을 참고하면, 1차 금속분말층(120) 또는 2차 금속분말층(160)을 이루는 금속분말은 금속알갱이(M1)일 수 있고, 열팽창계수가 17ppm 내지 18ppm인 Mo, Cu, Mn, Al 또는 SiC의 단일 소재로 구성되거나, Mo, Cu, Mn, Al 및/또는 SiC 소재의 금속알갱이 혼합된 분말 형태로 이루어질 수 있고, Cu 성분을 대부분 함유하는 기판(110) 및 전도체(170)와 유사한 열팽창계수를 갖도록 하여서, 반도체 패키지의 구동시 소재별 열팽창특성 차이에 의한 크랙발생을 최소화할 수 있다.
한편, 금속알갱이(M1)들 사이에는 다른 금속물질이 채워지지 않은 마이크로미터 수준의 틈인 하나 이상의 공극(air gap)(G)이 존재할 수 있고, 공극(G)의 크기는 1㎛ 이하인 것이 적어도 하나 이상이 되도록 형성되어, 열팽창특성의 변이를 최소화하면서 안정적인 접합구조를 형성할 수 있다.
또한, 금속알갱이(M1)는 가로직경과 세로직경이 상이한 형상으로 형성되고, 금속알갱이(M1)의 가로직경과 세로직경 중 짧은 쪽의 직경이 2㎛ 이하인 금속알갱이가 전체 금속알갱이 수의 20% 이상으로 형성될 수 있다.
또한, 도 5의 (a)를 참고하면, 2차 금속분말층(160)은, 전도체(170)의 하면과 측면을 감싸도록 형성되고, 전도체(170) 측면에 5㎛ 이상의 높이로 붙어 있도록 형성하여 접합강도를 높일 수 있다.
다음, 전도체(170)는 반도체 칩(140)과 터미널단자(미도시)를 전기적으로 연결하되, 전도체(170)의 일단은 2차 금속분말층(160)을 개재하여 2차 전도성 금속층(150)과 전기적으로 연결되고, 타단은 터미널단자와 전기적으로 연결되고, 최외각 접촉면의 적어도 한 면 이상에 전도체 도금층(172)이 도금된다.
한편, 도 5의 (b)를 참고하면, 전도체(170)는 분말 형태의 금속알갱이(M2)로 이루어지고, 금속알갱이(M2)는 Mo, Cu, Mn, Al 또는 SiC의 단일 소재로 구성되거나, Mo, Cu, Mn, Al 및/또는 SiC의 금속알갱이가 혼합된 분말 형태로 이루어질 수 있다.
또한, 전도체(170)는 1㎛ 내지 50㎛ 크기의 분말 형태의 금속알갱이(M2)를 70% 이상 함유할 수도 있다.
한편, 전도체(170)를 금속분말 형태의 금속알갱이로 예시하였으나, 이에 제한되지 않고 비금속분말 형태의 비금속알갱이로 이루어질 수도 있고, 비금속알갱이는 Mo, Cu, Mn, Al 또는 SiC의 단일 소재로 구성되거나, Mo, Cu, Mn, Al 및/또는 SiC의 금속알갱이가 혼합된 분말 형태로 이루어질 수 있으며, 1㎛ 내지 50㎛ 크기의 분말 형태의 비금속알갱이를 70% 이상 함유할 수도 있다.
구체적으로, 도 2 및 도 5의 (a)를 참고하면, 전도체(170)는 구조형상을 유지하는 주금속층(171)과, 주금속층(171)과 상이한 재질의 금속으로 이루어져 2차 금속분말층(160)과 접촉하는 최외각 접촉면의 한 면 이상에 도금되는 전도체 도금층(172)으로 구성될 수 있고, 전도체 도금층(172)은 1층 이상으로 적층되어 형성되어 전도체 도금층(172)의 두께는 2㎛ 이상일 수 있다.
또한, 전도체 도금층(172)은 가볍고 전기전도성이 양호한 금속재질로 구성하여 2차 전도성 금속층(150)과의 전기적 연결특성을 향상시키는 기능층으로서, 두께는 주금속층(171)의 두께보다 상대적으로 얇게 형성될 수 있고, 분리 제작된 주금속층(171)과 전도체 도금층(172)을 압착하여 일체화하거나, 주금속층(171)에 전도체 도금층(172)을 도금하여 일체화하여 형성할 수 있다.
여기서, 주금속층(171)에 전도체 도금층(172)을 도금하여 형성하는 경우에 도금 공정을 원활히 수행하기 위해서, 주금속층(171)과 전도체 도금층(172) 사이에 개재되어 상호 접합시키는 접합층(미도시)을 포함할 수 있다.
또한, 전도체 도금층(172)은, Ag, Au, Ni, Cu 또는 Sn의 단일 소재로 구성되거나, Ag, Au, Ni, Cu 및/또는 Sn를 50% 이상 함유한 합금일 수 있다.
최종, 패키지 하우징은 기판(110)과 반도체 칩(140)과 전도체(170)와 터미널단자를 EMC(Epoxy Molding Compound), PPS(PolyPhenylene Sulfide) 또는 PBT(PolyButylene Terephtalate) 소재로 패키징하여 절연시켜 보호하는 역할을 한다.
이에, 1차 금속분말층(120)의 금속분말을 통해 기판(110)과 1차 전도성 금속층(130)을 전기적으로 연결하고, 2차 금속분말층(160)의 금속분말을 통해 2차 전도성 금속층(150)과 전도체(170)를 전기적으로 연결하면서 기판(110) 및 전도체(170)와 열팽창특성이 유사한 금속분말층(120,160)을 사용하여 접합구조를 형성하여서, 솔더를 사용한 접합구조에서의 소재별 열팽창 차이로 인한 크랙(crack)의 발생을 최소화한다.
즉, 솔더에 비해 낮으면서 Cu 성분을 대부분 함유하여 기판(110) 및 전도체(170)와 유사한 열팽창계수를 갖는 금속분말층(120,160)을 이루는 금속알갱이(M1)를 통해 접합구조를 형성하여서, 기판(110)과 1차 전도성 금속층(130) 사이, 및 2차 전도성 금속층(150)과 전도체(170) 사이의 크랙발생을 최소화하여 접합부의 신뢰성을 향상시킬 수 있다.
이상, 본 발명을 도면에 도시된 실시예를 참조하여 설명하였다. 그러나, 본 발명은 이에 한정되지 않고 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 본 발명과 균등한 범위에 속하는 다양한 변형예 또는 다른 실시예가 가능하다. 따라서, 본 발명의 진정한 보호범위는 이어지는 특허청구범위에 의해 정해져야 할 것이다.
110 : 기판 120 : 1차 금속분말층
130 : 1차 전도성 금속층 140 : 반도체 칩
150 : 2차 전도성 금속층 160 : 2차 금속분말층
170 : 전도체 171 : 주금속층
172 : 전도체 도금층 M1,M2 : 금속알갱이
G : 공극
10 : 기판 20 : 반도체 칩
30 : 솔더

Claims (21)

  1. 전기적 연결이 가능하도록 특정 패턴이 형성된 하나 이상의 기판;
    상기 기판 상부에 마련되며, 1차 전도성 금속층이 있는 하면과, 2차 전도성 금속층이 있는 상면을 포함하는 하나 이상의 반도체 칩;
    일단은 상기 1차 전도성 금속층 또는 상기 2차 전도성 금속층과 전기적으로 연결되고, 타단은 터미널단자와 전기적으로 연결되며, 최외각 접촉면의 적어도 한 면 이상에 전도체 도금층이 도금된, 전도체;
    상기 1차 전도성 금속층 또는 상기 2차 전도성 금속층에 접촉하도록 형성된 하나 이상의 금속분말층; 및
    상기 터미널단자를 외부로 노출시키고, 상기 기판과 상기 반도체 칩과 상기 전도체와 상기 금속분말층을 패키징하는 패키지 하우징;을 포함하고,
    상기 전도체는 상기 1차 전도성 금속층이 있는 상기 반도체 칩의 하면 또는 상기 2차 전도성 금속층이 있는 상기 반도체 칩의 상면과 전기적으로 연결되어 상기 기판 또는 터미널단자와 전기적으로 연결되고,
    상기 전도체는 구조형상을 유지하는 주금속층, 및 상기 주금속층과 상이한 재질의 금속으로 이루어지고, 최외곽 접촉면의 적어도 한 면 이상에 전도체 도금층이 형성되며, 상기 주금속층은 금속분말 형태의 금속알갱이 또는 비금속분말 형태의 비금속알갱이로 이루어지는 것을 특징으로 하는, 반도체 패키지.
  2. 제 1 항에 있어서,
    상기 금속분말층은 금속분말을 포함하고,
    상기 1차 전도성 금속층과 전기적으로 연결되도록 접촉하는 1차 금속분말층과, 상기 2차 전도성 금속층과 전기적으로 연결되도록 접촉하는 2차 금속분말층을 포함하는 것을 특징으로 하는, 반도체 패키지.
  3. 제 1 항에 있어서,
    상기 금속분말층을 이루는 금속분말은 금속알갱이인 것을 특징으로 하는, 반도체 패키지.
  4. 제 3 항에 있어서,
    상기 금속알갱이는 Ag 또는 Cu의 단일 소재로 구성되거나, Ag, Au, Cu 및 Ni 중 어느 하나 이상이 70% 이상으로 포함되는 것을 특징으로 하는, 반도체 패키지.
  5. 제 3 항에 있어서,
    상기 금속알갱이들 사이에는 다른 금속물질이 채워지지 않은 하나 이상의 공극이 존재하는 것을 특징으로 하는, 반도체 패키지.
  6. 제 5 항에 있어서,
    상기 공극의 크기는 1㎛ 이하인 것이 하나 이상인 것을 특징으로 하는, 반도체 패키지.
  7. 제 1 항에 있어서,
    하나 이상의 상기 기판은 하나 이상의 절연층을 포함하는 것을 특징으로 하는, 반도체 패키지.
  8. 제 1 항에 있어서,
    상기 1차 전도성 금속층 또는 상기 2차 전도성 금속층은 1층 이상의 금속층으로 적층 형성되고, 상기 금속층은 Al, Ag, Au, Pd, Ni 또는 Cu의 단일 소재이거나, Al, Ag, Au, Pd, Ni 및 Cu 중 어느 하나 이상의 성분이 70% 이상 함유된 합금인 것을 특징으로 하는, 반도체 패키지.
  9. 제 8 항에 있어서,
    상기 금속분말층과 접촉하는 상기 1차 전도성 금속층 또는 상기 2차 전도성 금속층의 최외각 금속층은 Ni, Ag, Au, Al 또는 Cu의 단일 소재이거나, Ni, Ag, Au, Al 및 Cu 중 어느 하나 이상의 성분이 10% 내지 80% 이상 함유된 합금인 것을 특징으로 하는, 반도체 패키지.
  10. 삭제
  11. 제 1 항에 있어서,
    상기 금속알갱이 또는 상기 비금속알갱이는 Mo, Cu, Mn, Al 또는 SiC의 단일 소재로 구성되거나, Mo, Cu, Mn, Al 및 SiC 중 어느 하나 이상의 소재의 금속알갱이 또는 비금속알갱이가 혼합된 분말 형태로 이루어지는 것을 특징으로 하는, 반도체 패키지.
  12. 제 1 항에 있어서,
    상기 주금속층은, 1㎛ 내지 50㎛ 크기의 분말 형태의 금속알갱이를 70% 이상 함유하거나, 1㎛ 내지 50㎛ 크기의 분말 형태의 비금속알갱이를 70% 이상 함유하는 것을 특징으로 하는, 반도체 패키지.
  13. 제 1 항에 있어서,
    상기 전도체 도금층은 Ag, Au, Ni, Cu 또는 Sn의 단일 소재로 구성되거나, Ag, Au, Ni, Cu 및 Sn 중 어느 하나 이상을 50% 이상 함유한 합금인 것을 특징으로 하는, 반도체 패키지.
  14. 제 1 항에 있어서,
    상기 전도체 도금층은 1층 이상으로 적층형성되는 것을 특징으로 하는, 반도체 패키지.
  15. 제 14 항에 있어서,
    상기 전도체 도금층의 두께는 2㎛ 이상인 것을 특징으로 하는, 반도체 패키지.
  16. 제 2 항에 있어서,
    상기 1차 금속분말층은, 상기 1차 전도성 금속층과 상기 반도체 칩의 하면을 감싸도록 형성되고, 상기 반도체 칩 측면에 5㎛ 이상의 높이로 붙어 있는 것을 특징으로 하는, 반도체 패키지.
  17. 제 2 항에 있어서,
    상기 2차 금속분말층은, 상기 전도체의 하면을 감싸도록 형성되고, 상기 전도체 측면에 5㎛ 이상의 높이로 붙어 있는 것을 특징으로 하는, 반도체 패키지.
  18. 제 3 항에 있어서,
    상기 금속분말층은, 상기 금속알갱이가 상기 하나 이상의 반도체 칩의 하면의 상기 1차 전도성 금속층과 접촉하는 1차 금속분말층을 포함하는 것을 특징으로 하는, 반도체 패키지.
  19. 제 3 항에 있어서,
    상기 금속분말층은, 상기 금속알갱이가 상기 하나 이상의 반도체 칩의 상면의 상기 2차 전도성 금속층과 접촉하는 2차 금속분말층을 포함하는 것을 특징으로 하는, 반도체 패키지.
  20. 제 3 항에 있어서,
    상기 금속알갱이는 가로직경과 세로직경이 서로 다르게 형성되는 것을 특징으로 하는, 반도체 패키지.
  21. 제 20 항에 있어서,
    상기 금속알갱이의 가로직경과 세로직경 중 짧은 쪽의 직경이 2㎛ 이하인 금속알갱이가 전체 금속알갱이 수의 20% 이상으로 형성되는 것을 특징으로 하는, 반도체 패키지.
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US20210343631A1 (en) 2021-11-04
CN113611683A (zh) 2021-11-05

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