KR102185558B1 - Method for optical proximity correction - Google Patents

Abstract

With the optical proximity method, a plurality of evaluation points are set at the edge of the piece layout. Error values are calculated by matching each of the plurality of evaluation points with the pattern outline simulated from the piece layout. Among the error values, error values within an allowable error are set as a first error group. Among the error values, error values out of the tolerance are set as a second error group. While an error value exists in the first error group, the fragment layout is moved so that all error values included in the second error group have the same sign. According to the above method, the exposure mask pattern can be optically corrected so that the target pattern is formed at a desired position.

Description

Method for optical proximity correction

The present invention relates to an optical proximity correction method. More specifically, it relates to a method of correcting an optical proximity effect generated in an exposure process.

In an exposure process for manufacturing a semiconductor device, pattern distortion occurs during the process of transferring the pattern. In order to reduce such pattern distortion, a technology for correcting optical proximity effects (Optical Proximity Correction, OPC) has been developed. The optical proximity correction includes a process of correcting an exposure mask pattern to form a target pattern of a designed layout. Also, it includes a process of checking whether the target pattern is implemented on an actual substrate and recalibrating.

An object of the present invention is to provide an optical proximity correction method for correcting an exposure mask pattern so that the pattern is positioned at a target position.

In the optical proximity correction method according to an embodiment of the present invention for achieving the above object, a plurality of evaluation points are set at the edge of the piece layout. Error values are calculated by matching each of the plurality of evaluation points with the pattern outline simulated from the piece layout. Among the error values, error values within an allowable error are set as a first error group. Among the error values, error values out of the tolerance are set as a second error group. While an error value exists in the first error group, the fragment layout is moved so that all error values included in the second error group have the same sign.

In an embodiment of the present invention, the step of determining whether an error value exists in the first error group may be further included.

In an embodiment of the present invention, in order to move the piece layout, an extreme value, which is an error value at the pole of the pattern outline, is found among the error values. If a pole is not included in the pattern outline, an error value of a point where the pattern outline deviates from the edge of the piece layout is designated as the extreme value. Move the piece layout so that the extrema is within tolerance.

In an embodiment of the present invention, it may further include reconfirming whether the extreme value is within a tolerance with respect to the pattern outline simulated in the corrected fragment layout.

In an embodiment of the present invention, the tolerance may be set to 0 or a value within a range for preventing occurrence of defects between neighboring target patterns.

In an embodiment of the present invention, when both ends of the edge of the pattern outline have a convex shape, the fragment layout may be moved so that all error values included in the second error group are negative.

In an embodiment of the present invention, when both ends of the edge of the pattern outline have a concave shape, the fragment layout may be moved so that all error values included in the second error group are positive.

In the optical proximity correction method according to an embodiment of the present invention for achieving the above object, a plurality of evaluation points are set at the edge of the piece layout. Error values are calculated by matching each of the plurality of evaluation points with the pattern outline simulated from the piece layout. From the error values, an extreme value, which is an error value at the pole of the pattern outline, is found. In addition, the piece layout is moved so that the extrema is within tolerance.

In an embodiment of the present invention, if the pattern outline does not include a pole, an error value of a point where the pattern outline deviates from the edge of the piece layout may be designated as the extreme value.

In an embodiment of the present invention, among the error values, error values within the allowable error are set as a first error group in order to move the piece layout within the allowable error. Among the error values, error values out of the tolerance are set as a second error group. The fragment layout is moved so that at least one error value exists in the first error group. In addition, the fragment layout is moved so that the error values of the second error group have the same sign while the error value exists in the first error group.

According to embodiments of the present invention, the pattern outline is located within the edge of the target pattern of the design layout without deviating from the edge. By performing optical proximity correction on the exposure mask pattern in this way, it is possible to suppress process defects such as bridge and notching occurring in the actual pattern.

1 is a flow chart illustrating an optical proximity correction method for a layout of a semiconductor device according to the present invention.
2 is a plan view of an example layout of a semiconductor device suitable for performing the method of FIG. 1.
3 to 7 are plan views illustrating a method of correcting optical proximity to the layout of FIG. 2.
8 is a plan view of another example layout of a semiconductor device suitable for carrying out the method of FIG. 1.
9 is a plan view of a layout of another example of a semiconductor device suitable for carrying out the method of FIG. 1.
10 is an example of a layout of a semiconductor device for explaining an optical proximity correction method according to an embodiment of the present invention.
11A, 11B, and 12 are plan views illustrating a method of optical proximity correction to the layout of FIG. 10.
13 and 14 are plan views illustrating another example of an optical proximity correction method for a layout of a semiconductor device.
15 and 16 are perspective views illustrating a method of forming a pattern of a semiconductor device using an exposure mask pattern formed through optical proximity according to an embodiment of the present invention.

With respect to the embodiments of the present invention disclosed in the text, specific structural or functional descriptions have been exemplified only for the purpose of describing the embodiments of the present invention, and the embodiments of the present invention may be implemented in various forms. It should not be construed as being limited to the embodiments described in.

Since the present invention can apply various changes and have various forms, specific embodiments will be illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to a specific form of disclosure, it is to be understood as including all changes, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first and second may be used to describe various elements, but the elements should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, terms such as "comprise" or "have" are intended to designate the existence of disclosed features, numbers, steps, actions, components, parts, or a combination thereof, but one or more other features or numbers, It is to be understood that the presence or addition of steps, actions, components, parts or combinations thereof does not preclude the possibility of preliminary exclusion.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning of the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in this application. .

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same elements in the drawings, and duplicate descriptions for the same elements are omitted.

first. Optical proximity correction (OPC) will be described.

Each of the photo masks used in the photo process includes mask patterns corresponding to individual layers of the semiconductor device. A photoresist film is formed on a substrate, and a photoresist pattern is formed by projecting and developing light onto the photoresist film through the photomask. In addition, designed circuit patterns required for a semiconductor device may be formed by performing an etching process or the like using the photoresist pattern.

Mask patterns formed on the photo mask correspond to circuit patterns integrated on the substrate. A computer-aided design (CAD) program may be used to form a layout of mask patterns included in the photo mask. The mask pattern formation operation can be performed by Electronic Design Automation (EDA).

Certain rules are applied to the formation of the layout of the mask pattern. Usually, CAD programs have predetermined design rules for mask formation. For example, design rules define a spacing margin between circuit element patterns or line patterns. In addition, line width margins of circuit element patterns or line patterns are defined.

As semiconductor devices become highly integrated, dimensions of the circuit device patterns or line patterns are also decreasing. That is, since the line width of each pattern and the spacing between neighboring patterns are very narrow, defects due to pattern distortion during a pattern transfer process are further increasing. For example, bridging defects between patterns or notching defects of patterns are likely to occur, and accurate optical proximity correction is required to reduce the defects.

The following embodiments relate to an optical proximity correction method that can be usefully used when forming a pattern in which the position of the edge of the edge is very important. As an example, it may be used in a pattern having a narrow width so that an edge portion can be divided into one fragment layout. That is, the edge portion of the line pattern having a narrow width (part 10a in Fig. 2), the connecting portion of the ends of spacers having a narrow spacing distance (part A in Fig. 8), and the edge pattern part of the diagonal shape (part C in Fig. 9) ) Can be effectively used in the optical proximity correction method of the fragment layout.

However, in the case of a piece layout for forming a pattern having a convex and one concave contour at one of the both ends, the optical proximity correction method according to the following embodiments does not need to be applied. In the case of a piece layout for forming a pattern having a convex and one concave contour at one of the both ends, since almost no defects occur even without complicated optical proximity correction, the optical proximity correction method according to the following embodiment There is no need to apply.

1 is a flow chart illustrating an optical proximity correction method for a layout of a semiconductor device according to the present invention.

2 is a plan view of an example layout of a semiconductor device suitable for performing the method of FIG. 1. 3 to 7 are plan views illustrating a method of correcting optical proximity to the layout of FIG. 2.

8 is a plan view of another example layout of a semiconductor device suitable for carrying out the method of FIG. 1. 9 is a plan view of a layout of another example of a semiconductor device suitable for carrying out the method of FIG. 1.

Each of the steps of the optical proximity correction method described below may be performed using a computer system. That is, by executing a computer program programmed to perform optical proximity correction in the computer system, optical proximity correction may be performed. In addition, final corrected piece layouts can be obtained, and optical proximity corrected layouts can be obtained through each corrected layout.

An optical proximity correction method according to an exemplary embodiment of the present invention will be described using the design layout of the semiconductor device shown in FIG. 2.

1 and 2, a design layout including a target pattern 10 to be finally formed is prepared. The outline of the target pattern 10 is divided to generate a plurality of fragment layouts 10a (fragment) (S10).

For example, the target pattern of FIG. 2 has a line shape extending in a first direction. Each outline of the target pattern is divided at the dividing point 14 to form a respective piece layout.

Both ends of the target pattern 10 in the first direction have a straight line shape. However, the expected pattern contour 12 of the actual photoresist formed through the exposure process may have a convex edge portion due to an optical proximity effect.

Each of the fragment layouts 10a may have a width equal to a design rule of the semiconductor device. Therefore, after that, the exposure amount of the photoresist formed on the substrate for the piece layout 10a can be simulated with the light intensity distribution. In addition, optical proximity correction is performed on the fragment layout 10a to determine a corrected layout used for a final mask pattern.

When the line width of the target pattern 10 is narrow enough to be the same as the design rule of the semiconductor device, the width of the edge portion in the first direction of the target pattern 10 is one single segment edge. fragment).

As shown in FIG. 2, when the predicted pattern contour 12 at the edge portion is located inside the target pattern 10, the pattern contour becomes a convex corner with both edges convex.

At least one of the plurality of piece layouts is selected (S12).

The present embodiment relates to a method of effectively optical proximity correction of an edge portion of a mask pattern having a narrow line width enough to be divided into one piece layout. Therefore, the fragment layout 10a of the edge portion of the target pattern 10 in the first direction can be selected. However, even if a piece layout of another portion is selected, the method described below can be applied in the same manner.

1 and 3, a plurality of evaluation points 30 (multi-evaluation points, EP) are set at the edge of the selected piece layout 10a. (S14) The evaluation points 30 are the above. It can be set continuously at very narrow intervals along the edge of the piece layout 10a. For example, the spacing between the evaluation points 30 may be several nm. The narrower the spacing between the evaluation points 30 for accurate optical proximity correction, the more the number of evaluation points 30 increases. It is advantageous. However, as the number of evaluation points 30 increases, the time required for optical proximity correction may slightly increase. The evaluation points 30 may be arranged at equal intervals.

4A and 6A, a pattern contour 32 is generated by simulating from the engraving layout 10a. (S16) That is, the photoresist formed on the substrate in the engraving layout 10a The exposure amount is simulated with the light intensity distribution to obtain a pattern outline 32 of a photoresist pattern. The obtained pattern contour 32 may include a pole that is a relatively most protruding portion.

The simulated pattern contour 32 is associated with the evaluation points 30, respectively. In addition, error values (EPE), which are differences between the evaluation points 30 and the simulated pattern contour 32, are calculated (S18). Accordingly, the evaluation points 30 and The same number of error values are calculated. After that, the fragment layout is corrected using the error value, and the method will be described in order.

The error values are classified into a first error group EP1 and a second error group EP2, respectively, according to whether or not the error values are out of the allowable range (S20).

For example, the first error group EP1 may be a set of error values within an allowable range. In addition, the second error group EP2 may be a set of error values outside the allowable range.

That is, the first error group EP1 may include an error value when the evaluation point 30 and the pattern contour 32 are completely coincident with each other and the error value is 0. Alternatively, it may include an error value when the evaluation point 30 and the pattern contour 32 are out of only a fine degree within an allowable range and thus no error occurs substantially. The allowable range may be a range such that defects between neighboring target patterns do not occur. The second error group may include an error value in which the evaluation point 30 and the pattern contour 32 deviate beyond the allowable range.

At this time, the error values calculated at each evaluation point 30 belong to one of the first and second error groups EP1 and EP2. In this case, an error value may or may not exist in the first error group EP1.

Next, it is determined whether or not an error value exists in the first error group EP1. (S22) Depending on whether or not an error value exists in the first error group EP1, the moving direction of the piece layout is different. I can.

4A to 4C illustrate an optical proximity correction method when an error value does not exist in the first error group. 5 shows a moving direction of a piece layout according to the method of FIGS. 4A to 4C.

As illustrated in FIG. 4A, when there is no part in which the pattern outline 32 and the evaluation points 30 coincide, the error value of the first error group does not exist. In this case, the position of the pattern outline must be changed by moving the fragment layout so that the error value exists in the first error group.

To this end, referring to FIG. 4B, an extreme value is found among the error values. The extreme value may be an error value at the pole, which is the most protruding portion of the pattern outline 32. The extreme value may be determined according to the shape and position of the pattern outline. For example, when a pattern outline 32 as shown in FIG. 4A is obtained, the extreme value may be a minimum error value.

After that, the piece layout is moved so that the extreme value becomes 0 or is within an allowable error range. For example, as shown in FIG. 5, the layout of pieces can be moved.

Referring to FIG. 4C, the most protruding end of the moved pattern outline 32a may be accurately positioned without deviating from the edge of the target pattern. Thus, the corrected piece layout is created.

Thereafter, referring to FIG. 1, a simulated pattern outline is regenerated from the corrected fragment layout (S16). Further, error values between each evaluation point and the pattern outline are recalculated (S18), respectively. The error values are divided into first and second error groups (S20), and a process of determining whether the first error group exists (S22) is performed again.

Meanwhile, in the process of determining whether an error value exists in the first error group EP1 (S22), if at least one error value exists in the first error group, the following process is performed.

It is determined whether the signs of the respective error values included in the second error group are the same (S24).

For example, when the pattern outline is located within the outline of the target pattern (ie, the guide line of the evaluation point) (FIG. 2, IN), a negative sign may be assigned to the error value. When the pattern outline is located outside the outline of the target pattern (ie, the guide line of the evaluation point) (FIG. 2, OUT), the error value may be given a positive sign.

6A to 6C illustrate an optical proximity correction method when an error value exists in the first error group. 8 shows a moving direction of a piece layout according to the method of FIGS. 6A to 6C.

As shown in FIG. 6A, when there is a portion where the pattern outline 32 and the evaluation point 30 coincide, an error value of the first error group EP1 exists.

In this case, the position of the pattern outline 32 must be changed by moving the fragment layout so that the error values of the second error group EP2 all have the same sign while allowing the error value to exist in the first error group. If the signs of each of the error values included in the second error group are the same, there is no part of the pattern outline beyond the guide line, which is a connection line of the target evaluation points. That is, the pattern outline is located within the guide line.

To this end, referring to FIG. 6B, an extreme value is found among the error values. (S26) The extreme value may be an error value at the pole that is the most protruding portion of the pattern outline 32. The extreme value may be determined according to the shape and position of the pattern outline. For example, when a pattern outline as shown in FIG. 6A is obtained, the extreme value may be a maximum error value having a positive sign.

Thereafter, the piece layout is moved so that the extreme value becomes 0 or within the tolerance range (S28). For example, as shown in FIG. Further, as shown in FIG. 6B, the pattern outline may be moved. In this way, when the extreme value becomes 0 or is within an allowable error range, the error values of the second error group have the same sign.

Referring to FIG. 6C, the most protruding end of the moved pattern outline 32a may be accurately positioned without deviating from the edge of the target pattern. Thus, the corrected piece layout is created.

The sign of the error value of the second error group may have a positive or negative value according to a shape of an edge portion of the pattern outline.

For example, as shown in a portion 10a of FIG. 2, a portion B of FIG. 8, and a portion C of FIG. 9, when the edge portion of the pattern contour is a convex corner type, the pattern contour may be located inside the target pattern I can. Therefore, all of the signs of the error values included in the second error group may be negative. For example, when a portion of the fragment layout corresponds to an end of a line, all of the signs of error values included in the second error group may be negative.

As another example, as shown in part A of FIG. 8, when the edge portion of the pattern outline has a concave corner shape, the pattern outline may be located outside the target pattern. Therefore, all of the signs of the error values included in the second error group may be positive. For example, when the portion of the piece layout corresponds to the end of the space, all of the signs of the error values included in the second error group may be positive.

Thereafter, referring to FIG. 1, error values between the evaluation points and the pattern outline generated from the corrected fragment layout are recalculated, and the first and second error groups EP1, EP2), and when the first error group EP1 exists, a series of processes of checking whether all error values of the second error group EP2 have the same sign are performed (S16 to S24).

If it is determined that the signs of each of the error values included in the second error group EP2 are the same, it is determined as the final corrected piece layout (S30). That is, optical proximity correction for the piece layout is completed.

The pattern outline formed using the final corrected piece layout is positioned so as not to deviate outside the edge of the target pattern of the design layout.

Using the final corrected fragment layouts, a layout of an exposure mask pattern for forming a target pattern can be obtained. When the exposure mask pattern formed by performing the optical proximity correction method is used, a photoresist pattern can be formed at an accurate position.

10 is an example of a layout of a semiconductor device for explaining an optical proximity correction method according to an embodiment of the present invention. 11A to 12 are plan views illustrating a method of optical proximity correction to the layout of FIG. 10.

This embodiment relates to an optical proximity correction method when the pattern outline of the selected piece layout does not include a pole.

Referring to FIG. 10, since a pole is not included in the predicted pattern outline 52, the error value at the maximum point where the pattern outline deviates from the edge of the piece layout is designated as an extreme value, and each of the steps shown in the flowchart of FIG. Can be done.

First, the steps described with reference to steps S10 to S20 are performed in the same manner. Accordingly, each error value is divided into a first error group or a second error group.

It is determined whether or not an error value exists in the first error group (S22). When there is no error value in the first error group, the fragment layout needs to be moved so that the first error group exists.

To this end, referring to FIG. 11A, first, the error value at the maximum point P where the pattern outline 62 deviates from the edge of the piece layout is designated as an extreme value, and this is found. (S26) Referring to FIG. 11B , The piece layout is moved so that the extreme value becomes 0 or is within an allowable range (S28). Thus, the corrected piece layout is generated. For example, as illustrated in FIG. 12, the layout of pieces may be moved.

Thereafter, error values between the evaluation points 60 and the pattern outline 62a generated from the corrected fragment layout are recalculated, and the first and second error groups EP1 and EP2), and the process of determining whether the first error group EP1 exists is again performed (S16 to S22).

Meanwhile, if at least one error value exists in the first error group EP1, signs of each error value included in the second error group EP2 are checked (S24). The second error group EP2 The signs of each error value included in) should be the same.

If the signs of the error values included in the second error group EP2 are not all the same, the signs of the error values are matched through the following process. First, the error value at the maximum point where the pattern outline 62 deviates from the edge of the piece layout is designated as an extreme value and is found. (S26) The piece layout is moved so that the extreme value is within an allowable range. Thus, the corrected piece layout is created.

Thereafter, error values between the evaluation points 60 and the pattern outline 62a generated from the corrected fragment layout are recalculated, and the first and second error groups EP1 and EP2), and if there is an error value in the first error group EP1, it is checked whether all the error values of the second error group EP2 have the same sign (S16 to S24).

When all the signs of the error values included in the second error group EP2 are the same, the final corrected fragment layout is determined. That is, the optical proximity correction for the piece layout is completed.

13 and 14 are plan views illustrating another example of an optical proximity correction method for a layout of a semiconductor device.

This embodiment is different from that described with reference to FIG. 3 in a method of setting evaluation points.

First, a piece layout is selected by performing the same steps described with reference to steps S10 to S12. The piece layout may be a layout of one end of the target pattern in the first direction.

A plurality of evaluation points are set at the edge of the selected piece layout (S14).

Referring to FIG. 13, in the selected fragment layout, first evaluation points 30a are set at a first interval in a first region 1 adjacent to the pole of the pattern outline. In addition, in the selected piece layout, second evaluation points 30b are set at a second interval in the second portion, which is the remaining portion slightly separated from the pole of the pattern outline. The second interval may be wider than the first interval.

The first portion (1) is a portion where the pattern outline is most likely to deviate from the guide line of the evaluation point. Therefore, the evaluation points can be arranged more densely in the first portion 1 than in the second portion 2. Meanwhile, since the number of evaluation points in the second region 2 is relatively reduced, the total number of evaluation points may be reduced. Therefore, it is possible to reduce the time required for optical proximity correction.

Referring to FIG. 14, optical proximity correction is performed by performing the processes S20 to S30 on the set first and second evaluation points 30a and 30b.

15 and 16 are perspective views illustrating a method of forming a pattern of a semiconductor device using an exposure mask pattern formed through optical proximity according to an embodiment of the present invention.

Referring to FIG. 15, a pattern target layer 102 is formed on a substrate 100. The pattern target layer 102 may be patterned through a subsequent photolithography process to form a desired target pattern.

A photoresist film is coated on the pattern target film 102. The photoresist film is exposed by transferring light to the photomask 106 through the exposure mask 106 facing the photoresist film. Exposure mask patterns 108 for forming the target pattern are formed on the exposure mask 106.

The exposure mask patterns 108 may be formed by performing optical proximity correction described with reference to FIG. 1. As an example, at least an edge portion of the exposure mask pattern 108 may be formed using fragment layouts final corrected through optical proximity correction described with reference to FIG. 1. As another example, the exposure mask patterns 108 may be formed using fragment layouts finally corrected through optical proximity correction described with reference to FIG. 1.

The exposure mask patterns 108 are optically corrected so that the simulated pattern contour does not deviate from the guide line of the evaluation points. Therefore, when patterning using the exposure mask pattern 108, the edge portion of the target pattern may be positioned so as not to deviate from a desired position.

Referring to FIG. 16, a photoresist pattern 104a is formed through the above developing process. The photoresist pattern 104a may have the same shape as the target pattern 102a.

Thereafter, the target pattern 102a may be formed by etching the pattern target layer 102 using the photoresist pattern 104a as an etching mask.

The present invention can be used in various manufacturing processes for performing an exposure process. That is, it can be used in a technique of forming an exposure mask pattern used in an exposure process.

10: target pattern 32: pattern outline
30: evaluation point

Claims (10)

A plurality of fragment layouts are generated by dividing the outline of the target pattern including a line extending in the first direction, and one of the plurality of fragment layouts is provided at the edge of the target pattern in the first direction. A step of designating a layout of the fragments arranged at the edge of the target pattern in the first direction as a first fragment layout;
Selecting the first piece layout and setting a plurality of evaluation points at an edge of the selected first piece layout;
Calculating error values by matching each of the plurality of evaluation points with the pattern outline simulated from the first piece layout;
Setting error values within an allowable error among the error values as a first error group;
Setting error values out of the tolerance among the error values as a second error group; And
And moving the first piece layout so that the error values included in the second error group have the same sign while an error value exists in the first error group. The optical proximity correction method of claim 1, further comprising determining whether an error value exists in the first error group. The method of claim 1, wherein the step of moving the first piece layout,
Finding an extreme value, which is an error value at the pole of the pattern outline, among the error values;
If the pattern outline does not include a pole, designating an error value of a point where the pattern outline deviates from the edge of the first piece layout as an extreme value; And
And moving the first piece layout such that the extrema is within the tolerance. 4. The optical proximity correction method according to claim 3, further comprising reconfirming whether the extrema is within the tolerance for the simulated pattern contour in the corrected first piece layout. delete The optical proximity correction method of claim 1, wherein when both ends of the edge of the pattern outline have a convex shape, the first piece layout is moved so that all error values included in the second error group are negative. The optical proximity correction method of claim 1, wherein when both ends of the edge of the pattern outline have a concave shape, the first piece layout is moved so that all error values included in the second error group are positive. A plurality of fragment layouts are generated by dividing the outline of the target pattern having a line shape extending in the first direction, and one of the plurality of fragment layouts is provided at the edge of the target pattern in the first direction. A step of designating a layout of the fragments arranged at the edge of the target pattern in the first direction as a first fragment layout;
Selecting the first piece layout and setting a plurality of evaluation points at an edge of the selected first piece layout;
Calculating error values by matching each of the plurality of evaluation points with the pattern outline simulated from the first piece layout;
Finding an extreme value, which is an error value at the pole of the pattern outline, from the error values;
If the pattern outline does not include a pole, designating an error value of a point where the pattern outline deviates from the edge of the first piece layout as an extreme value; And
And moving the first piece layout such that the extrema is within a tolerance. delete The method of claim 8, wherein the extremal value moving the first piece layout within the tolerance comprises:
Among the error values, setting error values within the tolerance as a first error group;
Among the error values, setting error values out of the tolerance as a second error group;
Moving the first piece layout so that at least one error value exists in the first error group; And
And moving the first piece layout so that the error values of the second error group all have the same sign while an error value exists in the first error group.

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