KR102181766B1 - Layout of differential amplifier - Google Patents

Abstract

The differential amplifier layout according to the present invention is in a semiconductor device including a plurality of differential amplifiers, each of which is spaced apart from each other by a predetermined interval, wherein the differential amplifier is connected to a first transistor electrically connected to a ground voltage line, and connected to the first transistor. A second transistor receiving a signal through the enable signal line, a third transistor connected to the second transistor, receiving a first input signal, and outputting a first output signal, and a second transistor connected to the second transistor. And a fourth transistor configured to receive an input signal and output a second output signal.

Description

Differential Amplifier Layout {LAYOUT OF DIFFERENTIAL AMPLIFIER}

The present invention relates to a differential amplifier layout, and more particularly, to a differential amplifier layout in which one differential amplifier is divided into a plurality of differential amplifiers.

In general, a differential amplifier that differentially amplifies a potential difference between two input signals is widely used in semiconductor devices. A differential amplifier used in a semiconductor device includes a current mode logic (CML) circuit, and the output characteristics of the current mode logic circuit are greatly affected by the size of the resistor.

These differential amplifiers use large-sized transistors, and the fingering of the transistors is increasing. Accordingly, in the case of the outermost transistor, there is a problem in that it is difficult to completely transfer the characteristics of the transistor due to resistance of the metal line.

The present invention provides a differential amplifier layout in which the resistance of a metal line is reduced by dividing and disposing a plurality of differential amplifiers so that the characteristics of a transistor are fully reflected.

The differential amplifier layout according to the present invention is a semiconductor device including a plurality of differential amplifiers, each of which is spaced apart by a predetermined interval, wherein the differential amplifier includes a first gate line, a first source region, and a first drain region. A second transistor including a transistor, a first metal line extending in a direction parallel to the first gate line and electrically connected to the first drain region, a second gate line, a second source region, and a second drain region And, a second metal line extending in a direction parallel to the second gate line and electrically connected to the second source region, and connected to the first metal line and the second metal line between the first transistor and the second transistor, And a connection line extending in a direction perpendicular to the first metal line and the second metal line.

This technology provides the following effects by separating and arranging a plurality of transistors of a differential amplifier.

First, as the area of the conductive line, which is a connection line connected from the first transistor to the second transistor, is reduced, the resistance of the connection line can be reduced.

Second, by separating one differential amplifier into a plurality, the size of the differential amplifier is minimized and the area occupied by the connection line is reduced, so that the area required to form the differential amplifier can be greatly reduced.

1 is a circuit diagram showing a differential amplifier according to the present invention.
2 is a layout showing a differential amplifier according to the present invention.

Hereinafter, some embodiments of the present invention will be described in detail through exemplary drawings. In adding reference numerals to elements of each drawing, it should be noted that the same elements are assigned the same numerals as possible even if they are indicated on different drawings. In addition, in describing an embodiment of the present invention, if it is determined that a detailed description of a related known configuration or function obstructs an understanding of the embodiment of the present invention, a detailed description thereof will be omitted.

1 is a circuit diagram showing a differential amplifier according to the present invention.

Referring to FIG. 1, a plurality of differential amplifiers (A1, A2, A3, A4) are arranged, and each differential amplifier detects a potential difference between two input signals (IN, INB) and the difference between the input signals (IN, INB). The amplified output signals (OUT, OUTB) are output accordingly. Further, the differential amplifier includes a plurality of transistors T1, T2, T3, T4 and resistance lines RL1, RL2.

First, one differential amplifier will be described as follows.

One end of the first transistor T1 is electrically connected to the second transistor T2, and the other end is electrically connected to the ground voltage line VSS. Then, the gate of the first transistor T1 receives the bias signal CMLBIAS.

The second transistor T2 has one end electrically connected to the third transistor T3 and the fourth transistor T4, and the other end connected to the first transistor T1. In addition, the gate of the second transistor T2 receives the enable signal EN.

In addition, one end of the third transistor T3 is electrically connected to the first resistance line RL1 and the other end of the third transistor T3 is electrically connected to the second transistor T2. In addition, the gate of the third transistor T3 receives the first input signal IN and outputs the first output signal OUT.

In addition, one end of the fourth transistor T4 is electrically connected to the second resistance line RL2, and the other end is electrically connected to the second transistor T2. In addition, the gate of the fourth transistor T4 receives the second input signal INB and outputs the second output signal OUTB.

In addition, one end of the first resistance line RL1 and the second resistance line RL2 is electrically connected to the power voltage line VDD to receive the power voltage.

The present invention is a differential comprising a first transistor (T1), a second transistor (T2), a third transistor (T3) and a fourth transistor (T4), a first resistance line (RL1) and a second resistance line (RL2). The amplifier is divided into a plurality of units and includes a configuration in which the amplifier is arranged spaced apart at a predetermined interval.

2 is a layout showing a differential amplifier according to the present invention, and corresponds to the circuit diagram structure of FIG.

The layout of the differential amplifier according to the present invention will be described with reference to FIG. 2 as follows.

In the differential amplifier according to the present invention, the differential amplifiers A1, A2, A3, and A4 divided into a plurality of units are disposed at a predetermined interval, respectively.

And, each of the differential amplifiers (A1, A2, A3, A4) is a plurality of transistors (T1, T2, T3, T4), a plurality of resistance lines (RL), power supply voltage line (VDD), ground voltage line (VSS) , Input signal lines IN and INB, output signal lines OUT and OUTB, enable signal lines EN, and CML bias signal lines CMLBIAS.

First, in the plurality of transistors T1, T2, T3, and T4, the first transistor T1 and the second transistor T2 are connected in series, and the third transistor T3 and the fourth transistor T4 are arranged. They are arranged in pairs and connected in parallel. At this time, the third transistor T3 and the fourth transistor T4 forming a pair are connected in series with the second transistor T2. In addition, each of the plurality of transistors T1, T2, T3, and T4 may be implemented as a multi-finger transistor.

In a multi-finger transistor, a plurality of gate lines arranged parallel to each other on an active region are connected by fingers, and source regions and drain regions alternate with each other in an active region between gate lines connected by a plurality of fingers. It means a transistor formed of.

FIG. 2 is a diagram illustrating a state divided into four differential amplifiers A1, A2, A3, and A4. However, the number of differential amplifiers divided into a plurality of units is not limited thereto, and a minimum of two to a maximum of N, and the third transistor T3 and the fourth transistor T4 within a range including at least two gate lines. Can be separated from

First, the first transistor T1 electrically connected to the ground voltage line VSS includes a plurality of first gate lines 110 disposed on the active region 100, and the first gate line 110 is the other end. This may be implemented in the form of a connected multi-finger transistor.

First contacts 105 are disposed at the other ends of the first gate lines 110, and the first transistor T1 receives a signal through a CML bias signal line CMLBIAS connected to the first contact 105.

A plurality of first source regions S1 and first drain regions D1 are formed in the active region 100 between the first gate lines 110. A plurality of second contacts 115 are disposed in the first source region S1 and the first drain region D1, respectively, and a third contact is formed between the second contacts 115 of the first source region S1. 120) is placed.

The first source regions S1 are electrically connected to the ground voltage line VSS through the third contact 120. In addition, the first drain regions D1 are connected to the first metal line 125 through the second contacts 115. The first metal line 125 is disposed on the first drain region D1 between the first gate lines 110 and is disposed in a line shape in a direction parallel to the first gate line 110.

In addition, a second transistor T2 connected to the first transistor T1 and receiving a signal through the enable signal line EN is a plurality of second gate lines 210 disposed on the active region 200. Including, the second gate line 210 may be implemented in the form of a multi-finger transistor connected to the other end.

Fourth contacts 205 are disposed at the other ends of the second gate lines 210, and the second transistor T2 transmits an enable signal through an enable signal line EN electrically connected to the fourth contact 205. Receive.

In addition, a plurality of second source regions S2 and a plurality of second drain regions D2 are formed in the active region 200 between the second gate lines 210. A plurality of fifth contacts 215 are disposed in the second source region S2 and the second drain region D2, respectively.

The second source region S2 is connected to the second metal line 220a by a fifth contact 215. The second metal line 220a is disposed on the first source region S1 between the second gate lines 210 and is disposed in a line shape in a direction parallel to the second gate line 210.

A connection line 123 in the form of a line extending in a direction perpendicular to the first gate line 110 and the second gate line 210 is disposed between the first transistor T1 and the second transistor T2. The second metal line 220a and the first metal line 120 are connected through the connection line 123. That is, the first drain region D1 of the first transistor T1 and the second source region S2 of the second transistor T2 are electrically connected through the first metal line 120 and the second metal line 220a. Can be connected to.

Here, the number of fingers included in the first transistor T1 is greater than the number of fingers included in the second transistor T2. That is, as the number of fingers included in the first transistor T1 increases, the length of the connection line 123 connected from the first transistor T1 to the second transistor T2 increases.

As in the present invention, when one differential amplifier is divided into a plurality of small differential amplifiers, the first transistor T1 and the second transistor T2 are also separated into a plurality, and the first transistor T1 is divided into a second transistor. The length of the connection line 123 connected to the transistor T2 may be shorter than the conventional one. That is, the area of the conductive line, which is the connection line 123, is reduced. Therefore, parasitic capacitance and resistance generated by the connection line 123, which is a conductive line, are reduced, so that the cut-off frequency of the multi-finger transistor can have a higher value.

In addition, by separating one differential amplifier into a plurality, the size of the differential amplifier is minimized and the area occupied by the connection line 123 is reduced, so that an area required to form the differential amplifier can be greatly reduced.

Next, the second transistor T2 is connected, the third transistor T3 and the second transistor T2 are connected to receive a first input signal IN and output a first output signal OUT. The fourth transistor T4 that receives the second input signal INB and outputs the second output signal OUTB is disposed in a pair.

The third transistor T3 and the fourth transistor T4 include a plurality of third gate lines 310 and fourth gate lines 410 disposed on the active regions 300 and 400, respectively, and the third gate The line 310 and the fourth gate line 410 may be implemented in the form of a multi-finger transistor connected to the other ends. In this case, the number of fingers included in the third transistor T3 and the number of fingers included in the fourth transistor T4 may be the same. Further, the sum of the number of fingers included in the third transistor T3 and the fourth transistor T4 may be formed equal to the number of fingers of the second transistor T2.

A plurality of third source regions S3 and a plurality of third drain regions D3 are formed in the active region 300 between the third gate lines 310. A plurality of sixth contacts 315 are disposed in the third source region S3 and the third drain region D3, respectively. In addition, a seventh contact 317 is disposed between the sixth contacts 315 of the third drain region D3.

The third source region S3 is connected to the fourth metal line 320 by a sixth contact 315. The fourth metal line 320 is disposed on the third source region S3 between the third gate lines 310 and is disposed in a line shape parallel to the third gate line 310.

In addition, a plurality of fourth source regions S4 and a plurality of fourth drain regions D4 are formed in the active region 400 between the fourth gate lines 410. A plurality of ninth contacts 415 are disposed in the fourth source region S4 and the fourth drain region D4, respectively. In addition, a tenth contact 417 is disposed between the ninth contacts 415 of the fourth drain region D4.

The fourth source region S4 is connected to the fifth metal line 420 by a ninth contact 415. The fifth metal line 420 is disposed on the fourth source region S4 between the fourth gate lines 410 and is disposed in a line shape parallel to the fourth gate line 410.

The fourth metal line 320, the fifth metal line 420, and the third metal line 220b are connected to a connection line 223 between the third transistor T3 and the fourth transistor T4 and the second transistor T2. ) Through the electrical connection. That is, the second drain region D2 of the second transistor T2 and the third source region S3 and the fourth source region S4 of the third transistor T3 and the fourth transistor T4 are formed of the fourth metal. It may be electrically connected through the line 320, the fifth metal line 420, and the third metal line 220b.

An eighth contact 330 is disposed at one end of the third gate line 310, respectively, and receives a first input signal IN through the eighth contact 330. In addition, the first output signal OUT is output through the seventh contact 315 disposed in the third drain region D3.

An eleventh contact 430 is disposed at one end of the fourth gate line 410, respectively, and a second input signal INB is input through the eleventh contact 430. In addition, the second output signal OUTB is output through the ninth contact 415 disposed in the fourth drain region D4. The third transistor T3 and the fourth transistor T4 forming a pair serve to amplify the difference between the differential input signals IN and INB to output the output signals OUT and OUTB.

In addition, separated first and second resistance lines RL1 and RL2 are disposed on one side of the third transistor T3 and the other side of the fourth transistor T4, respectively. A 12th contact 510 and a 13th contact 515 are disposed on one end of the first resistance line RL and the tartan, respectively, and a 14th contact 520 and a 15th contact are respectively disposed at one end and the other end of the second resistance line RL. A contact 525 is placed. The first resistance line RL1 and the second resistance line RL2 are connected to the power voltage line VDD through the twelfth contact 510 and the fourteenth contact 520.

The thirteenth contact 515 of the first resistance line RL1 outputs the first output signal OUT together with the seventh contact 315 disposed in the third drain region D3. In addition, the fifteenth contact 525 of the second resistance line RL2 outputs the second output signal OUTB together with the ninth contact 415 disposed in the fourth drain region D4. The differential amplifier determines and outputs an output signal value according to a potential difference between two input signals while transistors are turned on by an enable signal and a via-earth signal.

As described above, in a differential amplifier having a layout divided into a plurality of units, as the area of the conductive line 123 connected from the first transistor T1 to the second transistor T2 is reduced, the conductive line The parasitic capacitance generated by the in-connection line 123 is reduced, and thus the cut-off frequency of the multi-finger transistor can have a higher value.

In addition, by separating one differential amplifier into a plurality, the size of the differential amplifier is minimized and the area occupied by the connection line 123 is reduced, so that an area required to form the differential amplifier can be greatly reduced.

100, 200, 300, 400: active area 105: first contact
110: first gate line 115: second contact
120: third contact 123, 323: connecting line
125: first metal line 205: fourth contact
210: second gate line 220a: second metal line
220b: third metal line 215: fifth contact
310: third gate line 320: fourth metal line
315: sixth contact 317: seventh contact
410: fourth gate line 415: eighth contact
417: ninth contact 420: fifth metal line
510: tenth contact 515: eleventh contact
520: 12th contact 525: 13th contact

Claims (16)

In a semiconductor device including a plurality of differential amplifiers each arranged spaced apart a predetermined interval,
The differential amplifier is
A first transistor including a first gate line, a first source region, and a first drain region;
A first metal line extending in a direction parallel to the first gate line and electrically connected to the first drain region;
A second transistor including a second gate line, a second source region, and a second drain region;
A second metal line extending in a direction parallel to the second gate line and electrically connected to the second source region; And
A connection line connected to the first metal line and the second metal line between the first transistor and the second transistor and extending in a direction perpendicular to the first metal line and the second metal line,
A differential amplifier layout, characterized in that a first input signal and a second input signal are commonly input to the plurality of differential amplifiers. The method according to claim 1,
And a third transistor and a fourth transistor connected to the second transistor, wherein the third and fourth transistors each include a gate line, a source region, and a drain region. The method according to claim 2,
Wherein the first transistor, the second transistor, the third transistor, and the fourth transistor are each a multi-finger transistor. The method according to claim 1,
A plurality of contacts are disposed at the other end of the first gate line, and the first gate line is electrically connected to a CMLBIAS signal line through the contact. The method according to claim 1,
And a plurality of contacts connected to the first source region, wherein the first transistor is connected to a ground voltage line through the contacts. The method according to claim 1,
The differential amplifier layout, wherein the first drain region is electrically connected to the first metal line through a contact. The method of claim 1,
And a plurality of contacts at the other end of the gate line of the second transistor, and the second transistor is electrically connected to an enable signal line by the contact. The method according to claim 1,
Wherein the second source region is connected to the second metal line through a contact. The method according to claim 2,
A third metal line including a plurality of contacts in the second drain region and connected to the drain region through the contacts;
A fourth metal line including a plurality of contacts in the source region of the third transistor and connected to the source region through the contacts; And
A fifth metal line including a plurality of contacts in the source region of the fourth transistor and connected to the source region through the contacts
Differential amplifier layout, characterized in that it further comprises. The method of claim 9,
The differential amplifier layout, wherein the third metal line and the fourth and fifth metal lines are electrically connected between the second transistor and the third and fourth transistors through a connection line. The method according to claim 2,
A differential amplifier layout, wherein a first resistance line is disposed on one side of the third transistor, and a second resistance line is disposed on the other side of the fourth transistor. The method of claim 11,
A contact is disposed at one end of the first and second resistance lines, and is electrically connected to a power supply voltage line through the contacts. The method of claim 11,
A contact is disposed at the drain region of the third transistor and the other end of the first resistance line, and is electrically connected to a first output signal line through the contacts. The method of claim 11,
A contact is disposed at the drain region of the fourth transistor and the other end of the second resistance line, and is electrically connected to a second output signal line through the contacts. The method according to claim 2,
A contact is disposed at one end of the gate line of the third transistor, and the third transistor is electrically connected to a first input signal line through the contact. The method according to claim 2,
A contact is disposed at one end of the gate line of the fourth transistor, and the fourth transistor is electrically connected to a second input signal line through the contact.

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