KR102173811B1 - Package unit and multi-stack package - Google Patents

Abstract

A plurality of semiconductor dies offset and stacked to partially expose active surfaces; A first encapsulation member covering the exposed active surface of the plurality of semiconductor dies, having first and second surfaces parallel to the active surface, and including a photosensitive insulating film; Through vias extending from the first surface to the active surface through the first encapsulation member; And upper wirings connecting the through vias on a first surface of the first encapsulant is provided.

Description

Package unit and multi-stack package}

The present invention relates to a package unit and a multi-stack package, and more particularly, to a package unit and a multi-stack package that are simple, fast, and inexpensive to manufacture.

While memory storage capacity is increased, electronic devices including semiconductor memory devices are required to be thin and light, so there are still points to be improved in a method of manufacturing a multichip package in which a plurality of semiconductor chips are stacked.

The first technical problem to be achieved by the present invention is to provide a package unit that is simple, fast, and inexpensive to manufacture.

A second technical problem to be achieved by the present invention is to provide a multi-stack package that is simple, fast and inexpensive to manufacture.

A third technical problem to be achieved by the present invention is to provide a method of manufacturing a package unit that is simple, fast, and inexpensive to manufacture.

In order to achieve the first technical problem, the present invention includes: a plurality of semiconductor dies stacked to be offset to partially expose active surfaces; A first encapsulation member covering the exposed active surface of the plurality of semiconductor dies, having first and second surfaces parallel to the active surface, and including a photosensitive insulating film; Through vias extending from the first surface to the active surface through the first encapsulation member; And upper wirings connecting the through vias on a first surface of the first encapsulation member.

In some embodiments, the photosensitive insulating layer may be a polyimide resin. In some embodiments, the first encapsulant may be configured to cover the entire upper surface of the uppermost semiconductor die among the plurality of semiconductor dies.

In some embodiments, the plurality of semiconductor dies each include an inactive surface opposite to the active surfaces, and further include a second encapsulant in contact with the inactive surface and covering the plurality of semiconductor dies, The second encapsulation body may be different from the first encapsulation body. The second encapsulant may include an epoxy molding compound (EMC). The second surface may be substantially on the same plane as the non-active surface of the lowermost semiconductor die. A frame remaining portion may be further included on at least one side of the first encapsulation member and the second encapsulation member.

In some embodiments, the first encapsulant may not extend above the active surface of the uppermost semiconductor die. The first surface of the first encapsulant is substantially on the same plane as the active surface of the uppermost semiconductor die, and at least one of the upper wirings is above the first surface to the active surface. Can be extended.

The present invention is a package substrate to achieve the second technical problem; Two or more of the package units stacked on the package substrate; And it provides a multi-stack package including a molding resin encapsulating the package units.

The present invention comprises the steps of forming a first encapsulant in the cavity of the frame in order to achieve the third technical problem; Stacking a plurality of semiconductor dies in the cavity, and stacking the semiconductor dies in an offset manner so that active surfaces of each of the semiconductor dies are partially exposed; Forming a second encapsulant including a photosensitive polymer to cover the exposed active surfaces by offsetting the semiconductor dies; Forming through via holes exposing the active surface to the second encapsulant through a photolithography method; Forming through vias in the through via holes; It provides a method of manufacturing a package unit, including forming an upper wiring connecting the through vias on an upper surface of the second encapsulant.

In some embodiments, the first encapsulant may not contain a photosensitive polymer. In some embodiments, the forming of the second encapsulant may include covering the entire upper surface of the uppermost semiconductor die among the plurality of semiconductor dies with the first encapsulant.

If a multi-stack package is manufactured using the package units according to the embodiments of the present invention, not only can it be manufactured quickly, but also a defective package unit among the package units tested for burn-in can be excluded in advance. The possibility that the whole is judged as defective can be greatly reduced. Conventionally, since the burn-in test was performed after manufacturing the entire package with all the semiconductor dies mounted, if all of the semiconductors are defective, the entire semiconductor package is judged as defective, resulting in a yield loss. There was an increasing problem.

In addition, the present invention does not sequentially stack a plurality of semiconductor dies, but stacks a package unit in which a plurality of semiconductor dies are already stacked, so that manufacturing is simple, rapid, and inexpensive.

1A is a side view showing a cross section of a package unit according to an embodiment of the present invention.
1B is a side view showing a cross section of a package unit according to another embodiment of the present invention.
2A to 2E are side cross-sectional views conceptually showing a method of manufacturing a package unit according to an embodiment of the present invention.
3 is a side cross-sectional view showing a multi-stack package according to an embodiment of the present invention.
4A and 4B are side cross-sectional views illustrating a method of manufacturing a multi-stack package according to an embodiment of the present invention.
5A to 5F are side cross-sectional views illustrating a method of manufacturing a package unit according to another embodiment of the present invention.
6A to 6F are side cross-sectional views showing a method of manufacturing a package unit according to still another embodiment of the present invention.
7A to 7E are side cross-sectional views illustrating a method of manufacturing a package unit according to still another embodiment of the present invention.
8A to 8D are side cross-sectional views illustrating a method of manufacturing a package unit according to still another embodiment of the present invention.

Hereinafter, exemplary embodiments of the concept of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the concept of the present invention may be modified in various different forms, and the scope of the concept of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the inventive concept are preferably interpreted as being provided in order to more fully explain the inventive concept to those with average knowledge in the art. Identical symbols mean the same elements all the time. Furthermore, various elements and areas in the drawings are schematically drawn. Accordingly, the inventive concept is not limited by the relative size or spacing drawn in the accompanying drawings.

Terms such as first and second may be used to describe various components, but the components are not limited by the terms. These terms are only used for the purpose of distinguishing one component from another component. For example, without departing from the scope of the present invention concept, a first component may be referred to as a second component, and conversely, a second component may be referred to as a first component.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the concept of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, expressions such as "comprises" or "have" are intended to designate the presence of features, numbers, steps, actions, components, parts, or a combination thereof described in the specification, but one or more other features or It is to be understood that it does not preclude the possibility of the presence or addition of numbers, actions, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical terms and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs. In addition, commonly used terms as defined in the dictionary should be construed as having a meaning consistent with what they mean in the context of the technology to which they are related, and in an excessively formal sense unless explicitly defined herein. It will be understood that it should not be interpreted.

When a certain embodiment can be implemented differently, a specific process order may be performed differently from the described order. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to the described order.

In the accompanying drawings, for example, depending on manufacturing techniques and/or tolerances, variations of the illustrated shape can be expected. Accordingly, the embodiments of the present invention should not be construed as being limited to the specific shape of the region shown in the present specification, but should include, for example, a change in shape resulting from the manufacturing process. All terms "and/or" as used herein include each and every combination of one or more of the recited elements. In addition, the term "substrate" as used herein may refer to a substrate itself, or a laminate structure including a substrate and a predetermined layer or film formed on the surface thereof. In addition, in the present specification, "the surface of the substrate" may mean an exposed surface of the substrate itself, or an outer surface of a predetermined layer or film formed on the substrate.

1A is a side view showing a cross-section of a package unit 100a according to an embodiment of the present invention.

Referring to FIG. 1A, a package unit 100a according to an aspect of the present invention may include two or more stacked semiconductor dies 110. In FIG. 1A, four semiconductor dies 110a, 110b, 110c, and 110d are stacked in the package unit 100a, but a person of ordinary skill in the art knows that the semiconductor dies 110 are two, three, or five or more. It will be appreciated that semiconductor dies may be included.

In some embodiments, the semiconductor dies 110a, 110b, 110c, and 110d may include a nonvolatile memory device. The nonvolatile memory device includes, for example, a flash memory, a phase-change memory (PRAM), a resistive RAM (RRAM), a ferroelectric memory (FeRAM), and a solid magnetic memory. , MRAM), etc., but is not limited thereto. The flash memory may be, for example, a NAND flash memory. The flash memory may be, for example, a V-NAND flash memory. The nonvolatile memory device may be formed of a single semiconductor die, or may be stacked of several semiconductor dies.

In some embodiments, the semiconductor dies 110a, 110b, 110c, and 110d may include a volatile memory device. The volatile memory device may be, for example, DRAM, SRAM, SDRAM, DDR RAM, RDRAM, etc., but is not limited thereto. The volatile memory device provides a cache function for storing frequently used data when the external host accesses the package unit 100a, thereby improving the process performance of the external host connected to the package unit 100a. Access-time and data-transfer performance can be scaled accordingly.

The semiconductor dies 110 may be stacked while being offset in the lateral direction. In other words, the semiconductor dies 110 may be stacked to form steps while being shifted in one direction. In some embodiments, the semiconductor dies 110 may be stacked with an active surface facing upward. Here, it is assumed that the upper surface of the semiconductor dies 110 is an active surface and the lower surface is an inactive surface. The semiconductor dies 110 may be offset and stacked to partially expose active surfaces.

Each of the semiconductor dies 110a, 110b, 110c, and 110d may be bonded to each other by an adhesive member 115 such as an adhesive or a die attach film (DAF). The first adhesive member 115a may couple the first semiconductor die 110a and the second semiconductor die 110b. The second adhesive member 115b may couple the second semiconductor die 110b and the third semiconductor die 110c. The third adhesive member 115c may couple the third semiconductor die 110c and the fourth semiconductor die 110d.

Side surfaces of the semiconductor dies 110 may be at least partially encapsulated by the encapsulation material 120. At this time, at least one of the semiconductor dies 110 may have a surface exposed. The encapsulation material 120 may be an epoxy molding compound (EMC), a photosensitive insulating layer (eg, a polyimide material layer), or a combination thereof. In some embodiments, one side of the semiconductor dies 110 may contact EMC and the other side of the semiconductor dies 110 may contact the photosensitive insulating layer.

Specifically, the encapsulation material 120 may include a first encapsulation body 124 and a second encapsulation body 122. The first encapsulant 124 may cover the exposed active surfaces of the semiconductor dies 110. The first encapsulant 124 may have a first surface 127 and a second surface 128 parallel to the active surfaces of the semiconductor dies 110, respectively. The second encapsulant 122 may contact an inactive surface of the semiconductor dies 110.

The first encapsulant 124 and the second encapsulant 122 may be made of different materials. In some embodiments, the first encapsulant 124 may be a photosensitive insulating layer, for example, a polyimide resin having photosensitive properties. In some embodiments, the second encapsulant 122 may be a non-photosensitive insulating layer, for example, an EMC resin.

In some embodiments, the first encapsulant 124 may cover the entire active surface of the semiconductor die 110d positioned at the top of the semiconductor dies 110a, 110b, 110c, and 110d.

Each of the semiconductor dies 110a, 110b, 110c, and 110d included in the package unit 100a may be electrically connected by a package unit redistribution line 130. In some embodiments, the package unit redistribution line 130 may include two or more through vias 132 and an upper wiring 134 connecting them.

The through via 132 may pass through the encapsulation material 120 and be connected to an active surface of each of the semiconductor dies 110a, 110b, 110c, and 110d. In some embodiments, the through vias 132 may be disposed such that the semiconductor dies 110a, 110b, 110c, and 110d are offset to be coupled to an exposed upper portion. In some embodiments, the through vias 132 may have different lengths. In some embodiments, upper ends of the through vias 132 may be located at substantially the same level. In some embodiments, the through vias 132 are from the upper surface of the encapsulation material 120 to the upper surface of the semiconductor dies 110a, 110b, 110c, 110d corresponding to each through via 132 It may have a vertical length corresponding to the distance of.

In some embodiments, two or more of the through vias 132 may be connected to each other by an upper wiring 134 on an upper surface of the encapsulation material 120. In some embodiments, a group of the through vias 132 corresponding to each of the semiconductor dies 110a, 110b, 110c, and 110d are connected to the upper wiring 134 on the upper surface of the encapsulation material 120. Can be connected to each other.

A capping layer 135 may be provided on the upper wiring 134. The capping layer 135 may be an insulator such as silicon nitride.

The through via 132 and the upper wiring 134 may be any conductor and are not particularly limited. For example, the through via 132 and the upper wiring 134 may each independently be doped silicon, a metal, a conductive metal nitride, a conductive metal oxide, a conductive metal oxynitride, or a combination thereof. have. The metal may be titanium (Ti), tungsten (W), tantalum (Ta), copper (Cu), aluminum (Al), nickel (Ni), cobalt (Co), iron (Fe), molybdenum (Mo), etc. It is not limited to these.

1B is a side view showing a cross section of a package unit 100b according to another embodiment of the present invention.

Referring to FIG. 1B, it is substantially the same as the embodiment described with reference to FIG. 1A except that the upper surface of the fourth semiconductor die 110d is exposed. Therefore, hereinafter, a description will be made focusing on differences from FIG. 1A, and detailed descriptions of points identical or similar to those of FIG. 1A will be omitted.

In the package unit 100b, through vias 132a corresponding only to the first semiconductor die 110a, the second semiconductor die 110b, and the third semiconductor die 110c may exist. The through vias 132a may be interconnected through an upper wiring 134a. The fourth semiconductor die 110d may be directly connected to the upper wiring 134a without passing through the through via 132a.

The first encapsulant 124 may not extend above the active surface of the fourth semiconductor die 110d, which is the uppermost semiconductor die among the semiconductor dies 110a, 110b, 110c, and 110d.

In some embodiments, the first surface 127 is substantially the same as the active surface of the fourth semiconductor die 110d, which is the uppermost semiconductor die among the semiconductor dies 110a, 110b, 110c, and 110d. It can be on a plane. Also, at least one of the upper wirings 134a may extend from the first surface 127 to the active surface of the fourth semiconductor die 110d. The second surface 128 may be substantially on the same plane as the non-active surface of the first semiconductor die 110a, which is the lowest semiconductor die among the semiconductor dies 110a, 110b, 110c, and 110d.

The package unit 100b illustrated in FIG. 1B may have a thinner thickness compared to the package unit 100a illustrated in FIG. 1A.

2A to 2E are side cross-sectional views conceptually showing a method of manufacturing the package unit 100a according to an embodiment of the present invention.

Referring to FIG. 2A, a frame 101 having a cavity CA is provided. The frame 101 may be made of a material having a predetermined hardness, such as EMC, and may have a cavity CA in which a stack of semiconductor dies to be formed later may be accommodated.

Referring to FIG. 2B, a second encapsulant 122 is formed in the cavity CA of the frame 101. The second encapsulant 122 may be formed by, for example, a printing method, and may be made of a polymer resin such as an epoxy molding compound. The second encapsulant 122 may have a viscosity that is deformable in correspondence with the shape of the semiconductor dies 110 to be disposed later.

Referring to FIG. 2C, semiconductor dies 110 are disposed in the cavity CA of the frame 101. In some embodiments, the semiconductor dies 110 may be sequentially disposed from the first semiconductor die 110a' to the fourth semiconductor die 110d. In other embodiments, a stacked body stacked from the first semiconductor die 110a' to the fourth semiconductor die 110d may be positioned within the cavity. However, the present invention is not limited thereto, and a part of the semiconductor dies 110 may be disposed in the cavity first and then the rest may be stacked.

As described with reference to FIG. 1A, the first to fourth semiconductor dies 110a ′ to 110d may be stacked while being laterally offset from each other by a predetermined length.

As shown in FIG. 2C, the first semiconductor die 110a ′ may be disposed to be in close contact with the side surface of the second encapsulant 122. In addition, since the second semiconductor die 110b is offset in one direction (to the left in FIG. 2C) of the first semiconductor die 110a', it may be in close contact with the upper edge of the second encapsulant 122.

2B and 2C, the second encapsulant 122 is provided at a time and the shape is determined by the arrangement of the semiconductor dies 110, but in another embodiment, the second encapsulant 122 122 may be sequentially stacked in each step while stacking the semiconductor dies 110. In another embodiment of the present invention, the second encapsulant 122 may be omitted.

Referring to FIG. 2D, a first encapsulant 124 may be formed to cover the upper surface of the offset side of the semiconductor dies 110. The first encapsulant 124 may be a photosensitive polymer, and in this case, via holes 124H in which through electrodes are to be formed may be easily formed by a photolithography method. The photosensitive polymer may be, for example, a polyimide resin, but is not limited thereto.

Referring to FIG. 2E, a through via 132 is formed in the via hole 124H formed in the first encapsulant 124. The through via 132 may be performed by a method such as chemical vapor deposition (CVD), physical vapor deposition (PVD) such as sputtering, electrolytic plating, and electroless plating. I can. However, the present invention is not limited thereto.

The through via 132 is, for example, tungsten (W), copper (Cu), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), ruthenium (Ru), palladium ( It may be made of Pd), platinum (Pt), cobalt (Co), nickel (Ni), or a combination thereof.

The upper wiring 134 may be formed at the same time as the process of forming the through via 132, consecutively to the process, or separately from the process of forming the through via 132. In some embodiments, the upper wiring 134 may be formed by forming a conductive layer and then patterning the conductive layer. The upper wiring 134 is, for example, tungsten (W), copper (Cu), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), ruthenium (Ru), palladium ( It may be made of Pd), platinum (Pt), cobalt (Co), nickel (Ni), or a combination thereof.

Subsequently, when the frame 101 is removed and the first semiconductor die 101a' is removed over a portion of the thickness, a package unit 100a as shown in FIG. 1A may be obtained.

3 is a side cross-sectional view showing a multi-stack package 10 according to an embodiment of the present invention.

Referring to FIG. 3, two or more package units 100a shown in FIG. 1A may be stacked. In FIG. 3, an example in which five package units 100a are stacked is illustrated, but a person skilled in the art will understand that two, three, four, or six or more package units 100a may be stacked.

When the plurality of package units 100a are stacked, a portion of the upper wiring 134 may be offset to be exposed by the package unit 100a disposed thereon. In addition, in FIG. 3, although the plurality of package units 100a are alternately offset to the left or right, a person skilled in the art will understand that the plurality of package units 100a may be offset in any direction. That is, the plurality of package units 100a may be offset not only in the left or right direction, but also in the front or rear direction of the gaze direction of FIG. 3.

The stacked plurality of package units 100a may be mounted on the package substrate 11. The plurality of package units 100a may be electrically connected to an upper pad 11b of the package substrate 11 through a connection means 15 such as a bonding wire.

In addition, the upper pad 11b is electrically connected to the lower pad 11c through a via 11d extending through the substrate insulator 11a, and the plurality of package units 100a are provided with the lower pad 11c. It can be electrically connected to an external device through.

The stacked package units 100a may be molded using a molding resin 17. The molding resin 17 may be, for example, EMC, but the present invention is not limited thereto.

4A and 4B are side cross-sectional views illustrating a method of manufacturing a multi-stack package 10 according to an embodiment of the present invention.

Referring to FIG. 4A, a package unit 100a serving as a stacking unit is manufactured. Since the manufacturing of the package unit 100a has been described with reference to FIGS. 2A to 2E, additional descriptions are omitted here.

Each of the package units 100a may perform a burn-in test on the package units 100a before being stacked later. Only the package unit 100a, which is a good product that has passed the burn-in test, can be selected and used for later lamination.

Referring to FIG. 4B, a plurality of package units 100a are stacked on the package substrate 11. In this case, as described with reference to FIG. 3, the stacked package units 100a may be stacked on the package substrate 11 so that they are offset from each other. More specifically, the plurality of package units 100a may be arranged to be offset so that a part of the upper wiring 134 is exposed by the package unit 100a disposed thereon when stacked.

One package unit 100a and the package unit 100a thereon may be coupled to each other by an adhesive member such as a die attaching film DAF.

Then, the exposed upper wiring 134 is electrically connected to the upper pad 11b of the package substrate 11. The upper wiring 134 may be electrically connected to the upper pad 11b by a connecting means 15 such as a bonding wire.

Subsequently, when the laminate in which the plurality of package units 100a are stacked is molded with a molding resin 17, a multi-stack package 10 according to an embodiment of the present invention may be obtained.

According to embodiments of the present invention, since each package unit is individually burn-in tested and then a multi-stack package is manufactured using package units determined as good products, the entire multi-stack package is determined as defective. It can greatly reduce the likelihood. Conventionally, since the burn-in test was performed after manufacturing the entire package with all the semiconductor dies mounted, if all of the semiconductors are defective, the entire semiconductor package is judged as defective, resulting in a yield loss. There was an increasing problem.

5A to 5F are side cross-sectional views illustrating a method of manufacturing a package unit 100c according to another embodiment of the present invention.

The manufacturing method illustrated in FIGS. 5A to 5F is different from the embodiment described with reference to FIGS. 2A to 2E in that two or more package units are simultaneously manufactured. Therefore, in the following description, the differences will be mainly described, and descriptions of common parts will be omitted.

Referring to FIG. 5A, a frame 101C in which a plurality of cavities CA is formed is provided. The frame 101C may have two or more of a plurality of cavities CA. 5A illustrates an example in which two cavities CA are formed in the frame 101C, a person of ordinary skill in the art will understand that three or more cavities CA may be formed in the frame 101C.

Since the steps shown in FIGS. 5B to 5E are substantially the same as the steps shown in FIGS. 2B to 2E, respectively, a brief description will be given here.

Referring to FIG. 5B, the second encapsulants 122 are respectively formed in the cavities CA of the frame 101C. Referring to FIG. 5C, semiconductor dies 110a', 110b, 110c, and 110d are respectively disposed in the cavities CA of the frame 101C. Referring to FIG. 5D, a first encapsulant 124 including a photosensitive polymer is formed to cover the upper surface of the offset side of the semiconductor dies 110a', 110b, 110c, and 110d, and via holes are formed. 5E, a through via 132 is formed in the via hole.

Referring to FIG. 5F, grinding may be performed along the line LH of FIG. 5E to expose the first semiconductor die 110a. Also, in order to singulate each package unit 100c, sawing may be performed along the LV line of FIG. 5E.

In the package unit 100c obtained as a result, the frame residual portion 101R, which is a part of the frame 101C, remains on the side surface. The frame remaining portion 101R may cover all or part of side surfaces of the package unit 100c. In some embodiments, the frame remaining portion 101R may at least partially cover each side surface of the package unit 100c. In some embodiments, the frame remaining portion 101R may remain on at least one side of the first encapsulation member 124 and/or the second encapsulation member 122.

6A to 6F are side cross-sectional views illustrating a method of manufacturing a package unit 100c according to still another embodiment of the present invention.

The manufacturing method shown in FIGS. 6A to 6F is different from the embodiment described with reference to FIGS. 5A to 5F in that a plurality of cavities are formed to penetrate the frame 101S. Therefore, in the following description, the differences will be mainly described, and descriptions of common parts will be omitted.

Referring to FIG. 6A, a frame 100S in which a plurality of cavities are formed is provided. The frame 101S may have two or more of a plurality of cavities. 6A illustrates an example in which two cavities are formed in the frame 101S, a person of ordinary skill in the art will understand that three or more cavities may be formed in the frame 101S.

As will be described later, the area and height of each of the cavities may be determined in consideration of the size and number of semiconductor dies mounted therein.

Since the steps shown in FIGS. 6B to 6E are substantially the same as the steps shown in FIGS. 2B to 2E, respectively, a brief description will be given here.

Referring to FIG. 6B, the second encapsulants 122 are respectively formed in the cavities CA of the frame 101S. Referring to FIG. 6C, semiconductor dies 110a', 110b, 110c, and 110d are disposed in the cavities CA of the frame 101S, respectively. Referring to FIG. 6D, a first encapsulant 124 including a photosensitive polymer is formed to cover the upper surface of the offset side of the semiconductor dies 110a', 110b, 110c, and 110d, and via holes are formed. Referring to FIG. 6E, a through via 132 is formed in the via hole.

Referring to FIG. 6F, in order to singulate each package unit 100c, sawing may be performed along the LV line of FIG. 6E.

The package unit 100c obtained as a result may be the same as the package unit 100c obtained in FIG. 5F. In the embodiment shown in Figs. 6A to 6F, the process is simpler since there is no need to grind along the LH line in Fig. 5E. In addition, since all semiconductor dies used for stacking may have the same thickness, manufacturing cost may be reduced.

7A to 7E are side cross-sectional views illustrating a method of manufacturing a package unit according to still another embodiment of the present invention.

The manufacturing method shown in FIGS. 7A to 7E is a step-shaped seating portion in which semiconductor dies are offset and seated in the cavity CA of the frame 101D compared to the embodiment described with reference to FIGS. 5A to 5F. There is a difference in that 101SP) is equipped. Therefore, in the following description, the differences will be mainly described, and descriptions of common parts will be omitted.

Referring to FIG. 7A, a step-shaped seating portion 101SP may be provided in the frame 101D. The seating part 101SP may be formed separately from the frame 101D or may be formed integrally with the frame 101D.

Referring to FIG. 7B, a plurality of semiconductor dies 110a', 110b, 110c, and 110d may be sequentially stacked in the frame 101D, and each of the semiconductor dies 110a', 110b, 110c, and 110d The sum of the height and the height of the adhesive members 115a, 115b, 115c may be the height of the seating portion 101SP.

Since the steps shown in FIGS. 7B to 7E are substantially the same as the steps shown in FIGS. 5C to 5F, respectively, a brief description will be given here.

Referring to FIG. 7B, semiconductor dies 110a', 110b, 110c, and 110d are disposed in the cavities CA of the frame 101D, respectively. Referring to FIG. 7C, a first encapsulant 124 including a photosensitive polymer is formed to cover the upper surface of the offset side of the semiconductor dies 110a', 110b, 110c, and 110d, and via holes are formed. Referring to FIG. 7D, a through via 132 is formed in the via hole. Referring to FIG. 7E, grinding may be performed along the line LH of FIG. 7D to expose the first semiconductor die 110a. In addition, in order to singulate each package unit 100d, sawing may be performed along the LV line of FIG. 7D.

8A to 8D are side cross-sectional views illustrating a method of manufacturing a package unit according to still another embodiment of the present invention.

Referring to FIG. 8A, a frame 224 on which wirings 232 and 234 are formed is provided. The wirings 232 and 234 may be formed by forming a hole in the frame 224 and then using a method such as plating or evaporation.

Referring to FIG. 8B, a connection means 237 ′ may be disposed on the vertical wiring 232 exposed to each step in the frame 224. The connection means 237 ′ may be a solder ball, but is not limited thereto.

Then, the first semiconductor die 210a may be disposed in the frame 224. In this case, an adhesive member 215a for attaching the first semiconductor die 210a to the frame 224 may be interposed between the first semiconductor die 210a and the frame 224. The adhesive member 215a may be a die attach film, a non-conductive film (NCF), an anisotropic conductive film (ACF), or the like, but is not limited thereto. In particular, when ACF is used, the connection means 237' may be omitted.

Referring to FIG. 8C, first to fourth semiconductor dies 210a, 210b, 210c, and 210d may be sequentially attached.

Referring to FIG. 8D, the first to fourth semiconductor dies 210a, 210b, 210c, and 210d are encapsulated with an encapsulant 220. The encapsulant 220 may be, for example, a material such as EMC, but is not limited thereto.

If a multi-stack package is manufactured using the package units according to the embodiments of the present invention, not only can it be manufactured quickly, but also a defective package unit among the package units tested for burn-in can be excluded in advance. The possibility that the whole is judged as defective can be greatly reduced. Conventionally, since the burn-in test was performed after manufacturing the entire package with all the semiconductor dies mounted, if all of the semiconductors are defective, the entire semiconductor package is judged as defective, resulting in a yield loss. There was an increasing problem.

In addition, the present invention does not stack a plurality of semiconductor dies sequentially, but stacks a package unit in which a plurality of semiconductor dies (four semiconductor dies in FIG. 1A) are stacked, so that manufacturing is simple, fast, and cost-effective It is cheaper.

Although described in detail with respect to the embodiments of the present invention as described above, those of ordinary skill in the art to which the present invention belongs, without departing from the spirit and scope of the present invention defined in the appended claims It will be possible to practice the present invention by various modifications. Therefore, changes to the embodiments of the present invention will not be able to depart from the technology of the present invention.

Claims (13)

A plurality of semiconductor dies each including an active surface and a non-active surface opposite to the active surface, and offset and stacked to partially expose the active surfaces;
A first encapsulation member covering the exposed active surface of the plurality of semiconductor dies, having first and second surfaces parallel to the active surface, and including a photosensitive insulating film;
A second encapsulation member different from the first encapsulation member, contacting the inactive surface, and covering the plurality of semiconductor dies;
Through vias extending from the first surface to the active surface through the first encapsulation member; And
Upper wirings connecting the through vias on a first surface of the first encapsulation member;
Including,
The second surface of the first encapsulation member is on the same plane as the inactive surface of the semiconductor die and the lowermost surface of the second encapsulation member. The method of claim 1,
The package unit, wherein the photosensitive insulating film is a polyimide resin. The method of claim 1,
And the first encapsulant covers the entire upper surface of the semiconductor die positioned at the top of the plurality of semiconductor dies. delete The method of claim 1,
The second encapsulant comprises an epoxy molding compound (EMC). delete A plurality of semiconductor dies each including an active surface and a non-active surface opposite to the active surface, and offset and stacked to partially expose the active surfaces;
A first encapsulation member covering the exposed active surface of the plurality of semiconductor dies, having first and second surfaces parallel to the active surface, and including a photosensitive insulating film;
A second encapsulation member different from the first encapsulation member, contacting the inactive surface, and covering the plurality of semiconductor dies;
Through vias extending from the first surface to the active surface through the first encapsulation member; And
Upper wirings connecting the through vias on a first surface of the first encapsulation member;
Including,
The package unit, further comprising a frame residual portion on at least one side of the first and second encapsulation bodies. The method according to claim 1 or 7,
Wherein the first encapsulant does not extend above the active surface of the uppermost semiconductor die. The method of claim 8,
The first surface of the first encapsulant is on the same plane as the active surface of the uppermost semiconductor die,
The package unit, wherein at least one of the upper wirings extends from the first surface to the active surface. Package substrate;
Two or more package units according to claim 1 or 7 stacked on the package substrate; And
A molding resin encapsulating the package units;
A multi-stack package containing. Forming a first encapsulant in the cavity of the frame;
Stacking a plurality of semiconductor dies in the cavity, and stacking the semiconductor dies in an offset manner so that active surfaces of each of the semiconductor dies are partially exposed;
Forming a second encapsulant including a photosensitive polymer to cover the exposed active surfaces by offsetting the semiconductor dies;
Forming through via holes exposing the active surface to the second encapsulant by a photolithography method;
Forming through vias in the through via holes;
Forming an upper wiring connecting the through vias on an upper surface of the second encapsulant;
A method of manufacturing a package unit comprising a. The method of claim 11,
The method of manufacturing a package unit, wherein the first encapsulant does not contain a photosensitive polymer. The method of claim 11,
The forming of the second encapsulant includes the step of covering the entire upper surface of the semiconductor die positioned at the top of the plurality of semiconductor dies with the second encapsulant.

Images