KR102171440B1 - Micro led driver capable of increasing bit number of source data - Google Patents

Abstract

The micro LED driver of the present invention includes a driving unit driven to generate a source signal having a duty corresponding to an activation width of a modulation clock and provide it to the source line of the display panel; A delay clock generator for generating first to n-th delay clocks sequentially delayed by a unit delay width with respect to the input clock (where n is a natural number of 2 or more); And a clock modulator for generating the modulation clock having a pulse width corresponding to the received source data by using at least a portion of the input clock and the first to (n-1)th delay clocks. The display panel driven by the micro LED driver of the present invention can display an image with high color gradation resolution.

Description

Micro LED driver capable of increasing the number of bits of source data {MICRO LED DRIVER CAPABLE OF INCREASING BIT NUMBER OF SOURCE DATA}

The present invention relates to a micro LED driver for driving a source line of a display panel, and to a micro LED driver capable of increasing the number of bits of source data used.

In general, a micro LED driver is an electronic circuit that generates a source signal having a duty corresponding to a code value of received source data and drives a source line of a display panel with the generated source signal.

At this time, the color gradation resolution of the image displayed on the display panel ultimately depends on the number of bits of the source data.

Therefore, in order to display an image with high color gradation resolution, a micro LED driver capable of increasing the number of bits of source data to be used is required.

An object of the present invention is to provide a micro LED driver capable of increasing the number of bits of source data to be used.

One aspect of the present invention for achieving the above object relates to a micro LED driver for driving a source line of a display panel. The micro LED driver of the present invention comprises: a driving unit driven to generate a source signal having a duty corresponding to an activation width of a modulation clock and provide it to the source line of the display panel; A delay clock generator for generating first to n-th delay clocks sequentially delayed by a unit delay width with respect to the input clock (where n is a natural number of 2 or more); And a clock modulator configured to generate the modulation clock having a pulse width corresponding to the received source data by using at least some of the first to (n-1)th delay clocks together with the input clock.

In the micro LED driver of the present invention having the above configuration, the main activation width and the additional code of the source data are generated in response to the clock width of the number of input clocks corresponding to the main code value of the source data. It is determined by the sum of the additional activation widths generated in response to the delay clock corresponding to the value. That is, in the micro LED driver of the present invention, the code value of the source data is constituted by adding an additional code value to the main code value. As a result, the display panel driven by the micro LED driver of the present invention can display an image with high color gradation resolution.

A brief description of each drawing used in the present invention is provided.
1 is a diagram showing a micro LED driver according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating generation of delay clocks in the micro LED driver of FIG. 1.
3 is a diagram for explaining a main activation width of a modulation clock according to a main code value of source data in the micro LED driver of FIG. 1.
4 is a diagram illustrating an additional activation width of a modulation clock according to an additional code value of source data in the micro LED driver of FIG. 1.
5 is a diagram for explaining that a delay control voltage is maintained in a standby period in the micro LED driver of FIG. 1.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the implementation of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed content may be thorough and complete, and the spirit of the present invention may be sufficiently conveyed to those skilled in the art.

And, in understanding each drawing, it should be noted that the same members are intended to be shown with the same reference numerals as much as possible. Further, detailed descriptions of known functions and configurations that are determined to unnecessarily obscure the subject matter of the present invention are omitted.

Meanwhile, in the present specification, reference numerals are added to <> together with the same reference numerals for elements performing the same configuration and operation. In this case, these components are collectively referred to by reference numerals. And, if it is necessary to distinguish them individually,'< >'is added after the reference sign.

In describing the contents of the present invention throughout the specification, the meanings of the terms'electrically connected','connected', and'connected' between individual constituent elements are not only direct connection, but also attributes more than a certain degree. It includes everything that is maintained and connected through an intermediate medium. Terms such as'transmitted' and'derived' of individual signals also include both direct meaning as well as indirect meaning through intermediate media while maintaining the properties of the signal to a certain extent. In addition, terms such as'applied,'applied', and'input' to a voltage or signal are all used in the same meaning throughout the specification.

Also, a plurality of expressions for each component may be omitted. For example, even a configuration consisting of a plurality of signal lines may be expressed as'signal lines' or in a singular number, such as'signal lines'. This is also because when a signal line is composed of multiple signal lines having the same property, for example, data signals, it is not necessary to separate them into singular and plural. In this respect, this description is reasonable. Therefore, similar expressions should also be interpreted as the same throughout the specification.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

1 is a diagram showing a micro LED driver 100 according to an embodiment of the present invention. Referring to FIG. 1, the micro LED driver 100 of the present invention generates a source signal VSC having a duty corresponding to source data SDAT received from an external source to generate a source line SL of a display panel DISPAN. Drive. Accordingly, the LED element PIX of the display panel DISPAN specified by the source line SL and the gate line GL is the duty of the source signal VSC, ultimately, the source data SDAT. It emits light according to the brightness. As a result, the display panel DISPAN displays an appropriate image.

Still referring to FIG. 1, the micro LED driver 100 of the present invention includes a driving unit 110, a delay clock generation unit 130, and a clock modulation unit 150.

The driving unit 110 generates a source signal VSC having a duty corresponding to the activation width (tDPK, see FIG. 4) of the modulation clock PCK generated by the clock modulator 150 to generate the display panel DISPAN. ) To the source line SL. Since the implementation of the driving unit 110 is obvious to those skilled in the art, detailed descriptions thereof are omitted in this specification.

The delay clock generator 130 generates first to nth delay clocks sequentially delayed with respect to the input clock ICK. Here, n is a natural number greater than or equal to 2, and is assumed to be '4' in this embodiment. That is, in the present embodiment, the delay clock generation unit 110 sequentially delays the first to fourth delay clocks DCK<1> to DCK<4> that are sequentially delayed by a unit delay width td with respect to the input clock ICK. ) Occurs.

Specifically, the delay clock generation unit 130 includes a delay generation unit 131 and a control unit 133.

The delay generating unit 131 includes first to fourth delay cells 131_1 to 131_4 connected in series to generate first to fourth delay clocks DCK<1> to DCK<4>. do.

Here, the first to fourth delay clocks DCK<1> to DCK<4> are sequentially delayed by the unit delay width td with respect to the input clock ICK, as shown in FIG. 2. . In this case, the unit delay width td depends on the level of the delay control voltage VCON, and ultimately, the delay control data DCON of the digital component.

Since the implementation of the delay generating unit 131 and the delay cells 131_1 to 131_4 included therein is obvious to those skilled in the art, a detailed description thereof will be omitted in this specification.

The control unit 133 generates the delay control voltage VCON by comparing the end of the input clock ICK and the fourth delay clock DCK<4>.

At this time, the level of the delay control voltage VCON is adjusted so that the end of the fourth delay clock DCK<4> corresponds to the end of the input clock ICK. In this embodiment, the level of the delay control voltage VCON is adjusted so that the leading end of the fourth delay clock DCK<4> coincides with the leading end of the input clock ICK.

As a result, the fourth delay clock DCK<4> is delayed by '1 clock' with respect to the input clock ICK, and the unit delay width td is the clock width tck of the input clock ICK. ) Is equivalent to 1/4 of

The clock modulator 150 generates the modulation clock PCK with a pulse width corresponding to the source data SDAT received from the input clock ICK.

Note that in this embodiment, the clock modulator 150 uses the first to third delay clocks DCK<1> to DCK3 together with the input clock ICK.

In addition, the source data SDAT is assumed to consist of a main code value MCD and an additional code value ACD. And, the main code value (MCD) is a code value generated by the upper bit of the source data (SDAT), the additional code value (ACD) is a code value generated by the lower bit of the source data (SDAT) to be.

On the other hand, the activation width (tDPK, see FIG. 4) of the modulation clock (PCK) may be composed of only the main activation width (tDMK, see FIG. 3), and an additional activation width (see tDMK, FIG. 3) tDAK, see FIG. 4) may be added.

Subsequently, the activation width (tDPK, see FIG. 4) of the modulation clock PCK generated by the clock modulation unit 150 will be described in detail.

In the micro LED driver 100 of the present invention, the main activation width (tDMK) of the modulation clock (PCK) corresponds to the main code value (MCD) of the source data (SDAT), as shown in FIG. It is generated corresponding to the clock width tck of the number of input clocks ICK.

In the example of FIG. 3, one frame FR forming one image corresponds to 64 clock widths tck. At this time, when the main code value (MCD) of the source data (SDAT) is <000011> (CSAE11), the main activation width (tDMK<1>) of the modulation clock (PCK) is of the input clock (PCK). It is three times the clock width (tck). And, when the main code value (MCD) of the source data (SDAT) is <111101> (CSAE12), the main activation width (tDMK<2>) of the modulation clock (PCK) is the input clock (PCK) It is equivalent to 62 times the clock width (tck).

In other words, in the example of FIG. 3, the main code value (MCD) of the source data (SDAT) may be formed with a maximum of 6 bits, and the main activation width (tDMK) of the modulation clock (PCK) is among 64 Become either. That is, when the brightness of the LED element PIX is determined only by the main code value MCD of the source data SDAT, 64 types are displayed.

By the way, in the micro LED driver 100 of the present invention, as shown in FIG. 4, the activation width tDPK of the modulation clock PCK is the main activation width tDMK plus an additional activation width tDAK. I can lose.

FIG. 4 is a diagram for explaining an additional activation width tDAK of the modulation clock PCK according to an additional code value ACD of the source data SDAT in the micro LED driver 100 of FIG. 1. In the example of FIG. 4, the main code value MCD of the source data SDAT is assumed to be'<000011>'.

CASE21 is a case where the additional code value MCD of the source data SDAT is <00>, and the total code value of the source data SDAT is'<00001100>. In this case, the activation width tDPK of the modulation clock PCK is a distance between the upper end of the first clock and the upper end of the fourth clock of the input clock ICK. That is, the activation width tDPK of the modulation clock PCK is the same as the main activation width tDMK. In this case, the additional activation width tDAK corresponds to '0'.

CASE22 is a case where the additional code value MCD of the source data SDAT is <01>, and the total code value of the source data SDAT is'<00001101>. In this case, the activation width tDPK of the modulation clock PCK is an interval between the upper end of the first clock of the input clock ICK and the fourth upper end of the first delay clock DCK<1>. That is, the activation width tDPK of the modulation clock PCK is equal to the main activation width tDMK plus a unit delay width td of one time. In this case, the additional activation width tDAK corresponds to '1 x td'.

CASE23 is a case where the additional code value MCD of the source data SDAT is <10>, and the total code value of the source data SDAT is'<00001110>. In this case, the activation width tDPK of the modulation clock PCK is an interval between the upper end of the first clock of the input clock ICK and the fourth upper end of the second delay clock DCK<2>. That is, the activation width tDPK of the modulation clock PCK is equal to the main activation width tDMK plus a unit delay width td of twice. In this case, the additional activation width tDAK corresponds to '2 x td'.

CASE24 is a case where the additional code value MCD of the source data SDAT is <11>, and the total code value of the source data SDAT is'<00001111>. In this case, the activation width tDPK of the modulation clock PCK is an interval between the upper end of the first clock of the input clock ICK and the fourth upper end of the third delay clock DCK<3>. That is, the activation width tDPK of the modulation clock PCK is equal to the main activation width tDMK plus a unit delay width td of 3 times. In this case, the additional activation width tDAK corresponds to '3 x td'.

In summary, in the micro LED driver 100 of the present invention, as described above, in the source data SDAT, an additional code value ACD of 2 bits is added to the main code value MCD of 6 bits. It can be composed of a code value of bits.

Accordingly, the LED element (PIX) of the display panel (DISPAN) driven by the micro LED driver 100 of the present invention is not 64 kinds of brightness based on all 6-bit source data (SDAT), but all 8-bit source data It can be controlled by 256 (=64x4) brightness by (SDAT).

As a result, the display panel (DISPAN) driven by the micro LED driver 100 of the present invention is much higher than when the activation width of the modulation clock (PCK) is controlled only by the end of the input clock (ICK). It is possible to display an image with color gradation resolution.

Referring back to FIG. 1, the control unit 133 includes an end comparator 133a, and preferably further includes a digital-analog converter 133b.

The end comparator 133a includes delay control data of a digital component such that the end of the fourth delay clock DCK<4> corresponds to the end of the input clock ICK (in this embodiment,'matches'). DCON) occurs.

Further, the digital-to-analog converter 133b converts the delay control data DCON of a digital component into the delay control voltage VCON of an analog component.

Since the implementation of the end comparator 133a and the digital-analog converter 133b of the control unit 133 is easy for those skilled in the art, detailed descriptions thereof are omitted herein.

Meanwhile, when an image is displayed on the display panel DISPAN, as shown in FIG. 5, between one frame (FR<1>) displaying one image and another frame (FR<2>), the There is a standby section ST in which the input clock ICK does not occur.

At this time, in the micro LED driver 100 of the present invention having the control unit 133 as described above, the locking time for controlling the delay control voltage VCON to a stabilization level VSTD is the first It occurs only in frame (FR<1>). First, the delay control voltage VCON controlled by the stabilization level VSTD is maintained even in the standby period ST in which the input clock ICK does not occur. As a result, the locking time (tlock) is not consumed from the second frame (FR<2>).

On the other hand, when the delay control voltage VCON of the analog component is directly generated without generation of the delay control data DCON of the digital component, the delay control voltage VCON in the standby period ST is the stabilization level ( VSTD). As a result, even in the second frame (FR<2>), a locking time (tlock) is required for the delay control voltage (VCON) to be controlled to the stabilization level (VSTD) again (see'A' in FIG. 5).

That is, in the micro LED driver 100 of the present invention, in order to control the unit delay width of the delay generating unit 131, delay control data DCON of a digital component whose value does not change in the standby period ST is once generated. do. In addition, the unit delay width of the delay generating unit 131 is ultimately controlled by the delay control data DCON. Therefore, the micro LED driver 100 of the present invention is more stable and can be driven immediately compared to the case of directly generating the delay control voltage VCON of the analog component without generating the delay control data DCON of the digital component. You will have an advantage.

As described above, although the embodiments have been described by the limited embodiments and drawings, various modifications and variations are possible from the above description by those of ordinary skill in the art. For example, the described techniques are performed in a different order from the described method, and/or components such as a system, structure, device, circuit, etc. described are combined or combined in a form different from the described method, or other components Alternatively, even if substituted or substituted by an equivalent, an appropriate result can be achieved.

As an example, in this specification, an embodiment in which the unit delay width of the delay generating unit 131 depends on the level of the delay control voltage VCON of the analog component converted from the delay control data DCON of the digital component is shown and described. . However, the technical idea of the present invention can also be implemented by an embodiment in which the delay generating unit 131 is directly controlled by the delay control data (DCON) of the digital component rather than the delay control voltage of the analog component.

In addition, in the present specification, an embodiment in which the activation width of the modulation clock PCK generated by the clock modulator 150 is determined in response to the upper end of the input clock ICK and/or the delay clock DCK is shown. And described. However, the technical idea of the present invention can also be implemented by an embodiment in which the activation width of the modulation clock (PCK) is determined in response to not only the upper end of the input clock (ICK) and/or the delay clock (DCK) but also the falling end. It is obvious to those skilled in the art.

Therefore, the true technical protection scope of the present invention should be determined by the technical idea of the attached registration claims.

Claims (6)

In the micro LED driver driving the source line of the display panel,
A driving unit driven to generate a source signal having a duty corresponding to an activation width of a modulation clock and provide it to the source line of the display panel;
A delay clock generator for generating first to n-th delay clocks sequentially delayed by a unit delay width with respect to the input clock (where n is a natural number of 2 or more); And
And a clock modulator for generating the modulation clock having a pulse width corresponding to the received source data by using at least a portion of the first to (n-1)th delay clocks together with the input clock. LED driver.
The method of claim 1, wherein the delay clock generator
A delay generating unit that sequentially delays the input clock by the unit delay width to generate the first to n-th delay clocks, the unit delay width being dependent on delay control data of a digital component; And
A control unit for generating the delay control data by comparing the input clock with an end of the n-th delay clock, wherein a value of the delay control data is adjusted such that an end of the n-th delay clock corresponds to an end of the input clock. Micro LED driver comprising the control unit.
The method of claim 2, wherein the control unit
And an end comparator for generating delay control data of a digital component such that an end of the n-th delay clock corresponds to an end of the input clock.
The method of claim 2, wherein the control unit
Further comprising a digital-to-analog converter for converting the delay control data of the digital component to the delay control voltage of the analog component,
The unit delay width of the delay generating unit is
Micro LED driver, characterized in that controlled by the level of the delay control voltage.
The method of claim 1, wherein the source data is
It consists of a main code value and an additional code value,
The activation width of the modulation clock is
Micro LED driver, characterized in that the sum of the main activation width and the additional activation width.
The method of claim 5, wherein the main activation width of the modulation clock is
It is generated corresponding to the clock width of the input clock of the number corresponding to the main code value of the source data,
The additional activation width of the modulation clock is
The micro LED driver, characterized in that generated in response to an i-th delay clock corresponding to the additional code value of the source data (where i is a natural number of 1 or more and (n-1) or less).

Images