KR102157326B1 - Computing apparutus, method for scaling memory bandwidth thereof and memory bandwidth scaler - Google Patents

Abstract

It relates to a method of dynamically adjusting a bandwidth of an external memory by activating or deactivating each of a plurality of input/output terminals provided in an external memory according to a dynamic situation of a processor. A method for adjusting a memory bandwidth according to an aspect includes the steps of collecting dynamic situation information indicating a dynamic situation of a processor, and determining the dynamic situation of the processor based on the dynamic situation information, and at least part of a plurality of input/output terminals according to the dynamic situation. And dynamically adjusting the bandwidth through the plurality of input/output terminals by activating or deactivating for each input/output terminal.

Description

A computing device, a method of adjusting the memory bandwidth of a computing device, and a memory bandwidth adjuster TECHNICAL FIELD [COMPUTING APPARUTUS, METHOD FOR SCALING MEMORY BANDWIDTH THEREOF AND MEMORY BANDWIDTH SCALER}

A computing device, a method of adjusting a memory bandwidth of a computing device, and a memory bandwidth adjuster. More specifically, a computing device that dynamically adjusts the bandwidth of an external memory by activating or deactivating each of a plurality of input/output (I/O) terminals provided in an external memory (off-chip) according to the dynamic situation of the processor, computing It relates to a method of adjusting a memory bandwidth of a device and a memory bandwidth adjuster.

In order to execute an application program requiring a large amount of data processing such as image processing, audio processing, and 3D graphics in a computing device, an external memory is required in addition to a processor. The increase in the bandwidth of the external memory used by the computing device increases the input/output power of the memory, thereby increasing the power consumption of the computing device.

An object of the present invention is to provide a computing device that dynamically adjusts the bandwidth of an external memory by activating or deactivating a plurality of input/output terminals provided in the external memory according to the dynamic situation of the processor, a memory bandwidth adjustment method of the computing device, and a memory bandwidth adjuster. To do.

A method for adjusting a memory bandwidth according to an aspect includes the steps of: collecting dynamic situation information indicating a dynamic situation of a processor; And determining the dynamic situation of the processor based on the dynamic situation information, and activating or deactivating at least a part of the plurality of input/output terminals for each input/output terminal according to the dynamic situation, thereby dynamically adjusting the bandwidth through the plurality of input/output terminals. It includes; adjusting step.

A memory bandwidth adjuster according to another aspect includes: a dynamic situation information collection unit indicating a dynamic situation of a processor; And determining the dynamic situation of the processor based on the dynamic situation information, and activating or deactivating at least a part of the plurality of input/output terminals for each input/output terminal according to the dynamic situation, thereby dynamically adjusting the bandwidth through the plurality of input/output terminals. It includes; a port opening and closing part to adjust.

A method of adjusting a memory bandwidth according to another aspect includes determining a dynamic state of a processor; And adjusting the bandwidth between the processor and the memory without changing the voltage or frequency based on the dynamic situation.

By adjusting the bandwidth of the external memory at the input/output terminal level in consideration of the dynamic situation of the processor, the bandwidth of the external memory can be dynamically adjusted according to the memory bandwidth required according to the workload of the application program.

Through this, it is possible to reduce leakage energy consumed in an external memory having a high bandwidth, thereby reducing power consumption due to execution of an application program.

1 is a diagram illustrating a computing device including a processor, an external memory, and a memory bandwidth adjuster.
2 is a flowchart illustrating a method of adjusting a memory bandwidth of a computing device.
3A to 3C are flowcharts illustrating in more detail steps of adjusting the bandwidth of the method of adjusting the memory bandwidth of FIG. 2.
4 is another flowchart illustrating a method of adjusting a memory bandwidth of a computing device.
5 is a diagram illustrating a memory bandwidth adjuster.
6 is another diagram illustrating a memory bandwidth adjuster.

Hereinafter, a specific example for implementation will be described in detail with reference to the accompanying drawings.

1 is a diagram illustrating a computing device including a processor, an external memory, and a memory bandwidth adjuster.

Referring to FIG. 1, the computing device 100 includes a processor 10, an external memory 30, and a memory bandwidth adjuster 50. The computing device 100 according to an exemplary embodiment may be a device that executes an application program requiring a large amount of data processing such as image processing, audio processing, and 3D graphics. For example, the computing device 100 may be one of a video signal processing device, an audio signal processing device, or a high-speed computer. Alternatively, the computing device 100 may be implemented as a single-chip system (SoC) including a processor 10, an external memory 30, and a memory bandwidth adjuster 50.

The processor 10 supports access to the external memory 30 and may process data transmitted from the external memory 30. The processor 10 according to an embodiment may be an operation processing device for processing a large amount of data such as image processing, audio processing, and 3D graphics. For example, the processor 10 may be any one of a central processing unit (CPU), a graphic processing unit (GPU), and a digital signal processor (DSP). The processor 10 may provide information on various events occurring internally to the outside in various ways. For example, the processor 10 may provide information about an event to the outside in a manner that adjusts a value of a specific register at the time when a specific event occurs. Event information provided by such a process may be used as dynamic situation information indicating a dynamic situation of the processor 10.

The external memory 30 is an off-chip memory that stores various programs and data necessary for operation and operation of the computing device 100 and may include a plurality of input/output terminals for data transmission with the processor 10. Here, the input/output terminal means an input/output port for data transmission, an input/output pin, and the like. The external memory 30 can transmit data to the processor 10 only when the input/output terminal is activated. The external memory 30 according to an exemplary embodiment may be a memory device having a high memory bandwidth to effectively support the processor 10. For example, the external memory 30 may be a 3D stacking DRAM.

The memory bandwidth adjuster 50 dynamically adjusts the bandwidth of the external memory 30 without adjusting the processor voltage or frequency by activating or deactivating each of a plurality of input/output terminals provided in the external memory 30 according to the dynamic situation of the processor 10. Can be adjusted. The memory bandwidth adjuster 50 will be described in detail below with reference to FIGS. 5 and 6.

The computing device 100 may finely adjust the memory bandwidth by adjusting the bandwidth of the external memory 30 at the input/output terminal level. In addition, by adjusting the bandwidth of the external memory 30 in consideration of the dynamic situation of the processor, the computing device 100 dynamically adjusts the bandwidth of the external memory 30 according to the memory bandwidth required according to the workload of the application program. Can be adjusted. Through this, it is possible to reduce the leakage energy consumed in the external memory 30 having a high bandwidth, it is possible to reduce power consumption according to the execution of the application program.

2 is a flowchart illustrating a method of adjusting a memory bandwidth of a computing device. Referring to FIG. 2, the memory bandwidth adjustment method includes a dynamic context information collection step 210 and a bandwidth adjustment step 230.

The dynamic context information collection step 210 collects dynamic context information indicating an operation or state of the processor 10. For example, the dynamic context information may be information about a specific event occurring in the processor 10 or information about a specific event processed by the processor 10. Information about a specific event is provided by the processor 10. As another example, the dynamic context information may be information on a cache miss rate of the processor 10. As another example, the dynamic context information may be information on the number of instructions per cycle (IPC) processed by the processor 10. As another example, the dynamic context information may be information on access to a buffer memory of the processor 10.

The dynamic context information collecting step 210 according to an embodiment may collect dynamic context information by reading a specific register value of the processor 10. The dynamic context information collection step 210 according to another embodiment may collect dynamic context information through a means previously implemented in a BIOS (basic input output system) or an operating system (OS). The dynamic context information collection step 210 according to another embodiment may collect dynamic context information through a separately provided device.

The bandwidth adjustment step 230 may adjust the bandwidth of the external memory 30 by activating or deactivating at least some of the plurality of input/output terminals provided in the external memory 30 based on the collected dynamic situation information. In the embodiment of FIG. 2, activating an input/output terminal may mean connecting an input/output terminal (I/O terminal) to (switch on). In addition, deactivating the input/output terminal may mean opening the input/output terminal (switch off). The I/O terminal can also be expressed as an I/O port or simply a port.

In the embodiment of FIG. 2, as a result of analyzing the collected dynamic situation information, it may be determined that a wider bandwidth is required. In this case, when at least some of the inactive input/output terminals among the plurality of input/output terminals are activated, the bandwidth is extended by a degree corresponding to the newly activated input/output terminal. Similarly, as a result of analyzing the collected dynamic situation information, it can be determined that a narrower bandwidth is sufficient. In this case, if at least some of the activated input/output terminals among the plurality of input/output terminals are deactivated, the bandwidth is reduced by a degree corresponding to the newly deactivated input/output terminals.

In order to adjust the bandwidth, there is also a technique of varying the frequency alone or the voltage and frequency together. However, in the case of a circuit driven by a low voltage, the swing width of the voltage is narrow. Therefore, the bandwidth adjustment range is small, and it is difficult to fine-tune the bandwidth. Therefore, according to the technique of adjusting the bandwidth by varying only the frequency or voltage and frequency, it is common that the number of steps capable of adjusting the bandwidth is limited to several.

On the other hand, in the embodiment of FIG. 2, by opening and closing a plurality of input/output terminals in units of pins, it is possible to finely control the expansion and reduction of a bandwidth. For example, in the case of an existing 3D stacked DRAM having multiple input/output terminals, the number of bandwidth steps between the minimum bandwidth and the maximum bandwidth is thousands. Further, as in the embodiment of FIG. 2, a technique of adjusting the bandwidth by opening and closing a plurality of input/output terminals in units of pins can be implemented through a simple logic circuit compared to a technique of adjusting a voltage to adjust the bandwidth. This is because the already implemented tri-state pin can be used.

3A is a flowchart illustrating an example of a bandwidth adjustment step of the method of FIG. 2 in more detail.

Referring to FIG. 3A, the bandwidth adjustment step 230 may determine a change in dynamic performance of the processor 10 based on the collected dynamic situation information (231a). In addition, the bandwidth adjustment step 230 may adjust the bandwidth of the external memory 30 by activating or deactivating each of the input/output terminals provided in the external memory 30 according to the determined result (233a).

In step 231a, as a result of analyzing the collected dynamic situation information, it may be determined that a wider bandwidth is required according to a change in dynamic performance of the processor 10. In this case, when at least some of the inactive input/output terminals among the plurality of input/output terminals are activated in the bandwidth adjustment step 233a, the bandwidth is extended by a degree corresponding to the newly activated input/output terminal. The bottleneck occurring at the input/output terminal is improved through bandwidth expansion, and the overall processing performance can be improved.

Likewise, as a result of analyzing the collected dynamic situation information in step 231a, it may be determined that a narrower bandwidth is sufficient according to a change in dynamic performance of the processor 10. In this case, if at least some of the activated input/output terminals among the plurality of input/output terminals are deactivated in the bandwidth adjustment step 233a, the bandwidth is reduced by a degree corresponding to the newly deactivated input/output terminals. By reducing the power consumed in the input/output terminal through the reduction of the bandwidth, it is possible to improve the overall power efficiency.

3B is a flowchart illustrating another example of a bandwidth adjustment step of the memory bandwidth adjustment method of FIG. 2 in more detail.

Referring to FIG. 3B, the bandwidth adjustment step 230 compares the collected cache failure rate with a preset threshold to change the dynamic performance of the processor 10 according to the increase in data waiting time due to the external memory 30. Can be determined (231b). In addition, the bandwidth adjustment step 230 may adjust the bandwidth of the external memory 30 by activating or deactivating each of the input/output terminals provided in the external memory 30 according to the determined result (233a). In step 231b, as a result of comparing the collected cache failure rate and the threshold value, it may be determined that a wider bandwidth is required according to the dynamic performance change of the processor 10. In this case, when at least some of the inactive input/output terminals among the plurality of input/output terminals are activated in the bandwidth adjustment step 233b, the bandwidth is extended by a degree corresponding to the newly activated input/output terminals. The bottleneck occurring at the input/output terminal is improved through bandwidth expansion, and the overall processing performance can be improved.

For example, if the cache failure rate is higher than the threshold value, it means that the waiting time for data from the external memory 30 is increased. When the data waiting time increases, the dynamic performance of the processor 10 decreases. Therefore, if the cache failure rate is higher than the threshold value, it is determined that the dynamic performance of the processor 10 is reduced, and by newly activating at least some of the inactive input/output terminals, the bandwidth is increased by the amount corresponding to the newly activated input/output terminals. Can increase.

For another example, the bandwidth adjustment step 230 may compare a cache failure rate of a predetermined number of recently continuously collected and a preset limit value. If the number of times it is determined that the cache failure rate is higher than the threshold value is more than a certain number, it may be determined that the dynamic performance of the processor 10 has decreased. For example, if three or more of the recently collected five cache failure rates are higher than the threshold value, it may be determined that the dynamic performance of the processor 10 has decreased. When determining the change in the dynamic performance of the processor 10 by comparing a plurality of cache failure rates and the threshold value, it is possible to more accurately determine the change in the dynamic performance of the processor 10 than comparing a single cache failure rate and the threshold value. I can.

Likewise, in step 231b, as a result of comparing the collected cache failure rate and the threshold value, it may be determined that a narrower bandwidth is sufficient according to the dynamic performance change of the processor 10. In this case, if at least some of the activated input/output terminals among the plurality of input/output terminals are deactivated in the bandwidth adjustment step 233b, the bandwidth is reduced by a degree corresponding to the newly deactivated input/output terminals. By reducing the power consumed in the input/output terminal through the reduction of the bandwidth, it is possible to improve the overall power efficiency.

3C is a detailed flowchart illustrating another example of a bandwidth adjustment step of the memory bandwidth adjustment method of FIG. 2.

Referring to FIG. 3C, the bandwidth adjustment step 230 calculates an average value for instructions per cycle collected over a certain period according to a preset criterion, detects a change in the calculated average value, and detects a change in the parallel operation performance of the processor. (10) It is possible to judge the change in dynamic performance. In addition, in the bandwidth adjustment step 230, the bandwidth of the external memory may be dynamically adjusted by activating or deactivating each of the input/output terminals provided in the external memory 30 according to the determined result (233c).

In step 231c, as the collected instruction per cycle (IPC) changes, the dynamic performance of the processor 10 deteriorates, and it may be determined that a wider bandwidth is required. In this case, when at least some of the inactive input/output terminals among the plurality of input/output terminals are activated in the bandwidth adjustment step 233b, the bandwidth is extended by a degree corresponding to the newly activated input/output terminals. The bottleneck occurring at the input/output terminal is improved through bandwidth expansion, and the overall processing performance can be improved.

For example, based on the collected instruction per cycle, the average value of the instruction per cycle of a certain interval is calculated according to a preset criterion, and when a decrease in the average value of the calculated instruction per cycle is detected, the dynamic performance of the processor 10 is reduced. It can be judged as. (231c) For example, if the average value of the recently collected 5 instructions per cycle decreases from the previous average value, it may be determined that the dynamic performance of the processor 10 has decreased. Alternatively, when the average value of the recently collected instructions per cycle of five times becomes smaller than the preset reference IPC value, it may be determined that the dynamic performance of the processor 10 has decreased. When it is determined that the dynamic performance of the processor 10 has decreased, the bandwidth of the external memory 30 may be increased by further activating the power of the input/output terminal. In the bandwidth adjustment step 233c, when at least some of the inactive input/output terminals among the plurality of input/output terminals are activated, the bandwidth is extended by a degree corresponding to the newly activated input/output terminal. The bottleneck occurring at the input/output terminal is improved through bandwidth expansion, and the overall processing performance can be improved.

Likewise, in step 231c, it may be determined that the dynamic performance of the processor 10 is improved based on the increase in the average value of the instruction per cycle. Accordingly, in consideration of the tradeoff between dynamic performance and power consumption of the processor 10, it may be determined that it is sufficient to use a narrower bandwidth. In this case, at least a part of the active input/output terminals among the plurality of input/output terminals may be deactivated in the bandwidth adjustment step 233c. The bandwidth is reduced by the amount corresponding to the newly deactivated input/output terminal. By reducing the power consumed in the input/output terminal through the reduction of the bandwidth, it is possible to improve the overall power efficiency.

FIG. 3D is a flowchart illustrating still another example of a bandwidth adjustment step of the memory bandwidth adjustment method of FIG. 2 in more detail. The bandwidth adjustment step 230 may determine a dynamic performance change of the processor 10 based on the collected two or more dynamic situation information, and adjust the bandwidth of the external memory 30 according to the determined result. For example, in FIG. 3D, a change in dynamic performance of the processor 10 is determined based on two types of dynamic situation information such as a cache failure rate and an instruction per cycle.

Referring to FIG. 3D, the bandwidth adjustment step 230 compares the collected cache failure rate with a preset threshold to change the dynamic performance of the processor 10 according to the increase in data waiting time due to the external memory 30. Can be determined (231bd). In addition, in step 231cd, as the collected instruction per cycle (IPC) changes, it is possible to determine a change in dynamic performance of the processor 10.

In step 232, based on the determination results in steps 231bd and 231cd, it is determined whether the bandwidth should be expanded or reduced, or whether the bandwidth should not be adjusted.

For example, if it is determined in step 232 that the bandwidth should be extended, when at least some of the inactive input/output terminals among the plurality of input/output terminals are activated in the bandwidth adjustment step 233d, the degree corresponding to the newly activated input/output terminal The bandwidth is extended as much. The bottleneck occurring at the input/output terminal is improved through bandwidth expansion, and the overall processing performance can be improved.

Likewise, when it is determined in step 232 that the bandwidth should be reduced, at least a part of the active input/output terminals among the plurality of input/output terminals may be deactivated in the bandwidth adjustment step 233d. The bandwidth is reduced by the amount corresponding to the newly deactivated input/output terminal. By reducing the power consumed in the input/output terminal through the reduction of the bandwidth, it is possible to improve the overall power efficiency.

In addition, when it is determined in step 232 that the current bandwidth should be maintained without adjusting the bandwidth, the bandwidth is not expanded or reduced, and the current bandwidth is maintained (234d).

4 is another flowchart illustrating a method of adjusting a memory bandwidth of a computing device.

Referring to FIG. 4, the memory bandwidth adjustment method includes a dynamic context information collection step 210, a bandwidth adjustment step 230, and a bandwidth default reduction step 250. Since the dynamic context information collection step 210 and the bandwidth adjustment step 230 are the same as those described above with reference to FIGS. 2 and 3A to 3D, only the bandwidth default reduction step 250 will be described in detail below.

The bandwidth default reduction step 250 may reduce the bandwidth of the external memory to the default bandwidth when there is no change in the dynamic performance of the processor even when the bandwidth of the external memory is adjusted based on the collected dynamic situation information. In other words, when it is determined that the change in the dynamic performance of the process 10 is not related to the memory bandwidth, the bandwidth of the external memory 30 is reduced to the default bandwidth. For example, even though the bandwidth reaches the maximum bandwidth by adjusting the memory bandwidth based on the collected cache failure rate, the cache failure rate collected afterwards may be kept higher than the threshold value. In this case, it is determined that the change in the dynamic performance of the process determined based on the cache failure rate collected in the bandwidth default reduction step 250 is not related to the memory bandwidth, and the memory bandwidth of the external memory 30 can be reduced to the default bandwidth. have. By reducing the extended bandwidth to the default bandwidth irrespective of the change in the dynamic performance of the process, power consumption caused by the extended bandwidth can be reduced. As a result, overall power efficiency is improved.

For another example, even though the bandwidth has reached the maximum bandwidth by adjusting the memory bandwidth of the external memory 30 based on the collected instructions per cycle, the average value of instructions per cycle calculated thereafter may continue to decrease. In this case, it is determined that the change in the dynamic performance of the process determined based on the collected instructions per cycle is not related to the memory bandwidth, and thus the memory bandwidth of the external memory 30 may be reduced to the default bandwidth.

Meanwhile, the method for adjusting a memory bandwidth according to an exemplary embodiment may be implemented as a computer-readable code on a computer-readable recording medium. The computer-readable recording medium includes all types of recording devices storing data that can be read by a computer system.

5 is a diagram illustrating a memory bandwidth adjuster.

Referring to FIG. 5, the memory bandwidth adjuster 50 includes a dynamic situation information collection unit 51 and a port opening/closing unit 53.

The dynamic situation information collection unit 51 collects at least one dynamic situation information representing a dynamic situation of the processor 10. In this case, the dynamic context information collection unit 51 may be a means implemented in advance in a BIOS or an operating system, but may be a separately implemented device for collecting dynamic context information. For example, the dynamic context information may be information about a specific event of the processor provided by the processor 10. For another example, the dynamic context information may be at least one of a cache failure rate or an instruction per cycle.

The port opening/closing unit 53 may adjust the bandwidth of the external memory 30 by activating or deactivating at least some of the plurality of input/output terminals provided in the external memory 30 based on the collected dynamic situation information. Activation or deactivation can be performed for each input/output terminal. For example, the port opening/closing unit 53 can disable the input/output terminal by switching off the input/output terminal on the memory interface. Also, by switching on the input/output terminals, the input/output terminals can be activated.

The port opening/closing unit 53 according to an embodiment may determine a change in dynamic performance of the processor 10 by comparing the collected cache failure rate with a preset limit value. For example, when the cache failure rate is high, since the data waiting time increases, it may be determined that the dynamic performance of the processor 10 is deteriorated. Likewise, when the cache failure rate is low, the data waiting time is shortened, so it can be determined that the dynamic performance of the processor 10 is improved. The port opening/closing unit 53 may adjust the bandwidth of the external memory 30 by activating or deactivating, respectively, a plurality of input/output terminals provided in the external memory 30 according to the determined result.

The port opening/closing unit 53 according to another exemplary embodiment may determine a change in dynamic performance of the processor 10 in advance based on an average value of instructions per cycle. For example, according to a set criterion, an average value for commands per cycle collected during a certain period may be calculated and a change in the calculated average value may be detected. Further, the port opening/closing unit 53 may dynamically adjust the bandwidth of the external memory by activating or deactivating each of the input/output terminals provided in the external memory 30 according to the determined result.

The port opening/closing unit 53 according to another embodiment determines the dynamic performance change of the processor 10 based on the collected two or more dynamic situation information (cache miss rate, instruction per cycle, etc.), and the external memory according to the determined result. You can adjust the bandwidth of 30.

The memory bandwidth adjuster 50 may finely adjust the memory bandwidth by adjusting the bandwidth of the external memory 30 at the input/output terminal level. In addition, the memory bandwidth adjuster 50 adjusts the bandwidth of the external memory 30 in consideration of the dynamic situation of the processor, so that the bandwidth of the external memory 30 is dynamically adjusted according to the memory bandwidth required according to the workload of the application program. Can be adjusted with Through this, it is possible to reduce the leakage energy consumed in the external memory 30 having a high bandwidth, it is possible to reduce power consumption according to the execution of the application program.

6 is another diagram illustrating a memory bandwidth adjuster.

Referring to FIG. 6, the memory bandwidth adjuster 50 includes a dynamic situation information collection unit 51, a port opening/closing unit 53, and a bandwidth default reduction unit 55. Since the dynamic situation information collection unit 51 and the memory port opening/closing unit 53 are the same as those described above with reference to FIG. 5, only the bandwidth default reduction unit 55 will be described in detail below.

The bandwidth default reduction unit 55 may reduce the bandwidth of the external memory to the default bandwidth when there is no change in the dynamic performance of the processor even though the bandwidth of the external memory is adjusted based on the collected dynamic situation information. In other words, when it is determined that the change in the dynamic performance of the process 10 determined based on the collected dynamic situation information is not related to the memory bandwidth, the bandwidth default reduction unit 55 defaults the bandwidth of the external memory 30. It is reduced to bandwidth.

For example, the bandwidth default reduction unit 55 adjusts the memory bandwidth based on the collected cache failure rate, and if the collected cache failure rate continues to be higher than the limit value even though the bandwidth reaches the maximum bandwidth, based on the collected cache failure rate. It is determined that the determined change in the dynamic performance of the process is not related to the memory bandwidth, and the memory bandwidth of the external memory 30 may be reduced to the default bandwidth.

For another example, the bandwidth default reduction unit 55 adjusts the memory bandwidth of the external memory 30 based on the collected instructions per cycle, so that even though the bandwidth reaches the maximum bandwidth, the average value of instructions per cycle calculated afterwards continues to decrease. In this case, it is determined that the change in the dynamic performance of the process determined based on the collected instructions per cycle is not related to the memory bandwidth, and thus the memory bandwidth of the external memory 30 may be reduced to the default bandwidth.

The bandwidth default reduction unit 55 may reduce the memory bandwidth to the default bandwidth through the port opening/closing unit 53.

The above-described embodiments are for illustrative purposes only and the scope of rights is not limited to these specific embodiments.

Claims (31)

Collecting dynamic situation information indicating a dynamic situation of the processor; And
The dynamic situation of the processor is determined based on the dynamic situation information, and at least a part of the plurality of input/output terminals is activated or deactivated for each input/output terminal based on the determined dynamic situation, thereby reducing the bandwidth through the plurality of input/output terminals. Including; dynamically adjusting
The plurality of input/output terminals are input/output terminals for a memory connected to the processor. The method of claim 1,
The step of dynamically adjusting the bandwidth,
If the bandwidth needs to be expanded according to the dynamic situation, newly activating at least some of the inactive input/output terminals among the plurality of input/output terminals. The method of claim 1,
The step of dynamically adjusting the bandwidth,
If the bandwidth needs to be reduced according to the dynamic situation, the step of newly deactivating at least some of the active input/output terminals among the plurality of input/output terminals. The method of claim 1,
The dynamic context information is at least one of a cache failure rate and a number of instructions per cycle processed by the processor. delete delete delete delete delete The method of claim 1,
After the step of dynamically adjusting the bandwidth,
If there is no relationship between the dynamic situation of the processor and the adjusted bandwidth, reducing the adjusted bandwidth to a default bandwidth; memory bandwidth adjustment method comprising a. The method of claim 10,
In the reducing step,
A memory bandwidth adjustment method for determining the presence or absence of the relationship based on dynamic situation information after the bandwidth is adjusted. The method of claim 1,
After the step of dynamically adjusting the bandwidth,
If the dynamic situation is not improved even though the bandwidth is adjusted to the maximum bandwidth, reducing the adjusted bandwidth to a default bandwidth; the memory bandwidth adjustment method further comprising. A dynamic situation information collection unit indicating a dynamic situation of the processor; And
The dynamic situation of the processor is determined based on the dynamic situation information, and at least some of the plurality of input/output terminals are activated or deactivated for each input/output terminal according to the determined dynamic situation, thereby dynamically adjusting the bandwidth through the plurality of input/output terminals. Includes; a port opening and closing portion to adjust,
The bandwidth is between the processor and the memory. The method of claim 13,
The port opening and closing part,
When the bandwidth needs to be expanded according to the dynamic situation, a memory bandwidth adjuster newly activating at least some of the inactive input/output terminals among the plurality of input/output terminals. The method of claim 13,
The port opening and closing part,
When the bandwidth needs to be reduced according to the dynamic situation, a memory bandwidth adjuster that newly deactivates at least some of the active input/output terminals among the plurality of input/output terminals. The method of claim 13,
The dynamic context information is at least one of a cache failure rate and a number of instructions per cycle processed by the processor. delete delete delete delete delete The method of claim 13,
After dynamically adjusting the bandwidth, if there is no relationship between the dynamic situation of the processor and the adjusted bandwidth, a bandwidth default reduction unit for reducing the adjusted bandwidth to a default bandwidth; memory bandwidth adjuster further comprising a. The method of claim 22,
The bandwidth default reduction unit is a memory bandwidth adjuster that determines whether or not the association exists based on dynamic situation information after the bandwidth is adjusted. The method of claim 22,
The bandwidth default reduction unit, when the dynamic situation is not improved even though the bandwidth is adjusted to the maximum bandwidth, a memory bandwidth adjuster for reducing the adjusted bandwidth to a default bandwidth. Determining a dynamic situation of the processor; And
Adjusting the bandwidth between the processor and the memory without changing a voltage or frequency based on the dynamic situation. The method of claim 25,
The adjusting step,
When extending the bandwidth based on the dynamic situation, newly activating at least some of the inactive input/output terminals among the plurality of input/output terminals. The method of claim 25,
The adjusting step,
If the bandwidth is reduced based on the dynamic situation, the step of newly deactivating at least some of the active input/output terminals among the plurality of input/output terminals. The method of claim 25,
The dynamic situation is at least one of a cache failure rate of the processor and a number of instructions per cycle processed by the processor. delete The method of claim 25,
After the step of adjusting,
If there is no relationship between the dynamic situation of the processor and the adjusted bandwidth, reducing the adjusted bandwidth to a default bandwidth; memory bandwidth adjustment method comprising a. The method of claim 30,
In the reducing step,
The memory bandwidth adjustment method of determining the presence or absence of the association based on a dynamic situation after the bandwidth is adjusted.

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