[go: up one dir, main page]

KR102117726B1 - Crimping device and crimping method - Google Patents

Crimping device and crimping method Download PDF

Info

Publication number
KR102117726B1
KR102117726B1 KR1020157002389A KR20157002389A KR102117726B1 KR 102117726 B1 KR102117726 B1 KR 102117726B1 KR 1020157002389 A KR1020157002389 A KR 1020157002389A KR 20157002389 A KR20157002389 A KR 20157002389A KR 102117726 B1 KR102117726 B1 KR 102117726B1
Authority
KR
South Korea
Prior art keywords
sheet
elastic sheet
chip
substrate
substrate stage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020157002389A
Other languages
Korean (ko)
Other versions
KR20150036254A (en
Inventor
가츠미 데라다
사토루 나라바
Original Assignee
토레이 엔지니어링 컴퍼니, 리미티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 토레이 엔지니어링 컴퍼니, 리미티드 filed Critical 토레이 엔지니어링 컴퍼니, 리미티드
Publication of KR20150036254A publication Critical patent/KR20150036254A/en
Application granted granted Critical
Publication of KR102117726B1 publication Critical patent/KR102117726B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67132Apparatus for placing on an insulating substrate, e.g. tape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/75251Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/75252Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/753Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301Bonding head
    • H01L2224/75314Auxiliary members on the pressing surface
    • H01L2224/75317Removable auxiliary member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7598Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/832Applying energy for connecting
    • H01L2224/83201Compression bonding
    • H01L2224/83203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83862Heat curing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9211Parallel connecting processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

기판에 접착제를 통해 가압착된 복수의 칩을 실장 어긋남을 발생시키는 일 없이 기판에 일괄 압착하는 것이 가능한 압착 장치 및 압착 방법을 제공하는 것이다. 구체적으로는, 칩이 압착되는 기판의 이면을 흡착 보유 지지하는 기판 스테이지와, 가압착한 칩의 표면을 덮는 탄성 시트와, 상기 기판 스테이지의 외주에 위치하고, 상기 탄성 시트를 보유 지지하는 시트 보유 지지 수단과, 상기 시트 보유 지지 수단과 상기 탄성 시트와 상기 기판 스테이지에 의해 형성된 밀폐 공간을 감압하는 감압 수단과, 탄성 시트를 통해 기판 상의 칩에 소정의 가압력을 부여하는 본딩 헤드를 구비하고 있는 압착 장치 및 압착 방법을 제공한다.It is to provide a crimping apparatus and a crimping method capable of collectively crimping a plurality of chips pressed through an adhesive to the substrate without causing mounting misalignment. Specifically, the substrate stage for adsorbing and holding the back surface of the substrate on which the chip is pressed, the elastic sheet covering the surface of the press-bonded chip, and the sheet holding means positioned on the outer periphery of the substrate stage and holding the elastic sheet And a pressure reducing means for depressurizing the sealing space formed by the sheet holding means, the elastic sheet, and the substrate stage, and a bonding head that provides a predetermined pressing force to the chip on the substrate through the elastic sheet. A method of crimping is provided.

Description

압착 장치 및 압착 방법 {CRIMPING DEVICE AND CRIMPING METHOD}Crimping device and crimping method {CRIMPING DEVICE AND CRIMPING METHOD}

기판에 접착제를 통해 가압착된 복수의 칩을 기판에 일괄 압착하는 압착 장치 및 압착 방법에 관한 것이다.The present invention relates to a crimping apparatus and a crimping method for collectively crimping a plurality of chips pressed through an adhesive to a substrate.

최근, LSI 칩의 고집적화·고밀도화의 요구에 대해, 웨이퍼 레벨로 CSP(Chip Size Package)를 제조하는 방법이 행해지고 있다. 웨이퍼 레벨 CSP에서는, 회로가 형성된 실리콘 웨이퍼에 대해 플립 칩을 압착한 후, 다이싱하여 CSP를 제조하고 있다. 웨이퍼와 플립 칩은, 열경화성 수지나 이방 도전성 접착제 등의 접착제를 사용하여 미리 가압착(가접속)되어 있다. 가압착 후, 웨이퍼 상의 복수의 플립 칩은, 소정 시간의 가압과 소정 온도에서 가열 및 냉각이 행해져 압착이 완료된다.In recent years, in response to the demand for high integration and high density of LSI chips, a method of manufacturing a chip size package (CSP) at a wafer level has been performed. In the wafer level CSP, a flip chip is pressed against a silicon wafer on which a circuit is formed, and then diced to produce a CSP. The wafer and the flip chip are pre-bonded (provisional connection) using an adhesive such as a thermosetting resin or an anisotropic conductive adhesive. After press bonding, the plurality of flip chips on the wafer are pressurized for a predetermined time and heated and cooled at a predetermined temperature to complete the pressing.

예를 들어, 특허문헌 1에서는, 웨이퍼 레벨로 CSP를 제조하는 압착 장치로서, 원통 형상의 실린더와, 그 일측을 밀폐하도록 설치된 베이스와, 실린더의 타측의 덮개와, 실린더의 내부를 이동하는 금속제의 피스톤으로 구성되어 있는 압착 장치를 개시하고 있다. 이 압착 장치에서는, 피스톤이 이동함으로써, 실린더 내의 밀폐 공간의 용적이 축소된다. 베이스에는 인터포저가 절연성 접착 필름에 의해 실리콘 웨이퍼에 가접속되어 설치되고, 시트 부재가 가접속된 실리콘 웨이퍼를 덮고 있다. 또한, 베이스에는 가열 히터가 매립되어 있다. 그리고, 실린더 내에 가압된 압축 가스를 도입하여, 가접속된 실리콘 웨이퍼를 시트 부재를 통해 전면적으로 가압하고, 가열 히터를 통전하여, 절연성 접착 필름을 용융시켜 실리콘 웨이퍼의 각 전극과 인터포저의 각 전극을 전기적으로 접속하여 CSP 접속체를 제조하고 있다.For example, in Patent Document 1, as a crimping apparatus for manufacturing a CSP at a wafer level, a cylindrical cylinder, a base provided to seal one side thereof, a lid on the other side of the cylinder, and a metal made to move the inside of the cylinder A crimping device composed of a piston is disclosed. In this crimping device, the volume of the closed space in the cylinder is reduced by the movement of the piston. An interposer is temporarily connected to and installed on the silicon wafer by an insulating adhesive film, and the sheet member covers the silicon wafer to which the sheet member is temporarily connected. In addition, a heating heater is embedded in the base. Then, the pressurized compressed gas is introduced into the cylinder, and the temporarily connected silicon wafer is pressed through the sheet member, the heating heater is energized to melt the insulating adhesive film, and each electrode of the silicon wafer and each electrode of the interposer. Is electrically connected to manufacture a CSP connecting body.

일본 특허 공개 제2000-195903호 공보Japanese Patent Publication No. 2000-195903

이러한 장치에서는, 가압된 압축 가스를 이용하여 비접촉 상태에서 가접속체에 압력을 가하므로, 실리콘 웨이퍼 및 인터포저에 대해 큰 압력을 균일하게 가할 수 있다. 한편, 시트 부재로 덮인 가접속된 실리콘 웨이퍼에는, 도 11에 도시하는 바와 같이 상면 및 측면으로부터 압력 F가 가해지고 있다. 그로 인해, 접착제(4)가 가열되어 연화되어 가는 과정에서 상면과 측면에 작용하는 힘의 밸런스를 잃어, 실리콘 웨이퍼(2)의 각 전극과 칩(3)(예를 들어, 인터포저)의 각 전극의 사이에서 실장 어긋남이 발생할 우려가 있다.In such a device, since a pressure is applied to the temporary connection body in a non-contact state by using a pressurized compressed gas, a large pressure can be uniformly applied to the silicon wafer and the interposer. On the other hand, the pressure F is applied from the upper surface and the side surface to the temporarily connected silicon wafer covered with the sheet member as shown in FIG. Therefore, the balance of the forces acting on the upper surface and the side surface in the process of heating and softening the adhesive 4, the angle of each electrode and chip 3 (for example, interposer) of the silicon wafer 2 Mounting misalignment may occur between the electrodes.

따라서, 기판에 접착제를 통해 가압착된 복수의 칩을 실장 어긋남을 발생시키는 일 없이 기판에 일괄 압착하는 것이 가능한 압착 장치 및 압착 방법을 제공하는 것을 과제로 한다.Accordingly, an object of the present invention is to provide a crimping apparatus and a crimping method capable of collectively crimping a plurality of chips pressed through an adhesive to the substrate without causing mounting misalignment.

상기 과제를 해결하기 위해, 청구항 1에 기재된 발명은,In order to solve the above problems, the invention described in claim 1,

기판 상에 복수의 칩을 위치 정렬한 후, 수지를 통해 가압착한 칩을, 일괄 압착하는 압착 장치이며,It is a crimping device for batch-pressing a chip pressed through a resin after positioning a plurality of chips on a substrate,

칩이 압착되는 기판의 이면을 흡착 보유 지지하는 기판 스테이지와,A substrate stage for adsorbing and holding the back surface of the substrate on which the chip is pressed;

상기 가압착한 칩의 표면을 덮는 탄성 시트와,An elastic sheet covering the surface of the pressed chip;

상기 기판 스테이지의 외주에 위치하고, 상기 탄성 시트를 보유 지지하는 시트 보유 지지 수단과,A sheet holding means positioned on an outer circumference of the substrate stage and holding the elastic sheet;

상기 시트 보유 지지 수단과 상기 탄성 시트와 상기 기판 스테이지에 의해 형성된 밀폐 공간을 감압하는 감압 수단과,Pressure reducing means for depressurizing the sealing space formed by the sheet holding means, the elastic sheet, and the substrate stage;

탄성 시트를 통해 기판 상의 칩에 소정의 가압력을 부여하는 본딩 헤드를 구비하고 있는 압착 장치이다.It is a crimping apparatus having a bonding head that applies a predetermined pressing force to a chip on a substrate through an elastic sheet.

청구항 2에 기재된 발명은, 청구항 1에 기재된 발명에 있어서,The invention according to claim 2 is the invention according to claim 1,

상기 탄성 시트를 낱장으로 공급하는 시트 공급 수단을 구비한 압착 장치이다.It is a crimping device provided with a sheet supply means for supplying the elastic sheet as a single sheet.

청구항 3에 기재된 발명은, 청구항 1 또는 2에 기재된 발명에 있어서,The invention according to claim 3 is the invention according to claim 1 or 2,

상기 시트 보유 지지 수단과 상기 탄성 시트와 상기 기판 스테이지에 의해 형성된 밀폐 공간에 불활성 가스를 공급하는 가스 공급 수단을 구비한 압착 장치이다.It is a crimping device provided with the sheet holding means and a gas supply means for supplying an inert gas to the closed space formed by the elastic sheet and the substrate stage.

청구항 4에 기재된 발명은, 청구항 1 내지 3 중 어느 한 항에 기재된 발명에 있어서,The invention according to claim 4 is the invention according to any one of claims 1 to 3,

상기 본딩 헤드와 상기 기판 스테이지에 가열 및 냉각 수단을 구비한 압착 장치이다.It is a crimping apparatus having heating and cooling means on the bonding head and the substrate stage.

청구항 5에 기재된 발명은, 청구항 1 내지 4 중 어느 한 항에 기재된 발명에 있어서,The invention according to claim 5 is the invention according to any one of claims 1 to 4,

상기 본딩 헤드의 가압면이 상기 기판 스테이지에 대해 평행한 상태를 유지하면서 하강시키는 기능을 갖는 것을 특징으로 하는 압착 장치이다.It is a pressing device characterized in that it has a function of lowering while maintaining a state in which the pressing surface of the bonding head is parallel to the substrate stage.

청구항 6에 기재된 발명은,The invention described in claim 6,

기판 상에 복수의 칩을 위치 정렬한 후, 수지를 통해 가압착한 칩을, 일괄 압착하는 압착 방법이며,A method of crimping a plurality of chips on a substrate and then crimping the chips pressed through a resin.

칩이 압착되는 기판의 이면을 흡착 보유 지지하는 기판 스테이지와,A substrate stage for adsorbing and holding the back surface of the substrate on which the chip is pressed,

상기 가압착한 칩의 표면을 덮는 탄성 시트와,An elastic sheet covering the surface of the pressed chip;

상기 기판 스테이지의 외주에 위치하고, 상기 탄성 시트를 보유 지지하는 시트 보유 지지 수단과,A sheet holding means positioned on an outer circumference of the substrate stage and holding the elastic sheet;

상기 시트 보유 지지 수단과 상기 탄성 시트와 상기 기판 스테이지에 의해 형성된 밀폐 공간을 감압하는 감압 수단과,Pressure reducing means for depressurizing the sealing space formed by the sheet holding means, the elastic sheet, and the substrate stage;

탄성 시트를 통해 기판 상의 칩에 소정의 가압력을 부여하는 본딩 헤드를 구비하고,It has a bonding head for applying a predetermined pressing force to the chip on the substrate through the elastic sheet,

칩이 가압착된 기판을 기판 스테이지에 설치하는 공정과,A process of installing the substrate on which the chip is pressurized to the substrate stage,

탄성 시트를 가압착한 칩의 표면에 덮고, 탄성 시트를 보유 지지하는 공정과,A step of covering the surface of the pressed sheet with the elastic sheet and holding the elastic sheet;

상기 시트 보유 지지 수단과 상기 탄성 시트와 상기 기판 스테이지에 의해 형성된 밀폐 공간을 감압하로 하는 공정과,A step of reducing the pressure of the closed space formed by the sheet holding means, the elastic sheet, and the substrate stage under reduced pressure;

본딩 헤드를 소정의 높이까지 하강시키고, 탄성 시트를 통해 기판 상의 칩에 소정의 가압력을 소정 시간 부여하는 공정을 갖는 압착 방법이다.It is a crimping method having a step of lowering the bonding head to a predetermined height and applying a predetermined pressing force to the chip on the substrate through the elastic sheet for a predetermined time.

청구항 7에 기재된 발명은, 청구항 6에 기재된 발명에 있어서,The invention according to claim 7 is the invention according to claim 6,

탄성 시트를 낱장으로 공급하고, 일괄 압착의 동작마다 탄성 시트를 교환하는 공정을 갖는 압착 방법이다.It is a crimping method having a step of supplying an elastic sheet as a single sheet and exchanging the elastic sheet for each operation of batch compression.

청구항 8에 기재된 발명은, 청구항 6 또는 7에 기재된 발명에 있어서,The invention according to claim 8 is the invention according to claim 6 or 7,

상기 탄성 시트에, 내열 온도 350℃ 이상, 열수축률이 350℃에서 0.1% 이하 및 열전도율이 1W/m·K 이상이라고 하는 특성을 구비한 재료를 사용하는 것을 특징으로 하는 압착 방법이다.It is a compression method characterized in that a material having properties such as a heat resistance temperature of 350 ° C or higher, a heat shrinkage rate of 0.1% or lower and a thermal conductivity of 1 W / m · K or higher is used for the elastic sheet.

청구항 9에 기재된 발명은, 청구항 6 내지 8 중 어느 한 항에 기재된 발명에 있어서,The invention according to claim 9 is the invention according to any one of claims 6 to 8,

탄성 시트를 통해 기판 상의 칩에 소정의 가압력을 소정 시간 부여하는 공정에 있어서, 본딩 헤드와 기판 스테이지에 구비된 가열 및 냉각 수단을 동작시키는 공정을 포함하는 압착 방법이다.In the step of applying a predetermined pressing force to the chip on the substrate through the elastic sheet for a predetermined time, it is a pressing method including a step of operating heating and cooling means provided on the bonding head and the substrate stage.

청구항 10에 기재된 발명은, 청구항 6 내지 9 중 어느 한 항에 기재된 발명에 있어서,The invention according to claim 10 is the invention according to any one of claims 6 to 9,

상기 시트 보유 지지 수단과 상기 탄성 시트와 상기 기판 스테이지에 의해 형성된 밀폐 공간을 불활성 가스 분위기로 하는 공정을 포함하는 압착 방법이다.It is a crimping method comprising the step of making the sheet holding means, the elastic sheet, and the closed space formed by the substrate stage into an inert gas atmosphere.

청구항 11에 기재된 발명은, 청구항 6 내지 10 중 어느 한 항에 기재된 발명에 있어서, 상기 본딩 헤드의 가압면이 상기 기판 스테이지에 대해 평행한 상태를 유지하면서 하강시키는 것을 특징으로 하는 압착 방법이다.The invention described in claim 11 is a crimp method according to any one of claims 6 to 10, wherein the pressing surface of the bonding head is lowered while maintaining a state parallel to the substrate stage.

본 발명의 압착 장치 및 압착 방법에 따르면, 본딩 헤드가 탄성 시트를 통해 소정의 가압력으로 칩을 압박하고 있으므로, 접착제가 용융될 때 칩과 기판이 위치 어긋남 되는 일 없이 압착되게 된다. 또한, 국소적으로 밀폐 공간을 형성하여, 감압하로 치환할 수 있으므로, 대규모의 챔버 구조를 필요로 하는 일 없이, 간이적인 구조로 범프의 산화를 방지하면서 일괄 압착할 수 있다.According to the crimping apparatus and crimping method of the present invention, since the bonding head presses the chip with a predetermined pressing force through the elastic sheet, the chip and the substrate are crimped without being displaced when the adhesive melts. In addition, since a closed space can be formed locally and replaced under reduced pressure, it is possible to perform bulk compression while preventing oxidation of the bump with a simple structure without requiring a large-scale chamber structure.

또한 접착제가 가열 경화될 때 발생하는 아웃 가스에 의한 보이드도 감압하에서 본딩함으로써, 보이드를 억제하면서 일괄 압착할 수 있다.In addition, voids caused by outgas generated when the adhesive is cured by heating are also bonded under reduced pressure, whereby the voids can be suppressed and compressed together.

또한, 탄성 시트를 통해 압착하고 있으므로, 가압착된 칩에 높이 편차가 있어도, 실장 어긋남을 발생시키는 일 없이 기판에 일괄 압착할 수 있다.Moreover, since it is crimped through the elastic sheet, even if there is a height variation in the press-bonded chip, it can be crimped onto the substrate without causing mounting misalignment.

또한, 탄성 시트를 국소적으로 형성한 챔버의 상부 덮개와 겸용함으로써 접착제에 의해 가압착된 칩을 일괄 압착할 때, 칩의 주변으로부터 밀려나온 접착제가 본딩 헤드측에 부착되는 것을 방지할 수 있다. 또한, 본딩 헤드와 기판 스테이지로부터의 상하 가열, 냉각에 의해 접착제의 경화와 범프 접합을 일괄적으로 행할 수 있다. 또한, 탄성 시트를 낱장으로 공급함으로써, 고속으로 웨이퍼의 교환을 용이하게 하여 연속적으로 압착을 행할 수 있다.In addition, it is possible to prevent the adhesive sticking out from the periphery of the chip from adhering to the bonding head side when the chip pressed by the adhesive is pressed together by combining the upper cover of the chamber where the elastic sheet is locally formed. In addition, curing and bump bonding of the adhesive can be performed collectively by vertical heating and cooling from the bonding head and the substrate stage. In addition, by supplying the elastic sheet as a single sheet, it is possible to easily exchange wafers at a high speed, and crimping can be performed continuously.

도 1은 본 발명의 실시 형태의 압착 장치의 개략 측면도이다.
도 2는 본 발명의 실시 형태의 문형 프레임의 수직 기둥부의 배치를 설명하는 상면도이다.
도 3은 시트를 인출하여 칩 상면에 배치한 상태를 도시하는 측면도이다.
도 4는 시트를 절단하여 흡착 보유 지지한 상태를 도시하는 측면도이다.
도 5는 본딩 헤드가 하강한 상태를 도시하는 측면도이다.
도 6은 시트로 둘러싸인 공간을 감압한 상태를 도시하는 측면도이다.
도 7은 압착 장치의 동작 흐름도이다.
도 8은 기판 스테이지 상에 웨이퍼 대신에 로드셀을 배치한 상태의 상면도이다.
도 9는 문형 프레임의 수직 기둥부의 높이를 모니터링하는 장치의 교정을 설명하는 도면이다.
도 10은 문형 프레임의 수직 기둥부의 높이를 모니터링하는 장치의 교정을 설명하는 도면이다.
도 11은 종래의 압착 장치의 문제점을 설명하는 개략 측면도이다.
1 is a schematic side view of a crimping apparatus according to an embodiment of the present invention.
It is a top view explaining the arrangement | positioning of the vertical pillar part of the door-shaped frame of embodiment of this invention.
3 is a side view showing a state in which the sheet is taken out and placed on the upper surface of the chip.
4 is a side view showing a state where a sheet is cut and held by adsorption.
5 is a side view showing a state in which the bonding head is lowered.
6 is a side view showing a state in which a space surrounded by a sheet is depressurized.
7 is an operation flowchart of the crimping device.
8 is a top view of a state in which a load cell is disposed instead of a wafer on a substrate stage.
9 is a view for explaining the calibration of the device for monitoring the height of the vertical pillar portion of the door frame.
10 is a view for explaining the calibration of the device for monitoring the height of the vertical pillar portion of the door frame.
11 is a schematic side view for explaining a problem of a conventional crimping apparatus.

본 발명의 실시 형태에 대해 도면을 참조하여 설명한다. 도 1은 본 발명의 실시 형태의 압착 장치의 측면도이다. 도 1에 있어서, 압착 장치(1)를 향해 좌우 방향을 X축, 전후 방향을 Y축, X축과 Y축으로 구성되는 XY 평면에 직교하는 축을 Z축(상하 방향), Z축 주위를 θ축으로 한다.Embodiments of the present invention will be described with reference to the drawings. 1 is a side view of a crimping apparatus according to an embodiment of the present invention. In Fig. 1, the axis perpendicular to the XY plane consisting of the X-axis, the front-rear direction as the Y-axis, the X-axis and the Y-axis as the left-right direction toward the crimping device 1 is the Z-axis (up-down direction), and the Z-axis is θ Axis.

압착 장치(1)는, 칩(3)이 접착제(4)를 통해 가압착된 웨이퍼(2)를 본압착하는 가압 수단(20)과, 웨이퍼(2)를 보유 지지하는 기판 스테이지(40)와, 본압착시에 칩(3)을 덮는 시트(5)를 공급하는 시트 공급 수단(50)과, 시트(5)를 기판 스테이지(4)의 외주에서 보유 지지하는 시트 보유 지지 수단(60)과, 웨이퍼(2) 상에 불활성 가스를 공급하는 가스 공급 수단(70)으로 구성되어 있다. 본 실시 형태에서 설명하는 웨이퍼(2)에는, 미리 칩(3)이 웨이퍼(2) 상의 소정 위치에 위치 정렬되고, 접착제를 사용하여 접합되어 있는 것으로 한다[이후, 칩(3)이 웨이퍼(2)에 가압착되어 있다고 표기함].The crimping device 1 includes a pressing means 20 for main-pressing the wafer 2 on which the chip 3 is pressed through the adhesive 4, and a substrate stage 40 for holding the wafer 2. , Sheet feeding means (50) for supplying the sheet (5) covering the chip (3) during main compression, and sheet holding means (60) for holding the sheet (5) at the outer periphery of the substrate stage (4). , It is composed of a gas supply means 70 for supplying an inert gas on the wafer (2). It is assumed that the wafer 3 described in the present embodiment is pre-aligned with a chip 3 at a predetermined position on the wafer 2, and is bonded using an adhesive (hereinafter, the chip 3 is a wafer 2). ).

가압 수단(20)은, 문형 프레임(21)과, 문형 프레임(21)의 수평 빔부(21a)에 설치된 본딩 헤드 지지부(22)와, 원통형의 본딩 헤드(23)로 구성되어 있다. 문형 프레임(21)의 수직 기둥부(21b)는, 강성이 높은 가이드 구조로 되어 있고, 강성 가이드(21c)로 지지되어 있다. 수직 기둥부(21b)는 상하로 신축 가능하게 되어 있고, 도시하지 않은 상하 구동 수단과 연결되어 있다. 상하 구동 수단에 의한 수직 기둥부(21b)의 승강 동작에 의해, 본딩 헤드(23)가 Z 방향(상하 방향)으로 이동 가능하게 되어 있다. 강성 가이드(21c)는 베이스(6)에 기립 설치되어 있다.The pressing means 20 is composed of a door-shaped frame 21, a bonding head support 22 provided on the horizontal beam portion 21a of the door-shaped frame 21, and a cylindrical bonding head 23. The vertical pillar portion 21b of the door-shaped frame 21 has a rigid guide structure, and is supported by a rigid guide 21c. The vertical pillar portion 21b can be stretched up and down, and is connected to up and down driving means (not shown). The bonding head 23 is movable in the Z direction (up and down direction) by the vertical movement of the vertical column portion 21b by the up and down driving means. The rigid guide 21c is provided standing on the base 6.

또한, 본 실시 형태에 있어서, 문형 프레임(21)은 4개의 수직 기둥부(21b)와, 각각의 수직 기둥부(21b)를 지지하는 4개의 강성 가이드(21c)를 구비하고 있다. 그 배치를 상면으로부터 본 XY 평면으로 나타낸 것이 도 2이며, 4개의 수직 기둥부[21b(21b1, 21b2, 21b3, 21b4)]와, 각각을 지지하는 4개의 강성 가이드[21c(21c1, 21c2, 21c3, 21c4)]가 배치되어 있다. 이 4개의 수직 기둥부(21b)의 높이 조정을 행함으로써, 문형 프레임(21)의 수평 빔부(21a)의, 기판 스테이지(40)에 대한 평행도가 확보된다.In addition, in this embodiment, the door-shaped frame 21 is provided with four vertical pillar parts 21b and four rigid guides 21c supporting each vertical pillar parts 21b. Fig. 2 shows the arrangement in an XY plane viewed from the top, and includes four vertical pillar sections 21b (21b1, 21b2, 21b3, 21b4) and four rigid guides 21c (21c1, 21c2, 21c3) , 21c4)]. By adjusting the height of the four vertical pillar portions 21b, the parallelism of the horizontal beam portion 21a of the door-shaped frame 21 to the substrate stage 40 is secured.

본딩 헤드(23)는, 칩(3)이 실장된 웨이퍼(2)의 칩측으로부터 가열하는 히터(43) 및 가열된 본딩 헤드(23)를 냉각하는 냉각부(45)를 구비하고 있다.The bonding head 23 is provided with a heater 43 for heating from the chip side of the wafer 2 on which the chip 3 is mounted, and a cooling unit 45 for cooling the heated bonding head 23.

기판 스테이지(40)는, 웨이퍼(2)의 이면(2b)을 흡착 보유 지지하는 흡인 구멍(41)과, 웨이퍼(2)를 가열하는 히터(42)와, 가열된 기판 스테이지(40)를 냉각하는 냉각부(44)를 구비하고 있다. 흡인 구멍(41)은 도시하고 있지 않은 흡인 파이프를 통해 흡인 펌프와 접속되어 있다.The substrate stage 40 cools the suction hole 41 for adsorbing and holding the back surface 2b of the wafer 2, the heater 42 for heating the wafer 2, and the heated substrate stage 40 A cooling section 44 is provided. The suction hole 41 is connected to a suction pump via a suction pipe (not shown).

웨이퍼(2)의 고정 수단은, 기계적으로 기판 스테이지(40)에 클램프하는 방식이나 정전 척 방식 등 강고하게 고정되는 것이면, 흡인 구멍(41)을 사용한 흡착 방식이 아니어도 된다.The fixing means for the wafer 2 may not be an adsorption method using a suction hole 41 as long as it is mechanically clamped to the substrate stage 40 or is strongly fixed, such as an electrostatic chuck method.

기판 스테이지(40)의 외주에는 시트 보유 지지 수단(60)이 설치되어 있다. 시트 보유 지지 수단(60)은 내벽(61)과 외벽(62)을 기판 스테이지(40)의 외주를 따라 기립 설치하고, 내벽(61)과 외벽(62) 사이에 끼인 공간인 흡인 스페이스(63)에서 시트 보유 지지 수단(60)의 상부에 설치된 시트(5)를 흡인하는 구성으로 되어 있다. 내벽(61)과 외벽(62)은 기판 스테이지(40)에 칩(3)의 가압착된 웨이퍼(2)가 설치된 높이보다 높은 위치까지 신장되어 있다.A sheet holding means 60 is provided on the outer circumference of the substrate stage 40. The sheet holding means 60 stands up and installs the inner wall 61 and the outer wall 62 along the outer circumference of the substrate stage 40, and is a suction space 63 which is a space sandwiched between the inner wall 61 and the outer wall 62. In this configuration, the sheet 5 provided on the upper portion of the sheet holding means 60 is sucked. The inner wall 61 and the outer wall 62 are extended to a position higher than the height at which the pressed wafer 2 of the chip 3 is installed on the substrate stage 40.

시트 보유 지지 수단(60)은, 기계적으로 내벽(61)에 강고하게 클램프하는 방법이면, 흡인 스페이스(63)를 사용한 흡착 방식이 아니어도 된다. 예를 들어, 본딩 헤드(23)와 내벽(61) 사이에 끼워 넣어 클램프하는 방식이면, 본딩 헤드(23)의 하강과 동시에 클램프할 수 있으므로 기구가 간략화된다.The sheet holding means 60 may not be an adsorption method using the suction space 63 as long as it is a method of mechanically clamping the inner wall 61 firmly. For example, if the clamping is performed by sandwiching between the bonding head 23 and the inner wall 61, the mechanism can be simplified because the bonding head 23 can be clamped simultaneously with the lowering.

내벽(61)과 기판 스테이지(40) 사이에는 감압 수단(80)이 설치되어 있다. 감압 수단(80)은 감압구(81)가 설치되고, 진공 펌프에 의해 시트 보유 지지 수단(60)과 탄성 시트(5)와 기판 스테이지(40)에 의해 형성된 밀폐 공간을 진공 흡인함으로써 감압할 수 있도록 되어 있다.A pressure reducing means 80 is provided between the inner wall 61 and the substrate stage 40. The pressure reducing means 80 is provided with a pressure reducing port 81 and can be reduced in pressure by vacuum suctioning a closed space formed by the sheet holding means 60 and the elastic sheet 5 and the substrate stage 40 by a vacuum pump. It is supposed to.

또한 내벽(61)과 기판 스테이지(40) 사이에는 가스 공급 수단(70)이 설치되어 있다. 가스 공급 수단(70)은 공급구(71)가 설치되고, 공급구(71)로부터 불활성 가스인 질소(N2)가 공급되도록 되어 있다. 도면 중, 시트 보유 지지 수단(60)과 가스 공급 수단(70), 감압 수단(80)은 사선으로 나타냈다.Further, a gas supply means 70 is provided between the inner wall 61 and the substrate stage 40. The gas supply means 70 is provided with a supply port 71 and is supplied with nitrogen (N2) as an inert gas from the supply port 71. In the figure, the sheet holding means 60, the gas supply means 70, and the pressure reducing means 80 are indicated by diagonal lines.

시트 공급 수단(50)은, 롤 형상의 시트(5)를 공급하는 시트 권출부(51)와, 시트 권출부(51)로부터 권출된 시트(5)를 파지하는 시트 파지부(53)와, 시트(5)를 인출하는 시트 인출부(52)와, 인출된 시트(5)를 절단하는 시트 절단부(54)로 구성되어 있다. 시트 권출부(51)는 문형 프레임(21)의 측부에 배치되어 있다. 시트 인출부(52)는 문형 프레임(21)의 내부를, 시트(5)를 파지하면서 X 방향(수평 방향)으로 이동하고, 칩(3)이 가압착 완료된 웨이퍼(2)의 상부에 시트(5)를 덮도록 되어 있다. 시트 절단부(54)는 시트 파지부(53)와 시트 인출부(52) 사이에 위치하고, 인출된 시트(5)를 시트 파지부(53)와 시트 인출부(52)로 파지한 상태에서 절단하도록 되어 있다. 시트 인출부(52)와 시트 파지부(53)는, 시트(5)를 파지한 상태에서, Z 방향(상하 방향)으로 이동 가능하게 구성되어 있다.The sheet supply means 50 includes a sheet unwinding portion 51 for supplying a roll-shaped sheet 5, and a sheet gripping portion 53 for gripping the sheet 5 unloaded from the sheet unwinding portion 51, It consists of a sheet take-out part 52 for drawing out the sheet 5 and a sheet cut-out part 54 for cutting the drawn sheet 5. The sheet unwinding portion 51 is disposed on the side of the door-shaped frame 21. The sheet take-out part 52 moves the inside of the door-shaped frame 21 in the X direction (horizontal direction) while gripping the sheet 5, and the sheet 3 is placed on the top of the wafer 2 on which the chip 3 is press-bonded. 5) It is supposed to cover. The sheet cutting portion 54 is positioned between the sheet gripping portion 53 and the sheet drawing portion 52, so that the drawn sheet 5 is cut with the sheet gripping portion 53 and the sheet drawing portion 52 being gripped. It is. The sheet lead-out portion 52 and the sheet gripping portion 53 are configured to be movable in the Z direction (up and down direction) in a state where the sheet 5 is held.

또한, 시트(5)의 재질로서 불소계 수지가 일반적이지만, 본 실시 형태와 같은 일괄 압착 용도에 있어서, 불소계 수지의 내열 온도, 열수축률, 열전도율은 충분한 특성이라고는 할 수 없다. 즉, 일괄 압착 용도에서는 히터(43)의 온도가 최고 350℃에 달하는 경우가 있으므로 내열성이 부족하여, 열수축에 의해 주름이 발생하여 실장 어긋남으로 될 가능성이 있고, 열전도율이 낮기 때문에 칩을 소정 온도로 가열하기 위한 히터(43)의 설정 온도가 높아진다고 하는 문제가 있다. 이로 인해, 시트(5)에 요구되는 특성으로서, 내열 온도가 350℃ 이상(불소계 수지는 260℃ 정도), 열수축률이 350℃에서 0.1% 이하(불소계 수지는 260℃에서 2% 전후), 열전도율이 1W/m·K 이상(불소계 수지는 0.3W/m·K)을 구비하고 있는 것이 바람직하다.Further, although the fluorine-based resin is generally used as the material of the sheet 5, in the batch compression application as in the present embodiment, the heat-resistant temperature, heat shrinkage, and thermal conductivity of the fluorine-based resin cannot be said to be sufficient properties. That is, in the case of the batch crimping application, since the temperature of the heater 43 may reach up to 350 ° C, the heat resistance is insufficient, there is a possibility that wrinkles are generated due to heat shrinkage, resulting in misalignment, and since the thermal conductivity is low, the chip is brought to a predetermined temperature. There is a problem that the set temperature of the heater 43 for heating becomes high. For this reason, as a characteristic required for the sheet 5, the heat resistance temperature is 350 ° C or more (fluorine-based resin is about 260 ° C), the heat shrinkage rate is 0.1% or less at 350 ° C (fluorine-based resin is around 2% at 260 ° C), and thermal conductivity. It is preferable to have 1 W / m · K or more (the fluorine-based resin is 0.3 W / m · K).

이러한 압착 장치(1)를 이용하여 칩(3)을 웨이퍼(2)에 본압착하는 압착 방법에 대해, 도 3∼도 6의 압착 장치(1)의 측면도와, 도 7의 흐름도를 이용하여 설명한다.The crimping method for the main crimping of the chip 3 to the wafer 2 using the crimping device 1 will be described using a side view of the crimping device 1 in FIGS. 3 to 6 and a flowchart in FIG. 7. do.

우선, 본딩 헤드(23)가 상승한 상태에서, 칩(3)이 가압착된 웨이퍼(2)를 기판 스테이지(40)에 설치한 상태로부터 설명을 개시한다(스텝 SP01).First, the description starts from the state in which the wafer 2 to which the chip 3 has been pressed is mounted on the substrate stage 40 while the bonding head 23 is raised (step SP01).

다음으로, 도 3에 나타내는 바와 같이, 시트 권출부(51)로부터 시트(5)를 인출한다. 시트(5)의 인출에는, 시트 인출부(52)가 사용된다. 시트 인출부(52)는 시트(5)를 파지하고, 시트 보유 지지 수단(60)을 넘도록 X 방향(수평 방향)으로 이동한다. 시트 인출부(52)가 X 방향으로 이동함으로써, 칩(3)이 가압착되어 있는 웨이퍼(2)의 상면측이, 시트(5)로 덮이게 된다. 또한, 시트(5)는 본딩 헤드(23)와 웨이퍼(2) 사이를 통과하도록 인출된다. 시트 파지부(53)와, 시트 인출부(52)가 시트를 파지한 상태에서, 하강하여 칩(3)의 상면에 시트(5)를 세트한다(스텝 SP02).Next, as shown in FIG. 3, the sheet 5 is taken out from the sheet unwinding portion 51. For taking out the sheet 5, a sheet taking-out portion 52 is used. The sheet take-out 52 holds the sheet 5 and moves in the X direction (horizontal direction) so as to exceed the sheet holding means 60. When the sheet take-out portion 52 moves in the X direction, the top surface side of the wafer 2 on which the chip 3 is pressed is covered with the sheet 5. Further, the sheet 5 is drawn out to pass between the bonding head 23 and the wafer 2. The sheet holding portion 53 and the sheet drawing portion 52 hold the sheet, and then descend to set the sheet 5 on the upper surface of the chip 3 (step SP02).

다음으로, 시트 절단부(54)가 시트(5)를 절단하고, 시트 인출부(52)는 원래 있었던 위치(대기 위치)로 복귀한다(도 4). 시트 보유 지지 수단(60)의 흡인 스페이스(63)에 접속되어 있는 도시하고 있지 않은 흡인 펌프가 작동하여, 시트(5)를 흡인한다(스텝 SP03). 이와 같이, 시트(5)를 낱장으로 공급함으로써, 고속으로 웨이퍼의 교환을 용이하게 하여 연속적으로 압착을 행할 수 있다.Next, the sheet cutting portion 54 cuts the sheet 5, and the sheet taking-out portion 52 returns to the original position (standby position) (Fig. 4). The suction pump (not shown) connected to the suction space 63 of the sheet holding means 60 operates to suck the sheet 5 (step SP03). As described above, by supplying the sheets 5 in a single sheet, it is possible to easily exchange wafers at a high speed and continuously press the wafer.

다음으로, 본딩 헤드(23) 및 기판 스테이지(40)에 설치되어 있는 히터(42, 43)를 승온하지 않은 상태에서, 도 5에 도시하는 바와 같이, 본딩 헤드(23)가 하강하여 시트(5)를 통해 칩(2)을 웨이퍼(3)에 가압한다. 본딩 헤드(23)의 하강시에는, 도시하고 있지 않은 승강 수단에 의해, 도 2에 도시하는 4개의 수직 기둥부[21b(21b1, 21b2, 21b3, 21b4)]의 높이가 항상 균일해지도록 모니터링하면서 행하여, 본딩 헤드(23)의 가압면에 경사가 발생하지 않도록 제어한다. 구체적으로는, 4개의 수직 기둥부(21b)의 최대값과 최소값이 소정의 편차 이내(예를 들어, 웨이퍼 사이즈가 300㎜인 경우는 3㎛)로 되도록 제어를 행하고, 본딩 헤드(23)의 가압면이 칩(2)에 접촉한 후에는 웨이퍼(2) 상에 탑재된 모든 칩(3)에 소정의 하중이 가해지도록 가압한다(스텝 SP04). 이와 같이 평행 상태를 유지하면서 가압을 행함으로써, 이후의 스텝에서 가열하여 가압을 행할 때, 접착제가 연화될 때에도 수평 분력이 발생하지 않아, 수평 분력에 기인한 실장 어긋남을 방지할 수 있다.Next, in a state in which the heaters 42 and 43 provided on the bonding head 23 and the substrate stage 40 are not heated, as shown in FIG. 5, the bonding head 23 descends and the seat 5 ) To press the chip 2 onto the wafer 3. When the bonding head 23 is lowered, the height of the four vertical pillar portions 21b (21b1, 21b2, 21b3, 21b4) shown in FIG. 2 is constantly monitored by an elevating means (not shown). It is controlled so that the inclination does not occur on the pressing surface of the bonding head 23. Specifically, control is performed so that the maximum and minimum values of the four vertical pillar portions 21b are within a predetermined deviation (for example, 3 µm when the wafer size is 300 mm), and the bonding head 23 is After the pressing surface contacts the chip 2, it is pressed so that a predetermined load is applied to all the chips 3 mounted on the wafer 2 (step SP04). By applying pressure while maintaining the parallel state in this way, when heating and pressing in a subsequent step, horizontal force is not generated even when the adhesive is softened, and mounting displacement due to horizontal force can be prevented.

다음으로, 도 6과 같이, 시트(5)와 기판 스테이지(40)와 시트 보유 지지 수단(60)의 내벽(61)으로 둘러싸인 공간의 공기를 감압 수단(80)에 의해 흡인함으로써 진공 상태로 한다(스텝 SP05).Next, as shown in Fig. 6, the air in the space surrounded by the inner wall 61 of the sheet 5, the substrate stage 40, and the sheet holding means 60 is sucked by the pressure reducing means 80 to obtain a vacuum. (Step SP05).

다음으로, 본딩 헤드(23) 및 기판 스테이지(40)에 설치되어 있는 히터(42, 43)가 승온되어 접착제(4)의 가열 경화가 개시된다(스텝 SP06). 이때의 칩(3)의 범프와 웨이퍼(2)의 회로면에 형성된 전극의 접속도 동시에 행해진다. 이와 같이, 본딩 헤드(23)가 시트(5)를 통해 소정의 가압력으로 칩(2)을 가압하고 있으므로, 접착제가 용융될 때 칩(2)과 기판(3)이 위치 어긋남 되는 일 없이 압착되게 된다. 또한 감압하에서 행하므로, 접착제가 가열 경화될 때 발생하는 아웃 가스에 의한 보이드가 억제되어 품질이 좋은 접합 상태로 된다.Next, the heaters 42 and 43 provided on the bonding head 23 and the substrate stage 40 are heated, and heat curing of the adhesive 4 is started (step SP06). At this time, the bumps of the chip 3 and the electrodes formed on the circuit surface of the wafer 2 are also connected at the same time. As described above, since the bonding head 23 presses the chip 2 with a predetermined pressing force through the sheet 5, the chip 2 and the substrate 3 are compressed without dislocation when the adhesive melts. do. Moreover, since it is performed under reduced pressure, voids caused by outgas generated when the adhesive is cured by heating are suppressed, and a good bonding state is achieved.

범프나 전극이 산화되기 쉬운 재질(예를 들어, 구리 등)인 경우에는, 진공 흡인 후에 가스 공급 수단(70)의 공급구(71)로부터 불활성 가스를 공급하여 시트(5)와 기판 스테이지(40)와 시트 보유 지지 수단(60)의 내벽(61)으로 둘러싸인 공간을 불활성 가스로 치환한다. 칩(2)이 가압착된 웨이퍼(2)의 주변 전체가 불활성 가스 분위기로 되어, 칩(2)의 전극의 산화가 방지된다(스텝 SP07).When the bump or the electrode is a material that is easily oxidized (for example, copper, etc.), the sheet 5 and the substrate stage 40 are supplied by supplying an inert gas from the supply port 71 of the gas supply means 70 after vacuum suction. ) And the space surrounded by the inner wall 61 of the sheet holding means 60 is replaced with an inert gas. The entire periphery of the wafer 2 on which the chip 2 is pressurized becomes an inert gas atmosphere, and oxidation of the electrode of the chip 2 is prevented (step SP07).

이와 같이, 본딩 헤드(23)가 시트(5)를 통해 소정의 가압력으로 칩(2)을 가압하고 있으므로, 접착제가 용융될 때에 칩(2)과 기판(3)이 위치 어긋남 되는 일 없이 압착되게 된다.As described above, since the bonding head 23 presses the chip 2 with a predetermined pressing force through the sheet 5, the chip 2 and the substrate 3 are compressed without dislocation when the adhesive melts. do.

가압력 및 가열 온도는 압착되는 칩수나, 범프수 및 접착제의 경화 반응이나 범프의 용융 온도에 따라서, 각각 임의의 타이밍에 다단계로 제어할 수 있도록 되어 있다.The pressing force and the heating temperature can be controlled in multiple stages at arbitrary timings depending on the number of chips to be compressed, the number of bumps and the curing reaction of the adhesive or the melting temperature of the bumps.

다음으로, 소정 시간의 가압과 가열이 행해진 후, 본딩 헤드(23)가 상승하고 본압착이 완료된다(스텝 SP08).Next, after pressurization and heating for a predetermined time, the bonding head 23 is raised and the main compression is completed (step SP08).

또한, 이상의 스텝 SP01∼SP08과는 별도로, 문형 프레임(21)은 4개의 수직 기둥부[21b(21b1, 21b2, 21b3, 21b4)]의 높이 모니터링을 행할 때의 오차를 저감시키기 위해, 소정의 주기로 높이 모니터링 기능의 교정을 행할 필요가 있다. 구체예로서는, 도 8에 도시하는 바와 같이 웨이퍼 대신에 동일 사양의 4개의 로드셀(91, 92, 93, 94)을 배치한 기판 스테이지(40)에, 도 9, 도 10에 도시하는 바와 같이 본딩 헤드(23)를 접근시켜, 양면이 평행 상태로 가장 접근한 단계에서 제로점 설정을 행하는 방법이 있다. 즉, 양면이 로드셀을 사이에 두고 평행 상태로 밀착되었는지 여부를, 4개의 로드셀 각각이 검지하는 가압력의 최대값과 최소값이 소정의 편차 이내에서 평형 상태에 있는지 여부로 판단한다.In addition, apart from the above steps SP01 to SP08, the door-shaped frame 21 is set at a predetermined cycle to reduce errors when performing height monitoring of the four vertical pillar portions 21b (21b1, 21b2, 21b3, 21b4). It is necessary to calibrate the height monitoring function. As a specific example, as shown in Fig. 8, a bonding head as shown in Figs. 9 and 10 is placed on a substrate stage 40 in which four load cells 91, 92, 93, and 94 of the same specification are disposed instead of a wafer. By approaching (23), there is a method of setting the zero point in the step where the two sides are closest in parallel. That is, it is determined whether the two sides are in close contact with the load cells in parallel, and whether the maximum and minimum values of the pressing force detected by each of the four load cells are in equilibrium within a predetermined deviation.

또한, 본 실시 형태에 있어서는, 로드셀을 높이 모니터링 기능의 교정을 행할 때, 기판 스테이지(40) 상에 배치하였지만, 기판 스테이지(40)와 히터(42) 사이에 상설해 두어도 된다. 또한, 문형 프레임(21)의 수직 기둥부(21b) 및 각각의 수직 기둥부(21b)를 지지하는 강성 가이드(21c)가 4개인 경우로 하였지만, 4개에 한정되는 것은 아니며, 3개 혹은 5개 이상이어도 된다.In addition, in the present embodiment, the load cell is disposed on the substrate stage 40 when the height monitoring function is calibrated, but may be permanently placed between the substrate stage 40 and the heater 42. In addition, although the vertical pillar portion 21b of the door-shaped frame 21 and the rigid guide 21c supporting each vertical pillar portion 21b are four, it is not limited to four, but is not limited to three or five. More than one dog.

1 : 실장 장치
2 : 웨이퍼
3 : 칩
4 : 접착제
5 : 시트
6 : 베이스
20 : 가압 수단
21 : 문형 프레임
21a : 문형 프레임(21)의 수평 빔부
21b : 문형 프레임(21)의 수직 기둥부
21c : 강성 가이드
22 : 본딩 헤드 지지부
23 : 본딩 헤드
40 : 기판 스테이지
41 : 흡인 구멍
42 : 히터
43 : 히터
44 : 냉각부
45 : 냉각부
50 : 시트 공급 수단
51 : 시트 권출부
52 : 시트 인출부
53 : 시트 파지부
54 : 시트 절단부
60 : 시트 보유 지지 수단
61 : 내벽
62 : 외벽
63 : 흡인 스페이스
70 : 가스 공급 수단
71 : 공급구
80 : 감압 수단
81 : 감압구
91 : 로드셀
92 : 로드셀
93 : 로드셀
94 : 로드셀
1: mounting device
2: Wafer
3: Chip
4: Adhesive
5: sheet
6: Base
20: pressing means
21: door frame
21a: Horizontal beam part of door-shaped frame 21
21b: vertical pillar portion of the door frame 21
21c: Rigidity guide
22: bonding head support
23: bonding head
40: substrate stage
41: suction hole
42: heater
43: heater
44: cooling unit
45: cooling unit
50: sheet supply means
51: sheet unwinding portion
52: sheet drawer
53: sheet gripping part
54: sheet cutting unit
60: seat holding means
61: inner wall
62: outer wall
63: suction space
70: gas supply means
71: Supply port
80: decompression means
81: pressure reducing port
91: load cell
92: load cell
93: load cell
94: load cell

Claims (11)

기판 상에 복수의 칩을 위치 정렬한 후, 수지를 통해 가압착한 칩을, 일괄 압착하는 압착 장치이며,
칩이 압착되는 기판의 이면을 흡착 보유 지지하는 기판 스테이지와,
상기 가압착한 칩의 표면을 덮는 탄성 시트와,
상기 기판 스테이지의 외주에 위치하고, 상기 탄성 시트를 보유 지지하는 시트 보유 지지 수단과,
상기 시트 보유 지지 수단과 상기 탄성 시트와 상기 기판 스테이지에 의해 형성된 밀폐 공간을 감압하는 감압 수단과,
탄성 시트를 통해 기판 상의 칩에 소정의 가압력을 부여하는 본딩 헤드를 구비하고 있는, 압착 장치.
It is a crimping device for batch-pressing a chip pressed through a resin after aligning a plurality of chips on a substrate,
A substrate stage for adsorbing and holding the back surface of the substrate on which the chip is pressed;
An elastic sheet covering the surface of the pressed chip;
A sheet holding means positioned on an outer circumference of the substrate stage and holding the elastic sheet;
Pressure reducing means for depressurizing the sealing space formed by the sheet holding means, the elastic sheet, and the substrate stage;
And a bonding head that applies a predetermined pressing force to the chip on the substrate through the elastic sheet.
제1항에 있어서,
상기 탄성 시트를 낱장으로 공급하는 시트 공급 수단을 구비한, 압착 장치.
According to claim 1,
And a sheet supplying means for supplying the elastic sheet as a single sheet.
제1항 또는 제2항에 있어서,
상기 시트 보유 지지 수단과 상기 탄성 시트와 상기 기판 스테이지에 의해 형성된 밀폐 공간에 불활성 가스를 공급하는 가스 공급 수단을 구비한, 압착 장치.
The method according to claim 1 or 2,
And a gas supply means for supplying an inert gas to the sheet holding means and the enclosed space formed by the elastic sheet and the substrate stage.
제1항 또는 제2항에 있어서,
상기 본딩 헤드와 상기 기판 스테이지에 가열 및 냉각 수단을 구비한, 압착 장치.
The method according to claim 1 or 2,
A crimping apparatus having heating and cooling means in the bonding head and the substrate stage.
제1항 또는 제2항에 있어서,
상기 본딩 헤드의 가압면이 상기 기판 스테이지에 대해 평행한 상태를 유지하면서 하강시키는 기능을 갖는 것을 특징으로 하는, 압착 장치.
The method according to claim 1 or 2,
The pressing device of the bonding head, characterized in that it has a function of lowering while maintaining a state parallel to the substrate stage, the pressing device.
기판 상에 복수의 칩을 위치 정렬한 후, 수지를 통해 가압착한 칩을, 일괄 압착하는 압착 방법이며,
칩이 압착되는 기판의 이면을 흡착 보유 지지하는 기판 스테이지와,
상기 가압착한 칩의 표면을 덮는 탄성 시트와,
상기 기판 스테이지의 외주에 위치하고, 상기 탄성 시트를 보유 지지하는 시트 보유 지지 수단과,
상기 시트 보유 지지 수단과 상기 탄성 시트와 상기 기판 스테이지에 의해 형성된 밀폐 공간을 감압하는 감압 수단과,
탄성 시트를 통해 기판 상의 칩에 소정의 가압력을 부여하는 본딩 헤드를 구비하고,
칩이 가압착된 기판을 기판 스테이지에 설치하는 공정과,
탄성 시트를 가압착한 칩의 표면에 덮고, 탄성 시트를 보유 지지하는 공정과,
상기 시트 보유 지지 수단과 상기 탄성 시트와 상기 기판 스테이지에 의해 형성된 밀폐 공간을 감압하로 하는 공정과,
본딩 헤드를 소정의 높이까지 하강시키고, 탄성 시트를 통해 기판 상의 칩에 소정의 가압력을 소정 시간 부여하는 공정을 갖는, 압착 방법.
It is a crimping method of batch-pressing a chip pressed through a resin after positioning a plurality of chips on a substrate,
A substrate stage for adsorbing and holding the back surface of the substrate on which the chip is pressed;
An elastic sheet covering the surface of the pressed chip;
A sheet holding means positioned on an outer circumference of the substrate stage and holding the elastic sheet;
Pressure reducing means for depressurizing the sealing space formed by the sheet holding means, the elastic sheet, and the substrate stage;
It has a bonding head for applying a predetermined pressing force to the chip on the substrate through the elastic sheet,
A process of installing the substrate on which the chip is pressurized to the substrate stage,
A step of covering the surface of the chip with the elastic sheet pressed and holding the elastic sheet;
A step of reducing the sealing space formed by the sheet holding means, the elastic sheet, and the substrate stage under reduced pressure;
The bonding method has a process of lowering the bonding head to a predetermined height and applying a predetermined pressing force to the chip on the substrate through the elastic sheet for a predetermined time.
제6항에 있어서,
탄성 시트를 낱장으로 공급하고, 일괄 압착의 동작마다 탄성 시트를 교환하는 공정을 갖는, 압착 방법.
The method of claim 6,
A method of crimping, wherein the elastic sheet is supplied as a single sheet, and the elastic sheet is exchanged for each operation of batch compression.
제6항 또는 제7항에 있어서,
상기 탄성 시트에, 내열 온도 350℃ 이상, 열수축률이 350℃에서 0.1% 이하 및 열전도율이 1W/m·K 이상이라고 하는 특성을 구비한 재료를 사용하는 것을 특징으로 하는, 압착 방법.
The method of claim 6 or 7,
The elastic sheet is characterized in that a material having heat resistance temperature of 350 ° C or higher, thermal shrinkage of 0.1% or lower at 350 ° C, and thermal conductivity of 1 W / m · K or higher is used.
제6항 또는 제7항에 있어서,
탄성 시트를 통해 기판 상의 칩에 소정의 가압력을 소정 시간 부여하는 공정에 있어서, 본딩 헤드와 기판 스테이지에 구비된 가열 및 냉각 수단을 동작시키는 공정을 포함하는, 압착 방법.
The method of claim 6 or 7,
A step of applying a predetermined pressing force to a chip on a substrate through an elastic sheet for a predetermined period of time, comprising a step of operating heating and cooling means provided on the bonding head and the substrate stage.
제6항 또는 제7항에 있어서,
상기 시트 보유 지지 수단과 상기 탄성 시트와 상기 기판 스테이지에 의해 형성된 밀폐 공간을 불활성 가스 분위기로 하는 공정을 포함하는, 압착 방법.
The method of claim 6 or 7,
And a step of making the sheet holding means, the elastic sheet, and the closed space formed by the substrate stage an inert gas atmosphere.
제6항 또는 제7항에 있어서,
상기 본딩 헤드의 가압면이 상기 기판 스테이지에 대해 평행한 상태를 유지하면서 하강시키는 것을 특징으로 하는, 압착 방법.
The method of claim 6 or 7,
A pressing method, characterized in that the pressing surface of the bonding head is lowered while maintaining a state parallel to the substrate stage.
KR1020157002389A 2012-06-29 2013-06-27 Crimping device and crimping method Active KR102117726B1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2012146895 2012-06-29
JPJP-P-2012-146895 2012-06-29
PCT/JP2013/067624 WO2014003107A1 (en) 2012-06-29 2013-06-27 Crimping device and crimping method

Publications (2)

Publication Number Publication Date
KR20150036254A KR20150036254A (en) 2015-04-07
KR102117726B1 true KR102117726B1 (en) 2020-06-01

Family

ID=49783244

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020157002389A Active KR102117726B1 (en) 2012-06-29 2013-06-27 Crimping device and crimping method

Country Status (3)

Country Link
JP (1) JP6029245B2 (en)
KR (1) KR102117726B1 (en)
WO (1) WO2014003107A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12057425B2 (en) 2021-05-17 2024-08-06 Samsung Electronics Co., Ltd. Semiconductor package

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014114093B4 (en) 2014-09-29 2017-03-23 Danfoss Silicon Power Gmbh Method for low-temperature pressure sintering
DE102014114097B4 (en) 2014-09-29 2017-06-01 Danfoss Silicon Power Gmbh Sintering tool and method for sintering an electronic assembly
DE102014114095B4 (en) 2014-09-29 2017-03-23 Danfoss Silicon Power Gmbh sintering apparatus
DE102014114096A1 (en) 2014-09-29 2016-03-31 Danfoss Silicon Power Gmbh Sintering tool for the lower punch of a sintering device
JP6411316B2 (en) * 2015-12-08 2018-10-24 株式会社新川 Electronic component mounting equipment
TWI671827B (en) * 2017-03-30 2019-09-11 日商新川股份有限公司 Bonding device and joining method
JP7182036B2 (en) * 2018-06-28 2022-12-02 パナソニックIpマネジメント株式会社 Component crimping device, sheet installation unit and installation method of sheet installation unit
US20230274951A1 (en) * 2020-08-05 2023-08-31 Shinkawa Ltd. Mounting device and mounting method
KR102233338B1 (en) * 2020-10-12 2021-03-29 주식회사 저스템 Apparatus for preventing oxidization of flip chip bonding
TWI791287B (en) * 2021-09-16 2023-02-01 日商新川股份有限公司 Packaging device and packaging method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001053092A (en) * 1999-08-13 2001-02-23 Japan Radio Co Ltd Package, device and manufacturing method thereof
JP2004296746A (en) * 2003-03-26 2004-10-21 Nikkiso Co Ltd Pressurizing device and circuit element mounting method
JP2012004603A (en) * 2004-09-15 2012-01-05 Seiko Epson Corp Mounting structure for semiconductor device, method for mounting semiconductor device and substrate

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3381781B2 (en) 1998-12-25 2003-03-04 ソニーケミカル株式会社 Method of manufacturing electronic component connection body and manufacturing apparatus therefor
JP3896017B2 (en) * 2001-08-03 2007-03-22 松下電器産業株式会社 Semiconductor mounting body manufacturing method and semiconductor mounting body manufacturing apparatus
JP4872291B2 (en) * 2005-09-27 2012-02-08 住友電気工業株式会社 Electrode connection method, electrode connection device, and method for manufacturing wiring board assembly
JP4925669B2 (en) * 2006-01-13 2012-05-09 ソニーケミカル&インフォメーションデバイス株式会社 Crimping apparatus and mounting method
JP5349189B2 (en) * 2009-07-28 2013-11-20 新光電気工業株式会社 Electronic component device manufacturing method and jig

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001053092A (en) * 1999-08-13 2001-02-23 Japan Radio Co Ltd Package, device and manufacturing method thereof
JP2004296746A (en) * 2003-03-26 2004-10-21 Nikkiso Co Ltd Pressurizing device and circuit element mounting method
JP2012004603A (en) * 2004-09-15 2012-01-05 Seiko Epson Corp Mounting structure for semiconductor device, method for mounting semiconductor device and substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12057425B2 (en) 2021-05-17 2024-08-06 Samsung Electronics Co., Ltd. Semiconductor package

Also Published As

Publication number Publication date
JP6029245B2 (en) 2016-11-24
KR20150036254A (en) 2015-04-07
JPWO2014003107A1 (en) 2016-06-02
WO2014003107A1 (en) 2014-01-03

Similar Documents

Publication Publication Date Title
KR102117726B1 (en) Crimping device and crimping method
CN100461358C (en) Component mounting method and component mounting device
JP4206320B2 (en) Manufacturing method of semiconductor integrated circuit device
KR102497661B1 (en) Mounting device and mounting method
JP5602439B2 (en) Heating device and manufacturing method of mounting body
KR102037948B1 (en) Die bonding method and apparatus
KR20160086277A (en) Bonding apparatus, bonding system, bonding method, and computer storage medium
KR20220048018A (en) Bonding apparatus, bonding system and bonding method
KR102372519B1 (en) mounting device
JP3896017B2 (en) Semiconductor mounting body manufacturing method and semiconductor mounting body manufacturing apparatus
JP6415328B2 (en) Joining method, program, computer storage medium, joining apparatus and joining system
TW201332084A (en) Three-dimensional mounting device
JP5892686B2 (en) Crimping apparatus and temperature control method
CN111712906A (en) Anti-warping PTFE sheet for die packaging and die packaging method
JP4796610B2 (en) Manufacturing method of semiconductor integrated circuit device
KR20190095352A (en) Manufacturing apparatus and manufacturing method of semiconductor device
JP4926630B2 (en) Manufacturing method and manufacturing apparatus for solid-state imaging device, and pasting apparatus
JP4619209B2 (en) Semiconductor element mounting method and semiconductor element mounting apparatus
JP5577652B2 (en) Bonding apparatus, bonding method, and manufacturing method of semiconductor device
WO2019230032A1 (en) Electronic component mounting device
JP6863767B2 (en) Mounting device and mounting method
US20230290666A1 (en) Semiconductor manufacturing apparatus, carrier jig, and manufacturing method of semiconductor device
KR102284943B1 (en) Bonding device and bonding method
KR20230030535A (en) Manufacturing method of semiconductor products, workpiece integration devices, film laminate, and semiconductor products
KR20100023574A (en) Method and apparatus for bonding semiconductor chip

Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20150128

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20180626

Comment text: Request for Examination of Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20191029

Patent event code: PE09021S01D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20200519

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20200526

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20200526

End annual number: 3

Start annual number: 1

PG1601 Publication of registration
PR1001 Payment of annual fee

Payment date: 20230522

Start annual number: 4

End annual number: 4