KR102091724B1 - Non-volatile memory device and fabricating method thereof - Google Patents

Abstract

A nonvolatile memory device and a method of manufacturing the same are provided. The nonvolatile memory device includes a pillar-shaped channel region extending in a direction perpendicular to the substrate, a tunneling insulating layer, a charge storage layer, and a blocking insulating layer sequentially formed on the channel region, and an interlayer insulating layer pattern formed on the blocking insulating layer. , A diffusion barrier formed conformally on the interlayer insulating layer pattern, and a gate electrode formed on the diffusion barrier layer.

Description

Non-volatile memory device and manufacturing method thereof

The present invention relates to a nonvolatile memory device and a method of manufacturing the same.

A semiconductor memory device is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Semiconductor memory devices are largely classified into volatile memory devices and nonvolatile memory devices.

The volatile memory device is a memory device in which stored data is lost when power supply is cut off. Volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). A nonvolatile memory device is a memory device that retains stored data even when the power supply is cut off. Nonvolatile memory devices include flash memory devices, read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EPMROM), resistive memory devices (e.g., PRAM (Phase- change RAM (FRAM), Ferroelectric RAM (FRAM), Resistive RAM (RRAM), and the like.

Meanwhile, as electronic products become smaller and smaller, high-volume data processing is required. Accordingly, there is a need to increase the degree of integration of semiconductor memory devices used in such electronic products. In order to improve the degree of integration of a semiconductor memory device, a three-dimensional memory device having a vertical transistor structure by vertically arranging unit memory cells has been proposed.

Korean Patent Publication No. 2011-0012806 discloses a flash memory device having a vertical channel structure.

The problem to be solved by the present invention is to provide a nonvolatile memory device including a diffusion barrier layer to prevent fluorine from penetrating into the blocking insulating layer and melting the blocking insulating layer.

The problem to be solved by the present invention is to provide a method for manufacturing a nonvolatile memory device including a diffusion barrier layer, in order to prevent fluorine from penetrating into the blocking insulating layer and melting the blocking insulating layer.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

One aspect of the nonvolatile memory device of the present invention for solving the above problems is a pillar-shaped channel region extending in a direction perpendicular to the substrate, a tunneling insulating film, a charge storage film sequentially formed on the channel region And a blocking insulating film, an interlayer insulating film pattern formed on the blocking insulating film, a diffusion barrier film conformally formed on the interlayer insulating film pattern, and a gate electrode formed on the diffusion barrier film.

The blocking insulating layer may include a high dielectric constant material.

The diffusion barrier may include nitride.

The nitride may be SiN or SiON.

A high dielectric constant film formed between the diffusion barrier layer and the gate electrode may be further included.

Another aspect of the nonvolatile memory device of the present invention for solving the above problems is a pillar-shaped channel region extending in a direction perpendicular to the substrate, an interlayer insulating layer pattern formed on the channel region, and an interlayer insulating layer pattern. It includes a tunneling insulating film, a charge storage film, a blocking insulating film, and a diffusion preventing film formed sequentially and sequentially, and a gate electrode formed on the diffusion preventing film.

The diffusion barrier may include nitride.

The nitride may be SiN or SiON.

A high dielectric constant film formed between the diffusion barrier layer and the gate electrode may be further included.

One aspect of a method of manufacturing a nonvolatile memory device of the present invention for solving the above problems is to alternately stack a plurality of sacrificial films and a plurality of interlayer insulating films on a substrate to form a mold structure, and to cut a part of the mold structure. Removed to form a channel hole exposing the upper surface of the substrate, in the channel hole, a blocking insulating film, a charge storage film, a tunneling insulating film are sequentially formed, the tunneling insulating film formed on the bottom surface of the channel hole, the charge storage film , Sequentially removing the blocking insulating film to expose the top surface of the substrate, filling the empty spaces of the channel hole with a semiconductor material, removing the plurality of sacrificial films, and conformally forming a diffusion barrier on the plurality of interlayer insulating films And forming a gate electrode on the diffusion barrier.

The method may further include removing the blocking insulating layer exposed between the plurality of interlayer insulating layers, and depositing the same material as the blocking insulating layer between removing the plurality of sacrificial layers and forming the diffusion barrier layer.

The diffusion barrier may include nitride.

The nitride may be SiN or SiON.

Between forming the diffusion barrier film and forming the gate electrode, a high dielectric constant film may be further included.

Another aspect of a method of manufacturing a nonvolatile memory device of the present invention for solving the above problems is to alternately stack a plurality of sacrificial films and a plurality of interlayer insulating films on a substrate to form a mold structure, and to cut a part of the mold structure. Forming a channel hole exposing the upper surface of the substrate by removing, filling a semiconductor material in the channel hole, removing the plurality of sacrificial films, and on the plurality of interlayer insulating films, a tunneling insulating film, a charge storage film, a blocking insulating film, And forming a diffusion barrier layer conformally and sequentially, and forming a gate electrode on the diffusion barrier layer.

The diffusion barrier may include nitride.

The nitride may be SiN or SiON.

Between forming the diffusion barrier film and forming the gate electrode, a high dielectric constant film may be further included.

Other specific matters of the present invention are included in the detailed description and drawings.

1 is a conceptual diagram illustrating a nonvolatile memory device in accordance with some embodiments of the present invention.
FIG. 2 is a perspective view illustrating the memory block of FIG. 1.
3 is a cross-sectional view taken along line I-I 'of FIG. 2.
FIG. 4 is an enlarged view showing a region A of FIG. 3 in detail.
5 is a part of a cross-sectional view for describing a nonvolatile memory device according to another embodiment of the present invention.
6 to 11 are intermediate step views for describing a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.
12 is an intermediate step diagram illustrating a method of manufacturing a nonvolatile memory device according to another embodiment of the present invention.
13 is a block diagram illustrating a memory system in accordance with some embodiments of the present invention.
14 is a block diagram illustrating an application example of the memory system of FIG. 13.
15 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 14.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only the present embodiments allow the disclosure of the present invention to be complete, and the ordinary knowledge in the technical field to which the present invention pertains. It is provided to fully inform the holder of the scope of the invention, and the invention is only defined by the scope of the claims. The same reference numerals refer to the same components throughout the specification.

When one element is referred to as being “connected to” or “coupled to” another, it is directly connected or coupled with the other, or intervening another element Includes all cases. On the other hand, when one device is referred to as being “directly connected to” or “directly coupled to” another device, it indicates that the other device is not interposed therebetween. The same reference numerals refer to the same components throughout the specification. “And / or” includes each and every combination of one or more of the items mentioned.

Although the first, second, etc. are used to describe various elements, components and / or sections, it goes without saying that these elements, components and / or sections are not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Accordingly, it goes without saying that the first element, the first component or the first section mentioned below may be the second element, the second component or the second section within the technical spirit of the present invention.

The terminology used herein is for describing the embodiments and is not intended to limit the present invention. In this specification, the singular form also includes the plural form unless otherwise specified in the phrase. As used herein, "comprises" and / or "comprising" refers to the components, steps, operations and / or elements mentioned above, the presence of one or more other components, steps, operations and / or elements. Or do not exclude additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used as meanings commonly understood by those skilled in the art to which the present invention pertains. In addition, terms defined in the commonly used dictionary are not ideally or excessively interpreted unless specifically defined.

The non-volatile memory device described below and a method of manufacturing the same are related to forming a diffusion barrier between the blocking insulating layer and the gate electrode in order to prevent fluorine from penetrating into the blocking insulating layer and melting the blocking insulating layer. In the process of forming a semiconductor memory device, when a tungsten (W) is deposited after forming a blocking insulating layer, WF6 gas is decomposed to form a tungsten (W) metal, and fluorine (F) byproducts may be generated. These fluorine (F) byproducts diffuse into the cell stack or remain inside the word line membrane. In general, when fluorine (F) is introduced into the dielectric film, the dielectric constant may be lowered, thereby deteriorating the inherent characteristics of the memory cell transistor or deteriorating the reliability of the semiconductor memory device. In addition, when fluorine (F) is combined with hydrogen to form HF, it acts as an SiO2 etchant, so that the oxide film of the memory cell stack can be etched to melt the blocking insulating film.

In the nonvolatile memory device according to the present invention, a diffusion barrier film containing nitride is formed between the blocking insulating film and the gate electrode, so that fluorine (F) can be prevented from penetrating into the blocking insulating film. As a result of SIMS analysis and TEM_EDS analysis, it can be seen that there is an effect of suppressing penetration of fluorine (F) by the diffusion barrier.

1 is a conceptual diagram illustrating a nonvolatile memory device in accordance with some embodiments of the present invention.

Referring to FIG. 1, a memory cell array of a nonvolatile memory device according to some embodiments of the present invention may include a plurality of memory blocks (BLK1 to BLKn, where n is a natural number). Each memory block BLK1 to BLKn may extend in the first to third directions D1, D2, and D3. As illustrated, the first to third directions D1, D2, and D3 may cross directions with each other and may be different directions. For example, the first to third directions D1, D2, and D3 may be directions perpendicular to each other, but are not limited thereto.

A nonvolatile memory device 1 according to an embodiment of the present invention will be described with reference to FIGS. 2 to 4.

FIG. 2 is a perspective view illustrating the memory block of FIG. 1. 3 is a cross-sectional view taken along line I-I 'of FIG. 2. FIG. 4 is an enlarged view detailing region A of FIG. 3.

2 to 4, a memory block (BLKi, where 1 ≤ i ≤ n, i is a natural number) of the nonvolatile memory device 1 according to an embodiment of the present invention includes a substrate 100 and a channel Region 340, tunneling insulating film 310, charge storage film 320, blocking insulating film 330, interlayer insulating film pattern 201, diffusion barrier film 400, gate electrodes 501-509, bit line contact 620 ), Bit lines 631 to 633, and the like.

The substrate 100 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, a group IV semiconductor may include silicon, germanium or silicon-germanium. The substrate 100 may be provided as a bulk wafer or an epitaxial layer.

The channel region 340 has a pillar shape extending in a direction perpendicular to the substrate 100. The channel region 340 may be arranged to have a regular arrangement on the substrate 100. For example, the channel regions 340 may be regularly arranged at regular intervals in a first direction and a second direction perpendicular to the first direction. The channel region 340 may be made of, for example, single crystal silicon. The channel region 340 may be formed by forming an amorphous silicon, and then applying heat to phase change the amorphous silicon to single crystal silicon. Alternatively, the channel region 340 may be formed through an epitaxial growth process using the substrate 100 as a seed. A plurality of cell transistors constituting one cell string may be formed in the channel region 340. Cell transistors may be connected in series in the vertical direction. In general, 2 ^m cells (m is a natural number of 1 or more) cell transistors may be formed in one cell string formed on the substrate 100.

The tunneling insulating layer 310, the charge storage layer 320, and the blocking insulating layer 330 are sequentially formed on the channel region 340. That is, the tunneling insulating layer 310, the charge storage layer 320, and the blocking insulating layer 330 are sequentially on the channel region 340 in a direction D2 perpendicular to the direction D1 in which the channel region 340 extends. It is formed by stacking.

The tunneling insulating layer 310 may be formed of a material having a band gap larger than the charge storage layer 320, and may be formed of a material having a lower dielectric constant than the blocking insulating layer 330. The tunneling insulating layer 310 is, for example, silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSi _x O _y ) , Aluminum oxide (Al ₂ O ₃ ), and zirconium oxide (ZrO ₂ ). The tunneling insulating layer 310 may be formed using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. In addition, the tunneling insulating layer 310 may be further formed by further including a heat treatment process performed after the deposition process. The heat treatment process may be a Rapid Thermal Nitridation (RTN) process or an annealing process performed in an environment including at least one of nitrogen and oxygen. The tunneling insulating layer 310 may tunnel charges to the charge storage layer 320 in the FN method.

The charge storage layer 320 may be disposed between the tunneling insulating layer 310 and the blocking insulating layer 330. The charge storage film 320 may be formed of, for example, a nitride film or a high-k film. The nitride film is, for example, silicon nitride, silicon oxynitride, hafnium oxynitride, zirconium oxynitride, hafnium silicon oxynitride, or hafnium silicon oxynitride. It may include at least one of aluminum oxynitride (hafnium aluminum oxynitride). The high-k film is, for example, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide (zirconium silicon oxide), tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium Yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate. The charge storage layer 320 is a portion where charge passing through the tunneling insulating layer 310 is trapped. That is, the charge storage layer 320 traps charges and stores information.

The blocking insulating layer 330 prevents charges trapped in the charge storage layer 320 from being discharged to the gate electrodes 501 to 509, and charges from the gate electrodes 501 to 509 are captured by the charge storage layer 320. Can be prevented.

The blocking insulating layer 330 is formed of a composite layer formed of silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), silicon oxynitride (SiON), or a high-k material or a combination thereof. Can be. The high-k material is aluminum oxide (Al ₂ O ₃ ), tantalum oxide (Ta ₂ O ₃ ), titanium oxide (TiO ₂ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ) , Zirconium silicon oxide (ZrSi _x O _y ), hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSi _x O _y ), lanthanum oxide (La ₂ O ₃ ), lanthanum aluminum oxide (LaAl _x O _y ), lanthanum hafnium oxide (LaHf _x O _y ), hafnium aluminum oxide (HfAl _x O _y ), and praseodymium oxide (Pr ₂ O ₃ ).

The interlayer insulating layer pattern 201 is formed on the blocking insulating layer 330. That is, since the plurality of interlayer insulating films 200, 210, and 220 (see FIG. 6) are formed spaced apart in the direction D1 in which the channel region 340 is extended, the plurality of sacrificial films 500 and 510 (see FIG. ) Is removed, an interlayer insulating layer pattern 201 may be formed on the blocking insulating layer 330. Accordingly, the plurality of interlayer insulating films 200, 210, and 220 may be formed of a material having an etch selectivity with respect to the plurality of sacrificial films 500 and 510. For example, the plurality of interlayer insulating films 200, 210, and 220 may be made of oxide, and the plurality of sacrificial films 500 and 510 may be made of nitride. The plurality of interlayer insulating films 200, 210, and 220 may be formed using a chemical vapor deposition (CVD) process.

The diffusion barrier film 400 is conformally formed on the interlayer insulating film pattern 201. The diffusion barrier 400 may be formed using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The diffusion barrier film 400 may include nitride, and may be, for example, any one of silicon nitride (SiN), silicon oxynitride (SiON), and high-k dielectric nitride. The high-k nitride film may be, for example, aluminum silicon oxide nitride (AlSiON), aluminum oxide nitride (AlON), HfSiON, HfON, or the like. Alternatively, the diffusion barrier film 400 may be a material having a low etch selectivity with respect to HF gas. The diffusion barrier film 400 serves to prevent the blocking insulating film 330 from being melted by HF gas generated when the gate electrodes 501 to 509 are formed. That is, the diffusion barrier layer 400 is positioned between the blocking insulating layer 330 and the gate electrodes 501 to 509 to prevent HF gas from contacting the blocking insulating layer 330. Specifically, when WF6 is used when forming the gate electrodes 501 to 509, fluorine (F) is generated, which reacts with hydrogen (H ₂ ) to form HF gas.

By the reaction formula 12HF (g) + 2SiO ₂ → 2SiF6 + 4H ₂ O + 2H ₂ , silicon oxide (SiO ₂ ) is dissolved by HF gas, and thus it is necessary to prevent it. Although not illustrated in FIGS. 2 to 4, a high-k film (eg, AlO) may be further formed between the diffusion barrier film 400 and the gate electrodes 501 to 509.

The gate electrodes 501 to 509 are formed on the diffusion barrier film 400. If a high-k film (eg, AlO) is further formed on the diffusion barrier film 400, gate electrodes 501 to 509 may be formed on the high-k film. The gate electrodes 501 to 509 may be made of W, Co, or Ni, or may be made of polysilicon (poly-Si) or polysilicide (poly-Silicide). The gate electrodes 501 to 509 may include a barrier metal (not shown), but may also be a single layer made of a gate metal material. In other words, when the diffusion barrier film 400 is formed, it acts as a barrier to the gate electrodes 501 to 509, so there is no need to separately form a barrier metal (not shown). When the barrier metal (not shown) is omitted, since the limited space of the mold stack can be filled with a gate metal material, the stack height is reduced and the sheet line resistance (Rs) of the word line can be reduced.

5 is a part of a cross-sectional view for describing a nonvolatile memory device according to another embodiment of the present invention. For convenience of description, substantially different points from non-volatile memory devices according to an embodiment of the present invention will be mainly described.

Referring to FIG. 5, the nonvolatile memory device 2 according to another embodiment of the present invention includes a substrate 100, a channel region 340, an interlayer insulating film pattern 201, a tunneling insulating film 310, and a charge storage film. 320, a blocking insulating film 330, a diffusion barrier film 400, gate electrodes 501, 502, and the like.

The substrate 100 may include a semiconductor material, for example, a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI oxide semiconductor. For example, a group IV semiconductor may include silicon, germanium or silicon-germanium. The substrate 100 may be provided as a bulk wafer or an epitaxial layer.

The channel region 340 has a pillar shape extending in a direction perpendicular to the substrate 100. The channel region 340 may be arranged to have a regular arrangement on the substrate 100. For example, the channel regions 340 may be regularly arranged at regular intervals in a first direction and a second direction perpendicular to the first direction. The channel region 340 may be made of, for example, single crystal silicon. The channel region 340 may be formed by forming an amorphous silicon, and then applying heat to phase change the amorphous silicon to single crystal silicon. Alternatively, the channel region 340 may be formed through an epitaxial growth process using the substrate 100 as a seed. A plurality of cell transistors forming one cell string may be formed in the channel region 340. Cell transistors may be connected in series in the vertical direction. In general, 2 ^m cells (m is a natural number of 1 or more) cell transistors may be formed in one cell string formed on the substrate 100.

The interlayer insulating layer pattern 201 is formed on the channel region 340. That is, since the plurality of interlayer insulating films 200, 210, and 220 (see FIG. 6) are formed spaced apart in the direction D1 in which the channel region 340 is extended, the plurality of sacrificial films 500 and 510 (see FIG. ), An interlayer insulating layer pattern 201 may be formed on the channel region 340. Accordingly, the plurality of interlayer insulating films 200, 210, and 220 may be formed of a material having an etch selectivity with respect to the plurality of sacrificial films 500 and 510. For example, the plurality of interlayer insulating films 200, 210, and 220 may be made of oxide, and the plurality of sacrificial films 500 and 510 may be made of nitride. The plurality of interlayer insulating films 200, 210, and 220 may be formed using a chemical vapor deposition (CVD) process.

The tunneling insulating film 310, the charge storage film 320, the blocking insulating film 330, and the diffusion barrier film 400 are formed sequentially on the interlayer insulating film pattern 201. That is, the tunneling insulating film 310 is conformally formed on the interlayer insulating film pattern 201, the charge storage film 320 is conformally formed on the tunneling insulating film 310, and the charge storage film 320 is formed. The blocking insulating layer 330 is conformally formed, and the diffusion barrier layer 400 is conformally formed on the blocking insulating layer 330.

The tunneling insulating layer 310 may be formed of a material having a band gap larger than the charge storage layer 320, and may be formed of a material having a lower dielectric constant than the blocking insulating layer 330. The tunneling insulating layer 310 may be formed using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. In addition, the tunneling insulating layer 310 may be further formed by further including a heat treatment process performed after the deposition process. The heat treatment process may be a Rapid Thermal Nitridation (RTN) process or an annealing process performed in an environment including at least one of nitrogen and oxygen.

The charge storage layer 320 is a portion where charge passing through the tunneling insulating layer 310 is trapped. That is, the charge storage layer 320 traps charges and stores information.

The blocking insulating layer 330 prevents charges trapped in the charge storage layer 320 from being discharged to the gate electrodes 501 and 502, and charges from the gate electrodes 501 and 502 are captured by the charge storage layer 320. Can be prevented.

The diffusion barrier 400 may be formed using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The diffusion barrier 400 may include nitride, and may be, for example, any one of silicon nitride (SiN), silicon oxynitride (SiON), and high-k nitride film. The high-k nitride film may be, for example, aluminum silicon oxide nitride (AlSiON), aluminum oxide nitride (AlON), HfSiON, HfON, or the like. Alternatively, the diffusion barrier film 400 may be a material having a low etch selectivity with respect to HF gas. The diffusion barrier film 400 serves to prevent the blocking insulating film 330 from being melted by HF gas generated when the gate electrodes 501 and 502 are formed. That is, the diffusion barrier film 400 is positioned between the blocking insulating film 330 and the gate electrodes 501 and 502, so that HF gas may be prevented from contacting the blocking insulating film 330. Although not illustrated in FIG. 5, a high-k film (eg, AlO) may be further formed between the diffusion barrier film 400 and the gate electrodes 501 and 502.

The gate electrodes 501 and 502 are formed on the diffusion barrier film 400. If a high-k film (eg, AlO) is further formed on the diffusion barrier film 400, gate electrodes 501 and 502 may be formed on the high-k film. The gate electrodes 501 and 502 may include a barrier metal (not shown), but may also be a single layer made of a gate metal material.

Hereinafter, a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention will be described with reference to FIGS. 6 to 11.

6 to 11 are intermediate step views for describing a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

6 and 7, first, a plurality of sacrificial films 500 and 510 and a plurality of interlayer insulating films 200, 210 and 220 are alternately stacked on the substrate 100 to form a mold structure. Subsequently, a part of the mold structure is removed to form a channel hole 300 and a first hole 301 exposing the upper surface of the substrate 100.

Next, referring to FIG. 8, a blocking insulating layer 330, a charge storage layer 320, and a tunneling insulating layer 310 are sequentially formed in the channel hole 300. The blocking insulating layer 330, the charge storage layer 320, and the tunneling insulating layer 310 may be formed to cover sidewalls and bottom surfaces in the channel hole 300. The blocking insulating layer 330, the charge storage layer 320, and the tunneling insulating layer 310 may be formed using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process.

Subsequently, referring to FIG. 9, the tunneling insulating layer 310, the charge storage layer 320, and the blocking insulating layer 330 formed on the bottom surface of the channel hole 300 are sequentially removed to expose the top surface of the substrate 100. Order. This is to allow the channel region 340 to contact the substrate 100 when the channel region 340 is formed in a subsequent process. Subsequently, the channel region 340 is formed by filling the semiconductor material to fill the empty space of the channel hole 300.

Next, referring to FIG. 10, a plurality of sacrificial films 500 and 510 are removed. The plurality of sacrificial films 500 and 510 may be removed using a space in the first hole 301 using a pullback process. Accordingly, the plurality of sacrificial films 500 and 510 may be a material having an etch selectivity with the plurality of interlayer insulating films 200, 210 and 220. At this time, the plurality of sacrificial films 500 and 510 are removed, and the blocking insulating film 330 exposed between the plurality of interlayer insulating films 200, 210, and 220 is removed, and the same material as the blocking insulating film 330 is used. A deposition process may be performed. Because, when removing the plurality of sacrificial films 500 and 510, since some of the blocking insulating films 330 exposed between the plurality of interlayer insulating films 200, 210, and 220 may also be removed, the blocking insulating films 330 This is to restore the portion where the thickness is thinned.

 Next, referring to FIG. 11, a diffusion barrier film 400 is conformally formed on the interlayer insulating film pattern 201. The diffusion barrier 400 may be formed using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The diffusion barrier 400 may include nitride, and may be, for example, any one of silicon nitride (SiN), silicon oxynitride (SiON), and high-k nitride film. The high-k nitride film may be, for example, aluminum silicon oxide nitride (AlSiON), aluminum oxide nitride (AlON), HfSiON, HfON, or the like. Alternatively, the diffusion barrier film 400 may be a material having a low etch selectivity with respect to HF gas. Although not illustrated in FIG. 11, after the diffusion barrier layer 400 is conformally formed, a high dielectric constant film (not shown) may be further included. Subsequently, gate electrodes 501 and 502 are formed on the diffusion barrier layer 400 by filling the gate metal material.

Hereinafter, a method of manufacturing a nonvolatile memory device according to another embodiment of the present invention will be described with reference to FIGS. 5 to 7 and 12.

12 is an intermediate step diagram illustrating a method of manufacturing a nonvolatile memory device according to another embodiment of the present invention. For convenience of description, description will mainly be made on a point substantially different from a method of manufacturing a nonvolatile memory device according to an embodiment of the present invention.

A method of manufacturing a nonvolatile memory device according to another embodiment of the present invention does not form a blocking insulating layer 330, a charge storage layer 320, or a tunneling insulating layer 310 in the channel hole 300, and the channel hole 300 ) To fill the semiconductor material to form the channel region 340.

That is, a plurality of sacrificial films 500 and 510 and a plurality of interlayer insulating films 200, 210 and 220 are alternately stacked on the substrate 100 to form a mold structure, and a part of the mold structure is removed to remove the substrate ( The channel hole 300 and the first hole 301 exposing the upper surface of the 100) are formed.

Subsequently, a channel region 340 is formed by filling the channel hole 300 with a semiconductor material. Subsequently, the plurality of sacrificial films 500 and 510 are removed, and the tunneling insulating film 310, the charge storage film 320, the blocking insulating film 330, and the diffusion barrier film 400 are conformed on the interlayer insulating film pattern 201. It is formed sequentially. The diffusion barrier 400 may be formed using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. The diffusion barrier 400 may include nitride, and may be, for example, any one of silicon nitride (SiN), silicon oxynitride (SiON), and high-k nitride film. The high-k nitride film may be, for example, aluminum silicon oxide nitride (AlSiON), aluminum oxide nitride (AlON), HfSiON, HfON, or the like. Alternatively, the diffusion barrier film 400 may be a material having a low etch selectivity with respect to HF gas. In addition, after forming the diffusion barrier film 400 conformally, it may further include forming a high-k film (not shown).

Subsequently, gate electrodes 501 and 502 are formed on the diffusion barrier layer 400 by filling the gate metal material.

13 is a block diagram illustrating a memory system in accordance with some embodiments of the present invention.

Referring to FIG. 13, the memory system 1000 includes a nonvolatile memory device 1100 and a controller 1200.

The nonvolatile memory device 1100 may be configured and operate as described with reference to FIGS. 1 to 12.

The controller 1200 is connected to a host and a nonvolatile memory device 1100. In response to the request from the host, the controller 1200 is configured to access the nonvolatile memory device 1100. For example, the controller 1200 is configured to control read, write, erase, and background operations of the nonvolatile memory device 1100. The controller 1200 is configured to provide an interface between the nonvolatile memory device 1100 and a host. The controller 1200 is configured to drive firmware for controlling the nonvolatile memory device 1100.

Illustratively, the controller 1200 further includes well-known components such as random access memory (RAM), a processing unit, a host interface, and a memory interface. RAM is used as at least one of the operating memory of the processing unit, the cache memory between the nonvolatile memory device 1100 and the host, and the buffer memory between the nonvolatile memory device 1100 and the host. do. The processing unit controls the overall operation of the controller 1200.

The host interface includes a protocol for performing data exchange between the host and the controller 1200. For example, the controller 1200 includes a Universal Serial Bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-E (PCI-express) protocol, an Advanced Technology Attachment (ATA) protocol, External (host) through at least one of various interface protocols such as Serial-ATA protocol, Parallel-ATA protocol, SCSI (small computer small interface) protocol, ESDI (enhanced small disk interface) protocol, and IDE (Integrated Drive Electronics) protocol. ). The memory interface interfaces with the nonvolatile memory device 1100. For example, the memory interface includes a NAND interface or a NOR interface.

The memory system 1000 may be configured to additionally include an error correction block. The error correction block is configured to detect and correct errors in data read from the nonvolatile memory device 1100 using an error correction code (ECC). Illustratively, the error correction block is provided as a component of the controller 1200. The error correction block may be provided as a component of the nonvolatile memory device 1100.

The controller 1200 and the nonvolatile memory device 1100 may be integrated into one semiconductor device. For example, the controller 1200 and the nonvolatile memory device 1100 may be integrated into a single semiconductor device to configure a memory card. For example, the controller 1200 and the nonvolatile memory device 1100 are integrated into a single semiconductor device, such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), a smart media card (SM, SMC), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), and universal flash memory (UFS).

The controller 1200 and the nonvolatile memory device 1100 may be integrated as one semiconductor device to form a solid state drive (SSD). The semiconductor drive (SSD) includes a storage device configured to store data in a semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of the host connected to the memory system 1000 is significantly improved.

As another example, the memory system 1000 includes a computer, an Ultra Mobile PC (UMPC), a workstation, a net-book, a PDA (Personal Digital Assistants), a portable computer, a web tablet, and a wireless Wireless phone, mobile phone, smart phone, e-book, portable multimedia player (PMP), portable game machine, navigation device, black box ), Digital camera, 3-dimensional television, digital audio recorder, digital audio player, digital picture recorder, digital video player ( digital picture player), digital video recorder, digital video player, devices that can transmit and receive information in a wireless environment, one of a variety of electronic devices that make up a home network, compose a computer network Ha Is provided as one of various components of an electronic device, such as one of various electronic devices, one of various electronic devices constituting a telematics network, an RFID device, or one of various components constituting a computing system.

For example, the nonvolatile memory device 1100 or the memory system 1000 may be mounted in various types of packages. For example, the nonvolatile memory device 1100 or the memory system 1000 may include Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer It can be packaged and mounted in the same way as -Level Processed Stack Package (WSP).

14 is a block diagram illustrating an application example of the memory system of FIG. 13.

Referring to FIG. 14, the memory system 2000 includes a nonvolatile memory device 2100 and a controller 2200. The nonvolatile memory device 2100 includes a plurality of nonvolatile memory chips. The plurality of nonvolatile memory chips are divided into a plurality of groups. Each group of the plurality of nonvolatile memory chips is configured to communicate with the controller 2200 through one common channel. For example, the plurality of nonvolatile memory chips are illustrated as communicating with the controller 2200 through the first to k-th channels CH1 to CHk.

Each nonvolatile memory chip is configured similarly to the nonvolatile memory device described with reference to FIGS. 1 to 12.

In FIG. 14, it has been described that a plurality of nonvolatile memory chips are connected to one channel. However, it will be understood that the memory system 2000 can be modified such that one nonvolatile memory chip is connected to one channel.

15 is a block diagram illustrating a computing system including the memory system described with reference to FIG. 14.

Referring to FIG. 15, the computing system 3000 includes a central processing unit 3100, a RAM 3200, a random access memory (RAM), a user interface 3300, a power supply 3400, and a memory system 2000. .

The memory system 2000 is electrically connected to the central processing unit 3100, the RAM 3200, the user interface 3300, and the power source 3400 through the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

In FIG. 15, the nonvolatile memory device 2100 is illustrated as being connected to the system bus 3500 through the controller 2200. However, the non-volatile memory device 2100 may be configured to be directly connected to the system bus 3500.

15, it is shown that the memory system 2000 described with reference to FIG. 14 is provided. However, the memory system 2000 may be replaced with the memory system 1000 described with reference to FIG. 13.

For example, the computing system 3000 may be configured to include all of the memory systems 1000 and 2000 described with reference to FIGS. 13 and 14.

Although the embodiments of the present invention have been described with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing its technical spirit or essential features. You will understand. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: substrate 200, 210, 220: a plurality of interlayer insulating film
201: interlayer insulating film pattern 300: channel hole
310: tunneling insulating film 320: charge storage film
330: blocking insulating film 340: channel region
400: diffusion barrier 500, 510: multiple sacrificial films
501 ~ 509: gate electrode

Claims (10)

delete delete delete delete delete delete A mold structure is formed by alternately laminating a plurality of sacrificial films and a plurality of interlayer insulating films on a substrate,
A part of the mold structure is removed to form a channel hole exposing the upper surface of the substrate,
In the channel hole, a blocking insulating film, a charge storage film, and a tunneling insulating film are sequentially formed,
The tunneling insulating layer, the charge storage layer, and the blocking insulating layer formed on the bottom surface of the channel hole are sequentially removed to expose the top surface of the substrate,
Fill the empty space of the channel hole with a semiconductor material,
Remove the plurality of sacrificial film,
A diffusion barrier is conformally formed on the plurality of interlayer insulating films,
And forming a gate electrode on the diffusion barrier layer,
Non-volatile memory device further comprising removing the blocking insulating layer exposed between the plurality of interlayer insulating layers, and depositing the same material as the blocking insulating layer between removing the plurality of sacrificial layers and forming the diffusion barrier layer. Method of manufacture. delete The method of claim 7,
The diffusion barrier layer is a method of manufacturing a nonvolatile memory device including nitride. A mold structure is formed by alternately laminating a plurality of sacrificial films and a plurality of interlayer insulating films on a substrate,
A part of the mold structure is removed to form a channel hole exposing the upper surface of the substrate,
Filling a semiconductor material in the channel hole,
Removing the plurality of sacrificial films,
On the plurality of interlayer insulating films, a tunneling insulating film, a charge storage film, a blocking insulating film, and a diffusion barrier film are conformally formed sequentially,
And forming a gate electrode on the diffusion barrier layer,
Non-volatile memory device further comprising removing the blocking insulating layer exposed between the plurality of interlayer insulating layers, and depositing the same material as the blocking insulating layer between removing the plurality of sacrificial layers and forming the diffusion barrier layer. Method of manufacture.

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