KR102089048B1 - Semiconductor device and method of fabricating the same - Google Patents

Abstract

A first semiconductor layer comprising a first region including a first element and a second region including a second element, the first semiconductor layer including the first element, and the first semiconductor layer provided in the first semiconductor layer A device isolation pattern for electrically separating the device and the second device, a drain provided on the bottom surface of the first area of the first semiconductor layer, and a surface provided on the bottom surface of the second area of the first semiconductor layer A semiconductor device comprising two semiconductor layers is provided.

Description

Semi-conductor device and method of fabricating the same}

The present invention relates to a semiconductor device, and more particularly, to a smart power integrated circuit (Smart Power IC) BCD (Bipolar-CMOS-DMOS) device and a method of manufacturing the same.

Semiconductor devices included in various electronic devices, including household appliances, are a major component for determining the quality of electronic devices. 2. Description of the Related Art With the trend toward high-capacity, multi-functionality, and / or miniaturization of electronic devices, there is an increasing demand for semiconductor devices with improved reliability and other characteristics. In order to meet these demands, various techniques for improving the characteristics of semiconductor devices have been introduced.

Recently, a smart power integrated circuit (Smart Power IC) in which various power device functions are integrated on one chip has emerged as a new high-speed growth field. Smart power integrated circuit (Smart Power IC) is mainly used to implement a high-frequency, high-breakdown-voltage information and communication system such as an automotive power integrated circuit (Automotive power IC) and DC / DC converter (converter). Conventional BCD (Bipolar-CMOS-DMOS) type power integrated circuits generally use a VDMOS device, which has a problem of high on-resistance and low driving capability.

One technical object of the present invention is to provide a semiconductor device including a power control element, a signal control element, and a current control element.

Another technical problem to be solved by the present invention is to provide a highly reliable semiconductor device.

A semiconductor device according to the present invention for achieving the above object includes a first semiconductor layer including a first region including a first element and a second region including a second element; A device isolation pattern provided in the first semiconductor layer and electrically separating the first device and the second device; A drain provided on a lower surface of the first region of the first semiconductor layer; And a second semiconductor layer provided on a lower surface of the second region of the first semiconductor layer.

According to an embodiment, a sidewall insulating pattern between the drain and the second semiconductor layer may be further included.

According to an embodiment, an ohmic contact layer between the first semiconductor layer and the drain may be further included.

According to one embodiment, the drain may extend over the lower surface of the second semiconductor layer.

According to an embodiment, the device isolation pattern may extend through the first semiconductor layer and into the second semiconductor layer.

According to an embodiment, the first semiconductor layer may have an n-type conductivity type, and the second semiconductor layer may have a p-type conductivity type.

According to one embodiment, the first semiconductor layer includes a first epi layer in contact with the first semiconductor layer and a second epi layer on the first epi layer, and the first epi layer is greater than the second epi layer. The impurity concentration may be high.

According to an embodiment, the first device may be a DMOS transistor.

According to an embodiment, the first device includes a source and a buried gate electrode, and the source and the buried gate electrode may be connected to metal wires provided on the first semiconductor layer.

According to an embodiment, the second element may be a CMOS element.

According to an embodiment, the first semiconductor layer further includes a third region including a third element, and the third element may be a bipolar transistor.

A method of manufacturing a semiconductor device according to the present invention for achieving the above object is to sequentially form the first and second epi layers on a substrate including a first region, a second region and a third region; Removing a portion of the first region of the substrate to expose the first epi layer; And forming a drain on the bottom surface of the exposed first epi layer.

According to one embodiment, forming the drain may include performing a plating process or a screen printing process.

According to an embodiment, further comprising forming device isolation patterns on the substrate, wherein forming the device isolation patterns penetrates the first and second epilayers on the substrate and extends into the substrate. Forming fields; Forming trench insulating patterns covering sidewalls of the trenches; And forming trench gap fill patterns filling the trenches in which the insulating patterns are formed, and the trench gap pip patterns may include a polycrystalline silicon film.

According to one embodiment, the method may further include thinning the substrate before removing a portion of the first region, and thinning the substrate may include performing a grinding process.

According to one embodiment, before forming the drain, further comprising forming a sidewall insulating pattern on the sidewall of the substrate where a portion of the first region is removed, wherein forming the sidewall insulating pattern is the first region Forming a protective oxide layer covering the sidewalls on the lower surface of the substrate from which a portion of the substrate is removed; And performing a front anisotropic etching process on a lower surface of the substrate on which the protective layer is formed.

According to one embodiment, before forming the drain further comprises forming an ohmic contact layer on the bottom surface of the exposed first epi layer, wherein forming the ohmic contact layer performs a metal deposition process or a plating process. It may include.

According to one embodiment, forming a DMOS device on the first region; Forming a CMOS element on the second region; And forming a bipolar device on the third region.

The semiconductor device according to the present invention provides a smart power integrated circuit (Smart Power IC) having a TDMOS (Trench Double diffused Metal-Oxide-Semiconductor) power device instead of the existing Vertical Double Diffused Metal-Oxide-Semiconductor (VDMOS). As a result, a device for a large current having a small size and excellent current driving capability can be realized.

The semiconductor device according to the present invention can provide a structure in which a current is applied in the vertical direction by forming the drain of the first device on the first region below the first epi layer. Accordingly, a high-efficiency semiconductor device having high current driving characteristics and low on-resistance can be provided.

1 to 22 are diagrams for describing a semiconductor device and a method of manufacturing the same according to embodiments of the present invention.

The above objects, other objects, features and advantages of the present invention will be readily understood through the following preferred embodiments related to the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to ensure that the disclosed contents are thorough and complete and that the spirit of the present invention is sufficiently conveyed to those skilled in the art.

 In the specification, when it is stated that a film is on another film or substrate, it means that it may be formed directly on another film or substrate, or a third film may be interposed between them. In addition, in the drawings, the thickness of the films and regions are exaggerated for effective description of the technical content. Further, in various embodiments of the present specification, terms such as first, second, and third are used to describe various regions, films, and the like, but these regions and films should not be limited by these terms. . These terms are only used to distinguish one region or membrane from another region or membrane. Therefore, the film quality referred to as the first film quality in one embodiment may be referred to as the second film quality in another embodiment. Each embodiment described and illustrated herein also includes its complementary embodiment.

Hereinafter, a semiconductor device and a method of manufacturing the same according to embodiments of the present invention will be described with reference to the drawings.

1 to 22 are diagrams for describing a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention.

Referring to FIG. 1, a substrate 100 including a first region A, a second region B, and a third region C is provided. The substrate 100 may be any one of a semiconductor substrate, for example, a silicon substrate or a germanium substrate. The substrate 100 may be a substrate doped with impurities. For example, the substrate 100 may be a p- substrate. Different elements may be formed in the regions A, B, and C. The substrate 100 may have an upper surface 100a, which is a surface on which a plurality of elements are formed, and a lower surface 100b that faces the upper surface 100a.

A semiconductor layer may be formed on the substrate 100. The semiconductor layer may include a first epi layer 102 and a second epi layer 104 sequentially formed on the top surface 100a of the substrate 100. The first and second epi layers 102 and 104 may be formed on the substrate 100 by performing an epitaxial process. The epi layers 102 and 104 may include first to third regions A, B, and C as in the case of the substrate 100. The epitaxial process may be performed using a semiconductor material such as silicon (Si) or germanium (Ge), or a group 3-5 compound semiconductor material. The first and second epi layers 102 and 104 include the same material, but may be doped in-situ. The first epi layer 102 is of a different conductivity type from the substrate 100, and may be doped with a higher impurity concentration. For example, the first epi layer 102 may be an n + epi layer. The second epi layer 104 has the same conductivity type as the first epi layer 102, but may be doped with a lower impurity concentration. For example, the second epi layer 104 may be an n- epi layer. Subsequently, the first oxide layer 106 may be formed on the second epitaxial layer 104. The first oxide film 106 may be formed by performing a deposition process. As an example, the first oxide film 106 may include a silicon oxide film.

Referring to FIG. 2, a collector 200 is formed in the second epi layer 104 in the third region C, and an n-well 300a is formed in the second epi layer 104 in the second region B. It can be formed.

The collector 200 and the n-well 300a may be formed by forming a first nitride layer pattern 108 on the first oxide layer 106 and using the same as a mask to implant n-type impurities. The n-type impurity may include phosphorus. The first nitride film pattern 108 may be formed by depositing a nitride film on the first oxide film 106 and patterning it. As an example, the nitride film may include a silicon nitride film. The first nitride film pattern 108 may expose the first oxide film 106 on the portion where the collector 200 and the n-well 300a are to be formed. The collector 200 is in contact with the second epi layer 104 of the third region C, but may be formed to be spaced apart from the first epi layer 102. Likewise, the n-well 300a may be formed in contact with the epi layer in the second region B, but spaced apart from the first epi layer 102. The collector 200 and the n-well 300a may be formed at the same time.

Subsequently, second oxide films 201 and 301 may be formed on the collector 200 and the n-well 300a. The second oxide films 201 and 301 may be formed by a Local Oxidation of Silicon (LOCOS) process, and may be thicker than the first oxide film 106. After the formation of the second oxide films 201 and 301, a heat treatment process may be performed.

Referring to FIG. 3, a p-well 300b may be formed in the second epi layer 104 of the second region B. The p-well 300b exposes the first oxide layer 106 between the second oxide layers 201 and 301 by patterning the first nitride layer pattern 108 on the second region B, and then removes p-type impurities. It can be formed by ion implantation. The p-well 300b is formed in the second epilayer 104 between the collector 200 and the n-well 300a, and may be formed spaced apart from the first epilayer 102. The p-type impurity may include boron. After the ion implantation of p-type impurities, a heat treatment process may be performed.

Referring to FIG. 4, after the first nitride film pattern 108, the first oxide film 106, and the second oxide film of FIG. 3 are removed, device isolation patterns in the first and second epilayers 102 and 104 ( 133) may be formed.

The device isolation patterns 133 form trenches 131 extending into the substrate 100 through the first and second epi layers 102 and 104 on the substrate 100, and the trenches 131 ) Filling trench insulating patterns 135 and trench gapfill patterns 137. That is, the device isolation patterns 133 may include trench insulation patterns 135 and trench gapfill patterns 137, and the device isolation patterns 133 may include first and second epilayers 102. , 104) and may extend into the substrate 100.

The trenches 131 form a mask pattern on the substrate 100 from which the first nitride layer pattern 108, the first oxide layer 106, and the second oxide layers 201 and 301 of FIG. 3 are removed, and then etch them. An anisotropic etching process using a mask may be performed and formed. Thereafter, a thermal oxidation process is performed on the substrate 100 on which the trenches 131 are formed, thereby forming an oxide film in the trenches 131 and performing a front anisotropic etching process to expose the bottom surface of the trenches 131. Thus, trench insulating patterns 135 may be formed. Subsequently, the trench gap patterns are formed by forming a polycrystalline silicon film filling the trenches 131 on which the trench insulating patterns 135 are formed, and performing a planarization process until the top surface 100a of the second epi layer 104 is exposed. 137 may be formed. The planarization process may include a chemical mechanical polishing (CMP) process. The device isolation patterns 133 formed by the trench isolation technology as described above may form isolation between devices.

Next, the third oxide layer 110 may be formed on the substrate 100 on which the device isolation patterns 133 are formed. For example, the third oxide film 110 may be a silicon oxide film.

Referring to FIG. 5, the base 203 may be formed in the third region C of the second epi layer 104, and the p-body region 400 may be formed in the first region A. The base 203 and the p-body region 400 may be formed by forming a mask pattern (not shown) on the third oxide layer 110 and performing an ion implantation process and a heat treatment process using the ion implantation mask. . The ion implantation process may include ion implantation of p-type impurities on the substrate 100 on which a mask pattern (not shown) is formed. For example, the p-type impurity may include boron. The base 203 may be formed in the collector 200 of the third region C, and the p-body region 400 may be formed in the second epi layer 104. The base 203 and the p-body region 400 may be simultaneously formed. Thereafter, the mask pattern (not shown) may be removed.

Referring to FIG. 6, gate trenches 403 may be formed in the p-body region 400 of the first region A. The gate trenches 403 may be formed by forming a mask pattern (not shown) on the third oxide layer 110 and performing an anisotropic etching process using it as an etching mask. The gate trenches 403 may be etched deeper than the p-body region 400 to extend into the second epi layer 104.

Referring to FIG. 7, buried gate oxide layers 405 and buried gate electrodes 407 may be formed in the gate trenches 403.

The buried gate oxide films 405 may be formed after growing a sacrificial oxide film inside the gate trenches 403 and wet etching to reduce surface curvature in the gate trenches 403. The buried gate electrodes 407 form a polycrystalline silicon film filling the gate trenches 403 on the substrate 100 on which the buried gate oxide films 405 are formed, and the top surface 100a of the second epi layer 104 is formed. It can be formed by performing a planarization process until exposed. As a result, the buried gate electrodes 407 may be formed in a shape buried in the gate trenches 403. The buried gate electrodes 407 may include impurities. As an example, the impurity may include Phosphorus. The planarization process may include chemical mechanical polishing (CMP) and / or dry etching processes. In the course of performing the planarization process, the third oxide layer 110 may also be removed.

Thereafter, the fourth oxide film 112 may be formed on the substrate 100 on which the buried gate electrodes 407 are formed. For example, the fourth oxide film 112 may include a silicon oxide film.

Referring to FIG. 8, field oxide films 150 may be formed on the substrate 100 on which the fourth oxide film 112 is formed. The field oxide layers 150 may be formed by forming a second nitride layer pattern 114 defining an active region on the fourth oxide layer 112 and performing a LOCOS (Local Oxidation of Silicon) process. Here, the active region means a portion covered by the second nitride film pattern 114. The second nitride film pattern 114 may be formed by forming a nitride film on the fourth oxide film 112, forming a mask pattern (not shown) on the nitride film, and performing an etching process using the etching mask. The second nitride film pattern 114 may expose the fourth oxide film 112 at a portion where the field oxide films 150 are to be formed. The field oxide films 150 may be formed on a portion exposed by the second nitride film pattern 114, and may be thicker than the fourth oxide film 112. In one embodiment, after forming the second nitride film pattern 114 and before forming the field oxide films 150, an ion implantation process using the second nitride film pattern 114 as an ion implantation mask may be performed. The ion implantation process is performed to control the field threshold voltage, and may include, for example, ion implantation of boron.

Referring to FIG. 9, after the second nitride film pattern 114 of FIG. 8 is removed, an emitter 205 is formed in the third region C of the second epitaxial layer 104, and the second region B An n-drift region 303 and a p-drift region 305 may be formed therein.

The emitter 205 and the n-drift region 303 define the emitter 205 and the n-drift region 303 on the substrate 100 from which the second nitride film pattern 114 (see FIG. 8) is removed. It can be formed by forming an ion implantation mask (not shown) and ion implanting impurities such as phosphorus. The p-drift region 305 forms an ion implantation mask (not shown) defining the p-drift region 305 on the substrate 100 from which the second nitride layer pattern 114 (see FIG. 8) is removed, and boron ( boron). The emitter 205 and the n-drift region 303 may be formed simultaneously, and then the p-drift region 305 may be formed. Conversely, the p-drift region 305 may be formed first, and then the emitter 205 and the n-drift region 303 may be formed. Emitter 205 may be formed in base 203. The n-drift region 303 may be formed in the p-well 300b, and the p-drift region 305 may be formed in the n-well 300a. A heat treatment process may be performed after the ion implantation process for forming the emitter 205, the n-drift region 303, and the p-drift region 305.

Referring to FIG. 10, after removing the fourth oxide film 112 of FIG. 9 and forming the fifth oxide film 116, an ion implantation process for controlling a threshold voltage may be performed. The fourth oxide film 112 of FIG. 9 may be removed by performing a wet etching process.

The ion implantation process for threshold voltage control is performed by forming a first photosensitive mask 118 exposing the second region B on the substrate 100 on which the fifth oxide film 116 is formed, followed by boron or phosphorus ( Phosphorus) may be included. The ion implantation process may be performed to adjust the threshold voltage of the second device formed in the second region B to a desired range. The threshold voltage can be adjusted by changing the doping concentration of n-well 300a and / or p-well 300b in the second region B by ion implantation of boron or phosphorus. Thereafter, the first photosensitive mask 118 may be removed.

Referring to FIG. 11, a gate oxide layer 120 may be formed on the substrate 100. The gate oxide layer 120 may be formed by performing a dry oxidation process after removing the fifth oxide layer 116 of FIG. 10 by wet etching. Thereafter, gate electrodes 307 may be formed on the gate oxide layer 120 of the second region B. The gate electrodes 307 may be formed by forming a polycrystalline silicon film containing phosphorus on the substrate 100 on which the gate oxide film 120 is formed and patterning it.

Referring to FIG. 12, n-LDDs (Lightly Doped Drain, 309) are formed in the p-well 300b of the second region B, and p-LDDs 311 are formed in the n-well 300a. Can be formed. The n-LDDs 309 form an ion implantation mask (not shown) defining the region of the n-LDDs 309 on the substrate 100 on which the gate electrodes 307 are formed, and phosphorus (Phosphorus) and It can be formed by ion implantation of the same impurities. Similarly, the p-LDDs 311 form an ion implantation mask (not shown) defining the region of the p-LDDs 311 on the substrate 100 on which the gate electrodes 307 are formed, and boron (Boron) ) Can be formed by ion implantation. The n- LDDs 309 and the p- LDDs 311 may be sequentially formed.

In this way, sidewall oxide films 313 may be formed on both sidewalls of the gate electrodes 307. The sidewall oxide films 313 may be formed on the substrate 100 by forming a Tetra Ethyl Ortho Silicate (TEOS) oxide film covering the gate electrodes 307 and performing a dry etching process.

Referring to FIG. 13, a collector junction 207, an emitter junction 209, and a base junction 211 may be formed in the third region C. That is, the collector junction 207, the emitter junction 209, and the base junction 211 may be formed in the collector 200, the emitter 205, and the base 203, respectively. The collector junction 207 and the emitter junction 209 may be doped with n + type, and the base junction 211 may be doped with p + type.

In the p-well 300b of the second region B, n + source / drains 315 and 317 and the p + ground region 325 are formed, and in the n-well 300a, p + source / drains 321, 323) and an n + ground region 319 may be formed. The n + sources / drains 315 and 317 and the n + ground region 319 may be doped with n + type, and the p + sources / drains 321 and 323 and p + ground region 325 may be doped with p + type. have.

N + sources 411 and p + junctions 413 may be formed in the p-body region 400 of the first region A. The n + sources 411 may be formed on both sides of the buried gate electrodes 407, and the p + junctions 413 may be formed between the n + sources 411. The n + sources 411 may be doped with n + type, and the p + junctions 413 may be doped with p + type.

These collector junctions 207, emitter junctions 209, base junctions 211, n + source / drains 315, 317, p + ground region 325, p + source / drains 321, 323, n + The ground region 319, the n + sources 411, and the p + junctions 413 may be formed by ion implanting an n + type impurity or a p + type impurity by sequentially using ion implantation masks (not shown). For example, the n + type impurity may include arsenic (As), and the p + type impurity may include boron (Boron).

Referring to FIG. 14, an interlayer insulating film 500 covering the gate electrodes 307 and first to third openings 501, 503, and 505 penetrating the interlayer insulating film 500 are formed on the substrate 100. Can be.

The interlayer insulating film 500 may be formed by applying a TEOS (Tetra Ethyl Ortho Silicate) oxide film and / or a BPSG (Borophospho Silicate Glass) oxide film on the result of FIG. 13 and performing a planarization process by heat treatment. The first to third openings 501, 503, and 505 may be formed by forming a mask pattern on the substrate 100 on which the interlayer insulating layer 500 is formed, and performing an etching process using the mask pattern. Such an etching process may include wet and / or dry etching. The first openings 501 may expose the collector junction 207, the emitter junction 209, and the base junction 211 of the third region C. The second openings 503 are n + source / drains 315 and 317 of the second region B, p + ground region 325, p + source / drains 321 and 323, and n + ground region 319. Can expose. The third openings 505 may expose n + sources 411 and p + junctions 413 of the first region A.

15, metal wires 511, 513, and 515 filling the first to third openings 501, 503, and 505 may be formed. The metal wires 511, 513, and 515 may be formed by forming a metal film filling the first to third openings 501, 503, and 505 and patterning it to perform a heat treatment process. The metal film may include aluminum (Al). The first metal wires 511 may be electrically connected to the collector junction 207, the emitter junction 209, and the base junction 211 of the third region C. The second metal wires 513 include n + source / drains 315 and 317 of the second region B, p + ground region 325, p + source / drains 321 and 323, and n + ground region 319. ) Can be electrically connected. The third metal wires 515 may be electrically connected to n + sources 411 and p + junctions 413 of the first region A.

Referring to FIG. 16, a grinding process of removing the lower surface 100b (see FIG. 15) of the substrate 100 (see FIG. 15) may be performed to form the thinned substrate 101. In the grinding process, after performing a taping operation of attaching a tape (not shown) on the substrate 100 (see FIG. 15) on which the metal wires 511, 513, and 515 are formed, the grinding process is performed. It may include thinning the lower surface (100b, see FIG. 15). The taping operation may be performed to protect the front surface of the substrate 100 (see FIG. 15) on which the metal wires 511, 513, and 515 are formed. The thinned substrate 101 may have an upper surface 101a contacting the first epi layer 102 and a lower surface 101b facing the first epi layer 102.

Thereafter, the first protective oxide layer 520 may be formed on the lower surface 101b of the thinned substrate 101. The first protective oxide film 520 may include a silicon oxide film, and may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process.

Referring to FIG. 17, a portion of the first protective oxide layer 520 and the thinned substrate 101 may be removed. Removing a portion of the first protective oxide layer 520 and the thinned substrate 101 forms a second photosensitive mask 525 exposing a portion of the first region A on the first protective oxide layer 520 and , It may include performing an anisotropic etching process using this as an etching mask. The etching process may be performed until the first epi layer 102 of the first region A is exposed. As a result, a portion of the first protective oxide layer 520 and the thinned substrate 101 may be removed, and one sidewall 101c of the thinned substrate 101 may be exposed. In one embodiment, a part of the first epi layer 102 may be recessed by being over-etched when performing the etching process. That is, the first epi layer 102 may include a recessed first epi layer portion 102a.

Referring to FIG. 18, after the second photosensitive mask 525 (see FIG. 17) is removed, a second protective oxide film (on the front surface of the result of removing the first protective oxide film 520 and a portion of the thinned substrate 101) 530) may be formed. That is, the second protective oxide layer 530 may be conformally formed on the lower surface 101b of the thinned substrate 101 from which the second photosensitive mask 525 (see FIG. 17) is removed. The second protective oxide layer 530 covers the first protective oxide layer 520 and may extend to one side wall 101c of the thinned substrate 101 exposed by the etching process of FIG. 17. In addition, the second protective oxide layer 530 may cover the recessed first epilayer portion 102a. According to an embodiment, the second protective oxide layer 530 may be thicker than the first protective oxide layer 520. The second protective oxide layer 530 may include a silicon oxide layer, and may be formed by a plasma-enhanced chemical vapor deposition (PECVD) process.

Referring to FIG. 19, a sidewall insulating pattern 531 may be formed on one sidewall 101c of the thinned substrate 101. The sidewall insulating pattern 531 may be formed by performing a front anisotropic etching process on a result of forming the second protective oxide layer 530. The anisotropic etching process may be performed until the second protective oxide layer 530 on the recessed first epilayer portion 102a is removed. As a result, a sidewall insulating pattern 531 defined on one sidewall 101c of the substrate 101 on which the second protective oxide layer 530 is thinned may be formed. The lower surface of the sidewall insulating pattern 531 may contact the recessed first epilayer portion 102a. In addition, as a result of the etching process, the first protective oxide layer 520 and the recessed first epilayer portion 102a may be exposed. The sidewall insulating pattern 531 may serve to isolate the device in the first region A from adjacent devices.

Referring to FIG. 20, an ohmic contact layer 540 may be formed on the entire surface of the resultant product having the sidewall insulating pattern 531. That is, the ohmic contact layer 540 may be formed to conformally cover the first protective oxide layer 520, the sidewall insulating pattern 531, and the recessed first epilayer portion 102a. The ohmic contact layer 540 may include a metal material such as aluminum (Al), and may be formed by a metal deposition process or a plating process. The ohmic contact layer 540 may be formed to lower the on-resistance of the device formed in the first region A.

Referring to FIG. 21, a drain 551 may be formed on the recessed first epi layer portion 102a. The drain 551 is formed by forming a mask pattern (not shown) defining an area where the drain 551 is to be formed on the result of FIG. 20 in which the ohmic contact layer 540 is formed, and performing a plating process or a screen printing process. Can be. As a result, a drain 551 filling the region where the thinned substrate 101 is removed may be formed on the recessed first epi layer portion 102a. The drain 551 may include at least one of silver (Ag) or copper (Cu). For example, the plating process may be performed using a material containing at least one of silver (Ag) or copper (Cu). Similarly, the screen printing process may be performed using at least one of silver (Ag) paste or copper (Cu) paste.

According to another embodiment, the drain 551 may be formed on the front surface of the result of the ohmic contact layer 540 as shown in FIG. 22. The drain 551 may be formed by performing a plating process or a screen printing process on the entire surface of the result of FIG. 20 on which the ohmic contact layer 540 is formed. As a result, the drain 551 may cover the recessed first epilayer portion 102a and extend over the lower surface 101b of the thinned substrate 101.

Different elements may be formed in the first to third regions A, B, and C through the series of processes described above.

The first region A may be defined as a region of the first element. For example, the first region A may be defined as a region of a diffused metal-oxide-semiconductor (DMOS) device. The DMOS device may be a TDMOS (Trench Double diffused Metal-Oxide-Semiconductor) device. The first element can be used as a power control circuit. For example, the first element can be used as a switch for high current.

The second region B may be defined as a region of the second element. For example, the second area B may be defined as an area of the CMOS device. The CMOS device may be at least one of PMOS, ED-PMOS, NMOS, or ED-NMOS. At least one of the CMOS devices may be used as a low voltage device or a high voltage device. The second element can be used as a digital element. For example, the second element can be used as a signal control circuit.

The third region C may be defined as a region of the third element. For example, the third element may be a bipolar element. The third element can be used as an analog element. For example, the third element can be included in the temperature sensor.

A typical smart power integrated circuit (Smart Power IC) may be affected, for example, when a high voltage bias is applied to a substrate drain of a high voltage device, a low voltage CMOS device and / or a bipolar device is destroyed.

However, according to embodiments of the present invention, by forming each device on the p-type substrate 100 and providing an isolation structure between each device by a trench isolation technology, a highly reliable semiconductor device can be provided. For example, when a high voltage bias is applied to the first device on the first region A, current flow is allowed through the ohmic contact layer 540, epi layers 102, 104, and the p-body region 400. Meanwhile, the flow of current to the second and third regions B and C may be prevented by the device isolation patterns 133 and the sidewall insulation pattern 531. Accordingly, it is possible to prevent current from entering the second element on the second region B and the third element on the third region C, so that the control circuit can be stabilized.

In addition, the first element on the first region A may provide a structure in which a current is applied in the vertical direction by forming a drain 551 on the lower surface of the first epi layer 102. Accordingly, the high-current driving characteristics are improved, and low on-resistance can be obtained, thereby improving the efficiency of the semiconductor device of the present invention.

So far, the present invention has been focused on the preferred embodiments. Those skilled in the art to which the present invention pertains will understand that the present invention may be implemented in a modified form without departing from the essential characteristics of the present invention. Therefore, the disclosed embodiments should be considered in terms of explanation, not limitation. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the equivalent range should be interpreted as being included in the present invention.

Claims (18)

On the substrate, a first semiconductor layer including a first region including a first element and a second region including a second element;
A device isolation pattern provided in the first semiconductor layer and electrically separating the first device and the second device;
A drain provided on a lower surface of the first region of the first semiconductor layer; And
And a second semiconductor layer provided on a lower surface of the second region of the first semiconductor layer,
The first semiconductor layer includes an n-conductive impurity,
The second semiconductor layer contains p-conductive impurities,
The first semiconductor layer includes a first epi layer in contact with an upper surface of the substrate and a second epi layer on the first epi layer,
The first epi layer is a semiconductor device having a higher impurity concentration than the second epi layer. The method of claim 1,
A semiconductor device further comprising a sidewall insulating pattern between the drain and the second semiconductor layer. The method of claim 1,
A semiconductor device further comprising an ohmic contact layer between the first semiconductor layer and the drain. The method of claim 1,
The drain is a semiconductor device extending over the lower surface of the second semiconductor layer. The method of claim 1,
The device isolation pattern penetrates the first semiconductor layer and extends into the second semiconductor layer. delete delete The method of claim 1,
The first element is a semiconductor device that is a DMOS transistor. The method of claim 1,
The first device includes a source and a buried gate electrode,
The source and the buried gate electrode are semiconductor devices connected to metal wires provided on the first semiconductor layer. The method of claim 1,
The second device is a semiconductor device that is a CMOS device. The method of claim 1,
The first semiconductor layer further includes a third region including a third element,
The third device is a bipolar transistor. Forming first and second epilayers in sequence on a substrate including a first region, a second region, and a third region;
Removing a portion of the first region of the substrate to expose the first epi layer; And
A method of manufacturing a semiconductor device comprising forming a drain on a bottom surface of the exposed first epi layer. The method of claim 12,
Forming the drain includes a method of manufacturing a semiconductor device including performing a plating process or a screen printing process. The method of claim 12,
Further comprising forming device isolation patterns on the substrate,
Forming the device isolation patterns:
Forming trenches extending through the first and second epi layers on the substrate and extending into the substrate;
Forming trench insulating patterns covering sidewalls of the trenches; And
And forming trench gap fill patterns filling the trenches in which the trench insulating patterns are formed,
The trench gap fill pattern is a method of manufacturing a semiconductor device including a polycrystalline silicon film. The method of claim 12,
The method further includes thinning the substrate before removing a portion of the first region,
The method of manufacturing a semiconductor device comprising thinning the substrate includes performing a grinding process. The method of claim 12,
The method may further include forming a sidewall insulating pattern on a sidewall of the substrate where a portion of the first region is removed before forming the drain,
Forming the sidewall insulation pattern:
Forming a protective oxide layer covering the sidewall on the bottom surface of the substrate where a part of the first region is removed; And
A method of manufacturing a semiconductor device comprising performing a front anisotropic etching process on a lower surface of the substrate on which the protective oxide film is formed. The method of claim 12,
Further comprising forming an ohmic contact layer on the lower surface of the exposed first epi layer before forming the drain,
Forming the ohmic contact layer is a method of manufacturing a semiconductor device comprising performing a metal deposition process or a plating process. The method of claim 12,
Forming a DMOS device on the first region;
Forming a CMOS element on the second region; And
A method of manufacturing a semiconductor device, further comprising forming a bipolar device on the third region.

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