KR102073361B1 - Method and computer program for recognizing defect pattern of wafer map based on neural network model - Google Patents

Abstract

The disclosed embodiment converts wafer map data on wafer yield in a semiconductor process into an image and learns about the properties of the defective pattern, based on the generated neural network model, based on the converted image, The present invention relates to a method for recognizing a defect pattern of a wafer based on a neural network model for recognizing a defect pattern of the wafer map data and outputting information on the defect pattern of the recognized wafer map data.

Description

Wafer defect pattern recognition method based on neural network model and computer program for it {METHOD AND COMPUTER PROGRAM FOR RECOGNIZING DEFECT PATTERN OF WAFER MAP BASED ON NEURAL NETWORK MODEL}

The disclosed embodiments relate to a neural network model based wafer defect pattern recognition method and a neural network model based wafer defect pattern recognition method.

In general, a plurality of semiconductor devices (semiconductor chips) are designed on one semiconductor wafer, and each semiconductor device is formed by repeatedly performing various kinds of unit processes. Unit processes for forming such a semiconductor device may be composed of hundreds of production steps.

On the other hand, the process of inspecting the yield of the wafer, which indicates the proportion of abnormal chips among the total chips on the wafer, may be performed at the end of several hundred production steps. Thus, for wafers with a high percentage of abnormal chips, when analyzing the cause of the defect, it may be very difficult to analyze which of the hundreds of production stages the defect occurred.

Therefore, various studies have been conducted on techniques for analyzing the cause of defects in semiconductors. For example, a study of analyzing a defect pattern generated on a wafer has been conducted by using the fact that the defect pattern is different according to the type of the process in which the defect occurs. However, as the types of the bad patterns vary, it is difficult to identify the types, and there is a need to develop a technology for analyzing still bad patterns.

The defect pattern of the wafer map generated in the semiconductor process may be automatically classified according to the characteristics of the pattern.

According to one or more embodiments, a neural network model based wafer defect pattern recognition method may include converting wafer map data regarding a yield of a wafer in a semiconductor process into an image; Recognizing a defect pattern of wafer map data based on the converted image using a neural network model generated as a result of learning about the characteristic of the defect pattern; And outputting information about the defective pattern of the recognized wafer map data.

According to an embodiment, a method of recognizing a wafer failure pattern based on a neural network model may include at least one layer constituting a neural network model based on characteristic information extracted from images of a plurality of wafer maps each having a type of a failure pattern specified therein. The method may further include updating a parameter of.

According to an embodiment, a method of recognizing a wafer failure pattern based on a neural network model may include converting a plurality of wafer map data acquired for learning a neural network model into an image; And specifying the type of the defective pattern for each of the images of the plurality of wafer maps obtained as a result of the conversion.

According to one or more embodiments, a neural network model-based wafer failure pattern recognition method includes: obtaining an actual image of a plurality of wafer maps each having a type of a failure pattern specified; And converting the obtained actual images of the plurality of wafer maps according to preset logic to generate at least one virtual image from the images of the plurality of wafer maps.

According to one or more embodiments, a neural network model-based wafer defect pattern recognition method performs at least one of rotation, position shift, noise addition, noise cancellation, and image integration on each of the real and virtual images of a plurality of wafer maps. The method may further include generating a wafer map image.

A computer program stored in a computer readable storage medium for a method for recognizing a wafer defect pattern based on a neural network model according to an embodiment may cause a computer to generate wafer map data regarding wafer yield in a semiconductor process. Converting to an image; Recognizing a defect pattern of the wafer map data based on the converted image by using a neural network model generated as a result of learning about the characteristic of the defect pattern; And outputting information on the defective pattern of the recognized wafer map data.

According to the disclosed embodiments, when analyzing wafer map defect patterns of various types of semiconductor processes, classification accuracy of various types of patterns that are difficult to classify may be increased.

1 is a conceptual diagram illustrating a method for recognizing a wafer failure pattern based on a neural network model, according to an exemplary embodiment.
2 is a flowchart illustrating a method for recognizing a wafer failure pattern based on a neural network model, according to an exemplary embodiment.
FIG. 3 is a diagram illustrating a method of recognizing a neural network model and recognizing a bad pattern based on the bad pattern recognition apparatus according to an exemplary embodiment.
4 is a diagram for describing a labeling process, according to an exemplary embodiment.
FIG. 5 is a diagram for describing a method of generating and propagating a virtual wafer map image for neural network learning, according to an exemplary embodiment.
6 is a diagram illustrating in detail the structure of a neural network model according to an embodiment.
7 is a block diagram of an apparatus for recognizing a bad pattern, according to an exemplary embodiment.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another element in between. . In addition, when a part is said to "include" a certain component, this means that it may further include other components, except to exclude other components unless otherwise stated.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a conceptual diagram illustrating a method for recognizing a wafer failure pattern based on a neural network model, according to an exemplary embodiment.

Referring to FIG. 1, in order to recognize a failure pattern of the yield map data 10, the apparatus for recognizing a failure pattern includes generating a neural network model 100 based on a plurality of wafer map images in which a failure pattern is specified. I can learn.

In order to use the neural network model 100 for learning, the bad pattern recognition apparatus may acquire data regarding a plurality of wafer maps obtained in the final step of the semiconductor process. In the wafer map, normal chips and abnormal chips may be distinguished and displayed. The bad pattern recognition apparatus may convert data regarding a plurality of wafer maps into an image form. Since the data on the wafer map stored in the semiconductor production process has a (X, Y) coordinate form, the bad pattern recognition apparatus may convert it into an image form.

The defective pattern recognition apparatus may determine the type of the defective pattern of each of the images of the plurality of wafer maps obtained according to the conversion result. For example, the bad pattern recognition apparatus may perform labeling on the image of the plurality of wafer maps in a linear pattern and a non-linear pattern.

Meanwhile, in order to improve performance of the neural network model 100, the bad pattern recognition apparatus may generate a virtual image from images of a plurality of wafer maps in which types of bad patterns are specified according to preset logic. Hereinafter, for convenience of description, the images of the plurality of wafer maps are referred to as real images, and the images generated therefrom are named as virtual images according to preset logic.

In addition, the bad pattern recognition apparatus may propagate images for learning by applying rotational movement, symmetry movement, noise addition, noise removal, and the like to the actual image and the virtual image of the plurality of wafer maps. The defective pattern recognition apparatus may improve performance of the neural network model 100 by proliferating an image for learning, in addition to an image actually obtained from a semiconductor process.

The bad pattern recognition apparatus may generate a neural network model 100 as a result of learning about characteristics of a bad pattern of wafer map data in a semiconductor process based on the grown image. Each layer constituting the neural network model 100 will be described later in more detail with reference to FIG. 6.

The failure pattern recognition apparatus may recognize the failure pattern of the newly acquired wafer map data 10 using the neural network model 100. For example, the bad pattern recognition apparatus may input an image of the wafer map data 10 into the neural network model 100 to obtain an output value indicating that the bad pattern of the wafer map corresponds to the linear pattern 15. However, this is just an example, and the type of the bad pattern recognizable based on the neural network model 100 is not limited to the linear pattern.

Hereinafter, a method for recognizing a wafer failure pattern based on a neural network model according to an embodiment will be described in detail with reference to FIGS. 2 to 7.

2 is a flowchart illustrating a method for recognizing a wafer failure pattern based on a neural network model, according to an exemplary embodiment.

In operation S210, the bad pattern recognition apparatus may convert the wafer map data regarding the yield of the wafer in the semiconductor process into an image.

According to an exemplary embodiment, the apparatus for recognizing a bad pattern may convert wafer image data for recognizing a kind of a bad pattern into an image.

In operation S220, the apparatus for recognizing a bad pattern may recognize a bad pattern of wafer map data based on the converted image by using a neural network model generated as a result of learning about the property of the bad pattern.

The bad pattern recognition apparatus may store a neural network model generated as a result of learning about characteristics of the bad pattern. The bad pattern recognition apparatus may input the wafer map image acquired in the above-described step S210 into the neural network model. As the wafer map image is input, each layer of the neural network model may extract and combine characteristic information of the wafer map image. As a result, as the output of the neural network model, a characteristic vector representing the type of the bad pattern can be obtained. The bad pattern recognition apparatus may select a bad pattern having the highest probability of being a bad pattern of the wafer map, based on the feature vector.

In operation S230, the bad pattern recognition apparatus may output information regarding a bad pattern of the recognized wafer map data.

According to an exemplary embodiment, the apparatus for recognizing a bad pattern may output information regarding the recognized bad pattern as the type of the bad pattern of the wafer map is recognized from the neural network model. For example, the bad pattern recognition apparatus may output information indicating that the type of the bad pattern of the wafer map corresponds to the linear pattern.

FIG. 3 is a diagram illustrating a method of recognizing a neural network model and recognizing a bad pattern based on the bad pattern recognition apparatus, according to an exemplary embodiment.

Referring to FIG. 3, the bad pattern recognition apparatus may acquire data regarding a wafer map through extraction 305 of a data file from the database 305. In this case, the data regarding the wafer map may be data indicating the position of the abnormal chip in the form of (X, Y) coordinates.

The bad pattern recognition apparatus may acquire a wafer map image from data related to the wafer map through the image file conversion 315. The bad pattern recognition apparatus may perform class labeling 320 on the obtained wafer map image. Here, the class labeling 320 refers to a process of defining the type of bad pattern for each of the obtained wafer map images.

The bad pattern recognition apparatus may generate a virtual wafer map image 330 from the wafer map image 325 labeled with a specific bad pattern. In general, in a semiconductor process, a certain bad pattern (eg, a linear pattern) may be difficult to obtain all the learning data in the semiconductor process as only a small portion of the total data exists. Accordingly, the bad pattern recognition apparatus generates a virtual wafer map image 330 by converting a pattern such as a straight line or a curve constituting the wafer map image 325 labeled with a specific bad pattern based on preset logic. Can be.

In addition, the bad pattern recognition apparatus may propagate the wafer map image 325 and the virtual wafer map image 330 obtained in the actual semiconductor process. For example, the bad pattern recognition apparatus rotates, shifts positions, adds noise, removes noise, and integrates images of the wafer map image 325 and the virtual wafer map image 330 obtained in the actual semiconductor process. Wafer map images can be generated.

The defective pattern recognition apparatus may perform the neural network model training 335 based on the wafer map image 325 obtained in the actual semiconductor process, the virtual wafer map image 330, and the multiplied wafer map image.

The bad pattern recognition apparatus may perform a neural network model test 345 on the neural network model 340 obtained as a learning result. In this case, the wafer map image 325 obtained in the actual semiconductor process may be used for the test. The bad pattern recognition apparatus compares the type of the bad pattern labeled on the wafer map image 325 obtained in the actual semiconductor process with the type of the bad pattern output through the neural network model 340, and thus the neural network model 340. The recognition performance of may be calculated 350.

The bad pattern recognition apparatus may determine the learned neural network model 340 as the final neural network model 355 when the generated error is less than a preset threshold. On the other hand, the bad pattern recognition apparatus may re-learn the training of the neural network model 355 when an error generated as a result of the recognition performance is greater than or equal to a preset threshold.

The defective pattern recognition apparatus according to an embodiment may acquire new wafer map data 360. The bad pattern recognition apparatus may perform image transformation 365 on the obtained wafer map data 360. The bad pattern recognition apparatus may recognize a bad pattern using a neural network model based on the wafer map image obtained as a result of the conversion.

 As a result of performing the neural network model based bad pattern recognition 370, the bad pattern recognition apparatus determines whether the bad pattern of the new wafer map data 360 corresponds to a pattern 375 different from the target pattern or to the target pattern 380. It can be determined whether or not applicable.

4 is a diagram for describing a labeling process, according to an exemplary embodiment.

Referring to FIG. 4, in order to generate training data for a neural network model, the bad pattern recognition apparatus may perform a labeling process on each of images of a plurality of wafer maps.

The apparatus for recognizing a bad pattern according to an exemplary embodiment may label images of a plurality of wafer maps by dividing into a bad pattern corresponding to a target type and a bad pattern corresponding to other types. For example, the bad pattern recognition apparatus may label images of the plurality of wafer maps with the linear pattern 410 and a pattern 420 other than the linear pattern.

The bad pattern recognition apparatus may perform supervised learning for the neural network model by using the images 410 and 420 of the plurality of labeled wafer maps.

However, this is only an example, and the bad pattern recognition apparatus may perform a labeling process by specifying not only the linear pattern but also other types of patterns.

FIG. 5 is a diagram for describing a method of generating and propagating a virtual wafer map image for neural network learning, according to an exemplary embodiment.

Referring to FIG. 5, the apparatus for recognizing a bad pattern may generate virtual data from a wafer map image labeled with a specific bad pattern as a method for obtaining training data for learning a neural network model. For example, the bad pattern recognition apparatus converts a pattern such as a straight line, a curve, and the like, which constitutes a wafer map image 510 having a linear pattern obtained in an actual semiconductor process, based on predetermined logic, thereby converting a virtual wafer map image ( 520 may be generated. Here, the virtual wafer map image 520 may mean a wafer map image having a logical pattern generated logically.

In addition, the defective pattern recognition apparatus may propagate the wafer map image 510 and the virtual wafer map image 530 obtained in an actual semiconductor process in order to secure data necessary for learning. For example, as described above with reference to FIG. 3, the bad pattern recognition apparatus may include rotation, position shift, and noise addition to the wafer map image 510 and the virtual wafer map image 530 obtained in an actual semiconductor process. Noise cancellation and image integration may be performed to generate a new wafer map image 530.

Meanwhile, in the exemplary embodiment disclosed in FIG. 5, a method of generating virtual data from a wafer map image having a linear defect pattern and multiplying the same has been described. However, this is merely an example. Can be applied.

6 is a diagram for describing in detail the structure of the neural network model 600 according to an embodiment.

Referring to FIG. 6, the neural network model 600 used to recognize a bad pattern includes at least one convolutional layer 610, at least one pulling layer 620, and at least one pulley-connected layer 630. It can be configured as. For example, the neural network model 600 may have five convolutional layers 610, four pulling layers 620, and two pulley-connected layers 630 arranged as shown in FIG. 6. .

The convolution layer 610 is a layer for extracting meaningful characteristic information from the input wafer map image 605. In order to identify meaningful characteristic information, parameters of the layer may be determined through repetitive learning. In addition, the pooling layer 620 may serve as a subsampling to reduce characteristic information included in the image. In the present embodiment, as an example of the pulling layer 620, a max pulling layer may be used. In addition, the pulley-connected layer 630 may serve to classify the characteristic information extracted through the pulling layer 620 or the convolution layer 610.

The characteristic information classified through the pulley-connected layer 630 may be stochasticly calculated through the softmax layer 650 to determine what kind of defect pattern belongs to.

The bad pattern recognition apparatus may determine the type of the bad pattern of the input wafer map image 605 based on the probability value calculated through the softmax layer 650.

Meanwhile, the neural network model 600 illustrated in FIG. 6 is only an example of a neural network model for recognizing a bad pattern, and a structure of a neural network model used for recognizing a bad pattern according to an embodiment is shown in this embodiment. It is not limited. The neural network model may have a different structure depending on the type of wafer and the type of defective pattern to be targeted.

7 is a block diagram of a bad pattern recognition apparatus 700 according to an exemplary embodiment.

In the defective pattern recognition apparatus 700 illustrated in FIG. 7, only components related to the present exemplary embodiment are illustrated. Therefore, it will be understood by those skilled in the art that other general purpose components may be further included in addition to the components illustrated in FIG. 7.

Referring to FIG. 7, the bad pattern recognition apparatus 700 may include an input / output unit 710, a processor 720, and a memory 730.

The input / output unit 710 may obtain at least one wafer map. For example, the input / output unit 710 may acquire a wafer map for use in learning a neural network model. In addition, the input / output unit 710 may acquire a wafer map image for recognizing a defective pattern using a trained neural network model.

The processor 720 may convert the wafer map data regarding the yield of the wafer in the semiconductor process into an image. In addition, the processor 720 may recognize the defect pattern of the wafer map data based on the converted image by using a neural network model generated as a result of learning about the characteristic of the defect pattern. For example, the processor 720 may recognize that the bad pattern of the wafer map data is a linear pattern.

The processor 720 may output information about the defective pattern of the recognized wafer map data through the input / output unit 710. In this case, the output information may be displayed through an external device connected to the bad pattern recognition apparatus 700, or when a display (not shown) is provided in the input / output unit 710, the output information may be displayed through a display (not shown). Can be.

The processor 720 may update the parameters of at least one layer constituting the neural network model based on the characteristic information extracted from the images of the plurality of wafer maps in which the types of the bad patterns are specified. In addition, the processor 720 may evaluate the performance of the neural network model using the labeled wafer map image as the parameter of the layer is updated.

The processor 720 may convert the plurality of wafer map data acquired for training the neural network model into an image. In addition, the processor 720 may specify the type of the defective pattern for each of the images of the plurality of wafer maps obtained as a result of the conversion.

The processor 720 may obtain an actual image of the plurality of wafer maps, each of which is specified as a kind of a bad pattern. In addition, the processor 720 may generate at least one virtual image from the images of the plurality of wafer maps by converting the obtained actual images of the plurality of wafer maps according to preset logic.

In addition, the processor 720 may generate a new wafer map image by performing at least one of rotation, position shift, noise addition, noise deletion, and image integration to each of the real image and the virtual image of the plurality of wafer maps.

The memory 730 may store information or data acquired by the bad pattern recognition apparatus 700, and may store an area for storing data necessary for controlling the processor 720 and data generated when the processor 720 controls the processor 720. Can have.

For example, the memory 730 may store a neural network model used for recognition of a bad pattern. According to another example, the memory 730 may store a result of recognizing a bad pattern for a wafer map image.

The memory 730 may be configured in various forms, such as a ROM or / and RAM or / and a hard disk or / and a CD-ROM or / and DVD.

The device according to the invention comprises a processor, a memory for storing and executing program data, a permanent storage such as a disk drive, a communication port for communicating with an external device, a user interface such as a touch panel, a key, a button and the like. Devices and the like. Methods implemented by software modules or algorithms may be stored on a computer readable recording medium as computer readable codes or program instructions executable on the processor. The computer-readable recording medium may be a magnetic storage medium (eg, read-only memory (ROM), random-access memory (RAM), floppy disk, hard disk, etc.) and an optical reading medium (eg, CD-ROM). ) And DVD (Digital Versatile Disc). The computer readable recording medium can be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion. The medium is readable by the computer, stored in the memory, and can be executed by the processor.

All documents, including publications, patent applications, patents, and the like cited in the present invention, may be incorporated into the present invention as if each cited document is individually and specifically shown as merged or as totally merged in the present invention. .

For the purpose of understanding the present invention, reference numerals have been set forth in the preferred embodiments shown in the drawings, and specific terms are used to describe the embodiments of the present invention, but the present invention is not limited to the specific terms, and the present invention May include all components conventionally conceivable to those skilled in the art.

The invention can be represented by functional block configurations and various processing steps. Such functional blocks may be implemented in various numbers of hardware or / and software configurations that perform particular functions. For example, the present invention relates to integrated circuit configurations such as memory, processing, logic, look-up table, etc., which may execute various functions by the control of one or more microprocessors or other control devices. It can be adopted. Similar to what the components of the present invention can be implemented in software programming or software elements, the present invention includes a variety of algorithms implemented in data forms, processes, routines or other programming constructs, including C, C ++ It may be implemented in a programming or scripting language such as Java, assembler, or the like. Functional aspects may be implemented in algorithms running on one or more processors. In addition, the present invention may employ the prior art for electronic environment setting, signal processing, and / or data processing. Terms such as "mechanism", "element", "means" and "configuration" can be used widely and are not limited to mechanical and physical configurations. The term may include the meaning of a series of routines of software in conjunction with a processor or the like.

Particular implementations described in the present invention are embodiments and do not limit the scope of the present invention in any way. For brevity of description, descriptions of conventional electronic configurations, control systems, software, and other functional aspects of the systems may be omitted. In addition, the connection or connection members of the lines between the components shown in the drawings are illustrative of the functional connection and / or physical or circuit connections as an example, in the actual device replaceable or additional various functional connections, physical It may be represented as a connection, or circuit connections. In addition, unless otherwise specified, such as "essential", "important" may not be a necessary component for the application of the present invention.

Claims (6)

In the method of wafer defect pattern recognition based on neural network model,
Acquiring an actual image of the plurality of wafer maps each of which the type of the defective pattern is specified;
Generating a plurality of virtual images from the actual images of the plurality of wafer maps by converting the obtained actual images of the plurality of wafer maps according to preset logic;
Generating a new wafer map image by performing at least one of rotation, position shift, noise addition, noise cancellation, and image integration to each of the plurality of actual images and the plurality of virtual maps of the wafer map;
Training a neural network model consisting of a plurality of convolutional layers, a pooling layer, and a pulley-connected layer for defective pattern recognition based on the real image of the plurality of wafer maps, the plurality of virtual images, and the new wafer map image. step;
Receiving wafer map data about a yield of a wafer to recognize a defective pattern;
Converting the input wafer map data into an image;
Recognizing a bad pattern of the wafer map data based on the converted image using the learned neural network model; And
Outputting information regarding a defective pattern of the recognized wafer map data. The method of claim 1,
Updating a parameter of at least one layer constituting the neural network model based on the characteristic information extracted from the actual image of the plurality of wafer maps, the plurality of virtual images and the new wafer map image; , Way. The method of claim 1, wherein obtaining an actual image of the plurality of wafer maps comprises:
Obtaining a real image of the plurality of wafer maps by converting the plurality of wafer map data obtained for learning the neural network model into an image form. delete delete Let the computer
Acquiring an actual image of the plurality of wafer maps each of which the type of the defective pattern is specified;
Generating a plurality of virtual images from the actual images of the plurality of wafer maps by converting the obtained actual images of the plurality of wafer maps according to preset logic;
Generating a new wafer map image by performing at least one of rotation, position shift, noise addition, noise cancellation, and image integration to each of the plurality of actual images and the plurality of virtual maps of the wafer map;
Training a neural network model consisting of a plurality of convolutional layers, a pooling layer, and a pulley-connected layer for defective pattern recognition based on the real image of the plurality of wafer maps, the plurality of virtual images, and the new wafer map image. step;
Receiving wafer map data about a yield of a wafer to recognize a defective pattern;
Converting the input wafer map data into an image;
Recognizing a bad pattern of the wafer map data based on the converted image using the learned neural network model; And
And outputting information regarding a bad pattern of the recognized wafer map data.

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