KR102071527B1 - Memory device performing multiple core accesses with bank group - Google Patents

Abstract

A memory device for performing multi-core access to a plurality of bank groups is disclosed. According to an embodiment of the invention, the burst length is b (b is an integer greater than or equal to 2), and k (k is an integer greater than or equal to 2 or less) core accesses per command, The memory device for receiving a command may include a memory cell array including a plurality of bank groups, and a plurality of bank groups provided for each bank group and generating a multiplexer control signal for selecting some of read data of a corresponding bank group. A control unit, and a multiplexer for sequentially outputting the read data of the plurality of bank groups in accordance with the multiplexer control signal received from the plurality of bank group control unit. Each data included in the output data of the multiplexer has the same length of time.

Description

MEMORY DEVICE PERFORMING MULTIPLE CORE ACCESSES WITH BANK GROUP}

The present invention relates to a memory device for multi-core access to a plurality of bank groups, and more particularly to a memory device for controlling the input and output data of the bank group to implement any burst length.

As memory speeds increase, the adoption of bank groups is increasing to reduce core access speeds while keeping the total bandwidth equal.

However, when banking in a memory device with multiple memory core accesses, it is not possible to implement any burst length specified in the spec. That is, for example, when the burst length is 2 in the memory core of the 2-bit pre-fetch structure, the bank group may be implemented. However, when the burst length is 4, the bank group cannot be used.

Accordingly, an object of the present invention is to provide a memory device that implements an arbitrary burst length by controlling input / output data of a bank group.

According to an embodiment of the present invention, the burst length is b (b is an integer of 2 or more), and k (k is an integer of 2 or more and b or less) core accesses per command. The memory device for receiving a command includes: a memory cell array including a plurality of bank groups; A plurality of bank group controllers provided for each bank group and generating a multiplexer control signal for selecting some of read data of a corresponding bank group; And a multiplexer for sequentially outputting read data of the plurality of bank groups according to the multiplexer control signal received from the plurality of bank group controllers, wherein each data included in the output data of the multiplexer has the same length of time. Has

The multiplexer control signal may select a portion of the read data to which read data by a first access and a second access are connected.

The multiplexer control signal may be synchronized with the read data, and the memory device may further include a third latch configured to output delay data, which delays read data by a first access, from the read data to the multiplexer.

In this case, b = k * n, and n may be the number of bank groups.

The memory device may further include a mode register, and the mode register may set the value of n.

At this time, tCCDL = 4 and tCCDS = 2.

The memory device receives the command and memory write data, and the plurality of bank group controllers receive data corresponding to a corresponding bank group among the memory write data, and include each of the data included in the received data. The bank group write data can be generated so that the data is continuously connected and have the same time space, and output to the corresponding bank group.

Each of the plurality of bank group controllers selects a command corresponding to a corresponding bank group among the commands, generates an internal command of the corresponding bank group by overlapping the number of core accesses, and generates a pulse corresponding to an operation command of the internal command. It may include a control signal generator for generating a latch control signal including a.

Each of the plurality of bank group controllers may include: a first latch configured to latch the received data so as to eliminate a gap between the received data; And a second latch configured to latch output data of the first latch according to the latch control signal to generate bank group write data in which each data included in the output data has the same length of time.

According to another embodiment of the present invention, the burst length is b (b is an integer of 2 or more), and k (k is an integer of 2 or more and b or less) core accesses per command (CMD). And a memory device for receiving commands and memory write data, the memory cell array including a plurality of bank groups; And each bank group, and receives data corresponding to a corresponding bank group among the memory write data, and adjusts each data included in the received data to be continuous and have the same time space. And a plurality of bank group controllers for generating one bank group write data and outputting the bank group write data to the corresponding bank group.

Each of the plurality of bank group controllers selects a command corresponding to a corresponding bank group among the commands, generates an internal command of the corresponding bank group by overlapping the number of core accesses, and generates a pulse corresponding to an operation command of the internal command. It may include a control signal generator for generating a latch control signal comprising.

Each of the plurality of bank group controllers may include: a first latch configured to latch the received data so as to eliminate a gap between the received data; And a second latch configured to latch output data of the first latch according to the latch control signal to generate bank group write data in which each data included in the output data has the same length of time.

In this case, b = k * n, and n may be the number of bank groups.

The memory device may further include a mode register, and the mode register may set the value of n.

At this time, tCCDL = 4 and tCCDS = 2.

According to the memory device according to the embodiment of the present invention, a bank group can be used while implementing an arbitrary burst length, thereby improving the speed of the memory device.

1 is a block diagram illustrating a memory device according to an example embodiment.
2 is a block diagram illustrating in detail a memory device according to an embodiment of the present invention.
3 is a block diagram illustrating in detail the first bank group controller illustrated in FIG. 2.
4 is a block diagram of an input / output data processing unit according to another exemplary embodiment of the present invention.
5 is a timing diagram during a write operation according to an embodiment of the present invention.
Fig. 6 is a timing diagram showing a conventional write operation in which the burst length is 4 and the core accesses twice.
6A shows that there is no bank group, and tCCD = 2.
6B illustrates a case in which a bank group is used and tCCD = 4.
6C shows a case where tCCDL = 4 and tCCDS = 1, 3 using a bank group.
7 is a timing diagram during a read operation according to an embodiment of the present invention.
8 is a timing diagram during a read operation according to another embodiment of the present invention.
9 is a timing diagram showing a conventional read operation in which the burst length is 4 and the core accesses twice.
9A shows the case where there is no bank group (non BG), where tCCD = 2.
9B illustrates a case where a bank group is used and tCCD = 4.
9C shows a case where tCCDL = 4 and tCCDS = 1, 3 using a bank group.
10A illustrates a layout showing a write path according to an embodiment of the present invention.
10B illustrates a layout showing a read path according to an embodiment of the present invention.
FIG. 11 illustrates an embodiment of a computer system including the semiconductor memory device shown in FIG. 1.
12 illustrates another embodiment of a computer system including the semiconductor memory device shown in FIG. 1.
FIG. 13 illustrates another embodiment of a computer system including the semiconductor memory device shown in FIG. 1.
FIG. 14 illustrates another embodiment of a computer system including the semiconductor memory device shown in FIG. 1.

Specific structural or functional descriptions of the embodiments according to the inventive concept disclosed herein are provided for the purpose of describing the embodiments according to the inventive concept only. It may be embodied in various forms and is not limited to the embodiments described herein.

Embodiments according to the inventive concept may be variously modified and have various forms, so embodiments are illustrated in the drawings and described in detail herein. However, this is not intended to limit the embodiments in accordance with the concept of the invention to the specific forms disclosed, and includes all changes, equivalents, or substitutes included in the spirit and scope of the present invention.

Terms such as first or second may be used to describe various components, but the components should not be limited by the terms. The terms are only for the purpose of distinguishing one component from another, for example, without departing from the scope of the rights according to the inventive concept, the first component may be called a second component and similarly The second component may also be referred to as the first component.

When a component is said to be "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but it may be understood that another component may be present in the middle. Should be. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between. Other expressions describing the relationship between components, such as "between" and "immediately between" or "neighboring to" and "directly neighboring", should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. As used herein, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof that is described, and that one or more other features or numbers are present. It should be understood that it does not exclude in advance the possibility of the presence or addition of steps, actions, components, parts or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and, unless expressly defined herein, are not construed in ideal or excessively formal meanings. Do not.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a memory device according to an example embodiment.

Referring to FIG. 1, a memory device 100 according to an embodiment of the present invention may include a command / address receiving unit 110, a command / address decoder 120, a memory cell array 130, and a write / read circuit 140. , An input / output data processor 150 and a data input / output unit 160.

The command / address receiving unit 110 may receive a plurality of control signals / CS, / WE, / CAS, / RAS and address signals A0 to A12 and BA0 to BA3. In addition, the command / address receiving unit 110 may receive a clock enable signal / CKE, a clock signal CK, and an inverted clock signal / CK.

The command / address decoder 120 decodes the received control signals / CS, / WE, / CAS and / RAS and address signals A0 to A12 and BA0 to BA3, and stores the memory cells based on the decoded signals. The array 130 can be accessed. The command / address decoder 120 may include a mode register MRS 121 to control whether a bank group is used.

The memory cell array 130 may include a first bank group 131 and a second bank group 133. Although only two bank groups are shown in the drawing for convenience, two or more bank groups may be included.

The write / read circuit 140 may write data to memory cells in the first bank group 131 and the second bank group 133, or verify read or read data stored in the memory cell. )can do.

The input / output data processor 150 receives a command CMD from the command / address decoder 120. The input / output data processing unit 150 adjusts the timing of the write data received from the input / output circuit 160 to the write / read circuit 140 during the write operation based on the command CMD, and outputs the read / write circuit 140 to the write / read circuit 140. The timing of the output data received from the readout circuit 140 is adjusted and output to the input / output circuit 160. The detailed configuration of the input / output data processing unit 150 will be described later with reference to FIGS. 2 and 3.

The input / output circuit 160 provides the data DQ to the input / output data processor 150 or receives the data DQ from the input / output data processor 150 to provide the data DQ.

2 is a block diagram illustrating in detail a memory device according to an embodiment of the present invention.

Referring to FIG. 2, the write / read circuit 140 may include a first write / read circuit 141 and a second write / read circuit corresponding to the first bank group 131 and the second bank group 133, respectively. 143). The input / output data processor 150 includes a first bank group controller 170, a second bank group controller 180, and a multiplexer 195.

The first bank group controller 170 and the second bank group controller 180 are disposed for each bank group 131 and 133, respectively, and receive a command CMD from the command / address decoder 120. The first bank group controller 170 and the second bank group controller 180 receive the first write data DATA_A and the second write data DATA_B through the input / output circuit 160 during a write operation, and receive a command ( Based on the CMD, the timing of the received write data DATA_A and DATA_B is adjusted to generate the bank group write data DATA_A_2 and DATA_B_2, and the corresponding first write / read circuit 141 or second write / read, respectively. Output to the circuit 143. During the read operation, the first bank group controller 170 and the second bank group controller 180 generate the first multiplexer control signal EN_A and the second multiplexer control signal EN_B based on the command CMD. Output to multiplexer 195.

The multiplexer 195 receives the first read data SA_A and the second read data SA_B from the first write / read circuit 141 and the second write / read circuit 143 in a read operation. The multiplexer 195 sequentially selects the first read data SA_A and the second read data SA_B according to the multiplexer control signals EN_A and EN_B received from the plurality of bank group controllers 170 and 180. The MUX_OUT is output to the input / output circuit 160.

3 is a block diagram illustrating in detail the first bank group controller illustrated in FIG. 2.

Referring to FIG. 3, the first bank group controller 170 includes a write / read controller 171, a first latch 173, and a second latch 175.

The write / read control unit 171 may receive the command CMD, and generate and output the latch control signal 2nd_En_A to the second latch 175 based on the command CMD during the write operation. The write / read control unit 171 may generate the first multiplexer control signal EN_A based on the command CMD and output the generated multiplexer 195 to the multiplexer 195 during the read operation.

The first latch 173 receives the first write data DATA_A and latches the clock according to the clock CLK to generate the first latch data DATA_A_1 by eliminating a gap in the first write data DATA_A. Output to the second latch 175. However, in some embodiments, the first latch 173 receives the first latch control signal 1st_EN_A from the write / read control unit 171 instead of the clock CLK and writes the first latch according to the first latch control signal 1st_EN_A. The data DATA_A may be latched.

The second latch 175 latches the first latch data DATA_A_1 according to the latch control signal 2nd_En_A, so that each data included in the first latch data DATA_A_1 has the same time space. The bank group write data DATA_A_2 is generated and output to the first write / read circuit 141. Detailed operations of the first latch 173 and the second latch 175 will be described later with reference to FIG. 5.

Meanwhile, the second bank group controller 180 may also have the same configuration as the first bank group controller 170 and perform the same function.

4 is a block diagram of an input / output data processing unit according to another exemplary embodiment of the present invention.

Referring to FIG. 4, the input / output data processor 150 ′ further includes a third latch 191 as compared to the input / output data processor 150 illustrated in FIG. 2. The third latch 191 may include a first read latch 192 and a second read latch 193 corresponding to each bank group. The third latch 191 receives the first read data SA_A and the second read data SA_B, and delays the read data by the first access from the read data SA_A and SA_B to delay the read data SA_A and SA_B. Will output A detailed operation of the input / output data processor 150 'will be described later with reference to FIG. 8.

5 is a timing diagram during a write operation according to an embodiment of the present invention.

5 is a diagram for the case where two bank groups are used, tCCDL = 4, and tCCDS = 2. The column address to column address delay (tCCD) is a time delay after the column address is applied until the next column address is applied. tCCDL is a time delay for accessing the same bank group after accessing the selected bank group, and tCCDS is time delay for accessing another bank group after accessing the selected bank group.

However, the scope of the present invention is not limited thereto. For example, the number of bank groups set in the mode register and the values of tCCDL and tCCDS can be changed by external commands.

The burst length may be a value obtained by multiplying the number of bank groups by the number of core accesses per command (CMD). That is, if the burst length is b (an integer greater than or equal to 2), the number of core accesses per command is k (an integer greater than or equal to 2), and the number of bank groups is n (an integer greater than or equal to 2), then b = k * n. . In FIG. 5, to support burst length 4, the number of bank groups may be determined as 2, and the number of core accesses per command may also be determined as 2.

2, 3, and 5, the first bank group controller 170 and the second bank group controller 180 receive a command CMD from the command / address decoder 120. The command CMD includes respective commands WR A and WR B corresponding to the first bank group and the second bank group. Hereinafter, a method of controlling write data of the first bank group 131 will be described. The method of controlling write data of the first bank group 131 and the second bank group 133 is the same.

The write / read control unit 171 selects the command WR A corresponding to the first bank group among the commands CMD, and generates a first internal command CMD_A_i by overlapping the number of core accesses. The write / read control unit 171 may include a latch control signal 2nd_En_A including a pulse corresponding to the operation instructions WR A and WR A ′ of the first internal command CMD_A_i based on the first internal command CMD_A_i. Is generated and output to the second latch 175.

The write data DQ includes both write data for the first bank group and the second bank group. The input / output circuit 160 selects only the write data WR DATA A and WR DATA A 'for the first bank group among the write data DQ to generate the first write data DATA_A and the first bank group 131. It outputs to the first bank control unit 170 corresponding to the.

The first latch 173 receives the first write data DATA_A and latches the first latch data according to the clock signal CLK, thereby eliminating a gap between the respective data of the first write data DATA_A. DATA_A_1 may be generated and output to the second latch 175.

The second latch 175 latches the first latch data DATA_A_1 according to the latch control signal 2nd_En_A, and adjusts each data 210, 220, 230, 240,... To have the same length of time. The bank group write data DATA_A_2 is generated and output to the first write / read circuit 141.

The first write / read circuit 141 receives the bank group write data DATA_A_2 output from the second latch 175 and outputs the bank group write data DATA_A_2 to the first bank group 131. At this time, since the write speed of the bank group write data DATA_A_2 is 1/2 of the speed of the write data DQ, the core access speed can be reduced.

Fig. 6 is a timing diagram showing a conventional write operation in which the burst length is 4 and the core accesses twice. 6A shows the case where there is no bank group (non BG), where tCCD = 2. 6B illustrates a case in which a bank group is used and tCCD = 4. 6C shows a case where tCCDL = 4 and tCCDS = 1, 3 using a bank group.

Referring to FIG. 6A, since tCCD = 2, the write commands WR A and WR B may be applied at intervals of two clock cycles of the clock signal CLK. If there is no bank group, no problem occurs in the write data DQ even if the core access is performed twice. However, it is not possible to reduce the core access speed because no bank group is used.

Referring to FIG. 6B, when changing from tCCD = 2 to 4 using the bank group, the write command may be input at intervals of four clock cycles of the clock signal. In this case, bubbles 250-1 to 250-4 occur in the middle of the write data.

Referring to FIG. 6C, tCCDL = 4 and tCCDS = 1 and 3 may be designated to eliminate the bubble. However, in this case, data is interleaved between different bank groups, so it is difficult to use, and there is an overhead in which the user stores and regroups the previous data for use of the interleaved data.

7 is a timing diagram during a read operation according to an embodiment of the present invention.

2, 3, and 7, the write / read controller 171 in the first bank group controller 170 generates the first internal command CMD_A_i based on the command CMD. The internal command CMD_A_i includes two commands RD A and RD A 'which overlap the operation RD A of the command CMD, and further includes a mux enable MUX_EN command. The mux enable MUX_EN command may be periodically applied as long as two clock cycles of the clock signal CLK. The write / read control unit 171 generates the first multiplexer control signal EN_A based on the mux enable MUX_EN command and outputs the first multiplexer control signal EN_A to the multiplexer 195.

Meanwhile, the write / read controller in the second bank group controller 180 may also operate in the same manner as the write / read controller 171 in the first bank group controller 170 to control the second internal command CMD_B_i and the second multiplexer control signal ( EN_B).

According to the first internal command CMD_A_i and the second internal command CMD_B_i, data is read from the first bank group 131 and the second bank group 133. Each read data SA_A and SA_B is input to the multiplexer 195 through the write / read circuit 140.

The multiplexer 195 sequentially outputs read data SA_A and SA_B according to the multiplexer control signals EN_A and EN_B. The multiplexer 195 selects the rear half of the first access data 310 of the first read data SA_A and the front half of the second access data 320 according to the first multiplexer control signal EN_A. . The lengths of the portions selected from the first access data 310 and the second access data 320 are the same. The multiplexer 195 selects data from the second read data SA_B in the same manner to generate the selection data MUX_OUT and output the selected data MUX_OUT to the input / output circuit 160. Therefore, each data included in the selection data MUX_OUT has the same length of time and can be continuously connected without a gap between the data.

8 is a timing diagram during a read operation according to another embodiment of the present invention.

4 and 8, the third latch 191 is controlled by the first bank group controller 170 and the second bank group controller 180, so that the first access data of the read data SA_A and SA_B is read. Delay data SA_A 'and SA_B' having been delayed 310 are generated and output to the multiplexer 195. In this case, the length of delay of the first access data 310 is equal to the length of the second access data 320. In FIG. 8, delay data SA_A 'and SA_B' delaying the first access data 310 are illustrated. However, the second access data 320 may be delayed.

The multiplexer control signals EN_A and EN_B are synchronized with the read data SA_A and SA_B. The multiplexer 195 outputs, to the input / output circuit 160, the selection data MUX_OUT which sequentially selects delay data SA_A 'and SA_B' according to the multiplexer control signals EN_A and EN_B. Therefore, since the lengths of the selected portions of the first access data 310 and the second access data 320 are the same, each data included in the selection data MUX_OUT has the same length of time.

9 is a timing diagram showing a conventional read operation in which the burst length is 4 and the core accesses twice. 9A shows the case where there is no bank group (non BG), where tCCD = 2. 9B illustrates a case where a bank group is used and tCCD = 4. 9C shows a case where tCCDL = 4 and tCCDS = 1, 3 using a bank group.

In each of FIGS. 9A, 9B, and 9C, the same problem as that in the case of FIGS. 6A, 6B, and 6C relating to the write operation also occurs in the read operation.

That is, referring to FIG. 9A, the core access speed cannot be reduced by not using a bank group.

Referring to FIG. 9B, when changing from tCCD = 2 to 4 using the bank group, the read command CMD may be input at intervals of four clock cycles of the clock signal. In this case, bubbles 250-1 to 250-4 are generated in the middle of the read data.

Referring to FIG. 9C, tCCDL = 4 and tCCDS = 1 and 3 may be set to eliminate the bubbles 250-1 to 250-4. However, in this case, data is interleaved between different bank groups, so it is difficult to use, and there is an overhead in which the user stores and regroups the previous data for use of the interleaved data.

According to the present invention, since the above problem does not occur, the speed of the memory device is improved.

10A illustrates a layout showing a write path according to an embodiment of the present invention.

2 and 10A, the data input / output unit 160 of the memory device 100a may receive write data from each of the plurality of input / output terminals 160-1 and 160-2.

The memory cell array 130 may include a plurality of bank groups 131, 133, 135, and 137 corresponding to the input / output terminals 160-1 and 160-2. In FIG. 10A, the first bank group 131 and the second bank group 133 correspond to the first input / output terminal 160-1, and the third bank group 135 and the fourth bank group 137 are formed of the first bank group 131 and the second bank group 133. 2 corresponds to the input / output terminal 160-2. Since the configurations of the first bank group 131 and the second bank group 133 are the same as those of the third bank group 135 and the fourth bank group 137, the first bank group 131 and the second bank will be described below. Only the group 133 will be described.

Each bank group 131 and 133 may include a plurality of memory blocks 1311 to 1317 and 1331 to 1335. For example, the first bank group 131 may include a plurality of memory blocks 1311, 1313, 1315, and 1317.

The write / read circuit 140 may include a plurality of sub write / read circuits 140-1 to 140-4. Each sub write / read circuit 140-1 to 140-4 may be disposed between each of the memory blocks 1311 to 1317 and 1331 to 1335.

Second latches 175-1 and 175-2 for each bank group may be disposed between the sub-write / read circuits 140-1 to 140-4 in each bank group 131 and 133. First latches 173-1 and 173-2 for each bank group may be disposed between the second latches 175-1 and 175-2 in each bank group 131 and 133. The first latches 173-1 and 173-2 for each bank group may be connected to the input / output terminal 160-1.

The write data received by the input / output terminal 160-1 continues in succession through the first latches 173-1 and 173-2 and the second latches 175-1 and 175-2 for each bank group, and has the same length of time. The memory blocks 1311 to 1317 and 1331 to 1337 in the bank groups 131 and 133 are written to be adjusted.

10B illustrates a layout showing a read path according to an embodiment of the present invention. The layout of the memory device 100b of FIG. 10B is identical to the memory device 100a of FIG. 10A except for a part thereof, and therefore, the differences will be mainly described.

2 and 10B, when the bank groups 131, 133, 135, and 137 have four bank groups, the multiplexer 195 sequentially reads the read data of the first bank group 131 and the second bank group 133. The first multiplexer 195-1 and the read data of the third bank group 135 and the fourth bank group 137, which are output to the first input / output terminal 160-1, are sequentially input to the second input / output terminal 160-1. And a second multiplexer 195-2 output to 2).

The first multiplexer 195-1 selects one of the read data of each of the sub-write / read circuits 140-1 to 140-4 in each bank group 131 and 133. And a second mux 199-1 for selecting one of the read data selected from each first mux and outputting the selected mux to the first input / output terminal 160-1.

The second mux 199-1 may operate in the same manner as in FIG. 7 or FIG. 8 described above, so that the output data has the same length of time and can be continuously connected without a gap between the data.

In FIG. 10A and FIG. 10B, for convenience of explanation, the components that operate during the write operation and the read operation are shown in separate diagrams, respectively. However, in the case where separate configurations are respectively shown at the corresponding positions of FIGS. 10A and 10B, the layout may be configured by arranging all of the configurations at the positions.

For example, the position of the second latch 175-1 of FIG. 10A corresponds to the first mux 197-1 of FIG. 10B, in which the second latch 175-1 and the first mux 197-1 are positioned. ) You can place them all.

FIG. 11 illustrates an embodiment of a computer system including the semiconductor memory device shown in FIG. 1.

Referring to FIG. 11, a computer system 400 including the semiconductor memory device 100 shown in FIG. 1 may be a cellular phone, a smart phone, a personal digital assistant, or wireless communication. It may be implemented as a device.

The computer system 400 includes a semiconductor memory device 100 and a memory controller 420 that can control operations of the semiconductor memory device 100. The memory controller 420 may control a data access operation of the semiconductor memory device 100, for example, a write operation or a read operation, under the control of the host 410.

Data of the semiconductor memory device 100 may be displayed through the display 430 under the control of the host 410 and the memory controller 420. The radio transceiver 440 may transmit or receive a radio signal through the antenna ANT. For example, the radio transceiver 440 may convert a radio signal received through the antenna ANT into a signal that can be processed by the host 410. Accordingly, the host 410 may process a signal output from the wireless transceiver 440 and transmit the processed signal to the memory controller 420 or the display 430. The memory controller 420 may store a signal processed by the host 410 in the semiconductor memory device 100.

In addition, the wireless transceiver 440 may convert a signal output from the host 410 into a wireless signal and output the changed wireless signal to an external device through the antenna ANT. The input device 450 is a device capable of inputting a control signal for controlling the operation of the host 410 or data to be processed by the host 410. The input device 450 may include a touch pad and a computer mouse. The same may be implemented with a pointing device, a keypad, or a keyboard.

The host 410 may display the data output from the memory controller 420, the data output from the wireless transceiver 440, or the data output from the input device 450 through the display 430. Can control the operation of.

According to an embodiment, the memory controller 420 capable of controlling the operation of the semiconductor memory device 100 may be implemented as part of the host 410 and may be implemented as a chip separate from the host 410.

12 illustrates another embodiment of a computer system including the semiconductor memory device shown in FIG. 1.

Referring to FIG. 12, a computer system 400 including the semiconductor memory device 100 illustrated in FIG. 1 may include a personal computer, a network server, a tablet PC, and a net-book. It may be implemented as a book, an e-reader, a personal digital assistant, a portable multimedia player, a MP3 player, or an MP4 player.

The computer system 500 may include a memory controller 520, a display 530, and an input device 540 that may control data processing operations of the host 510, the semiconductor memory device 100, and the semiconductor memory device 100. Include.

The host 510 may display data stored in the memory device 420 on the display 440 according to data input through the input device 450. For example, the input device 450 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard. The host 510 may control the overall operation of the computer system 500 and may control the operation of the memory controller 520.

According to an embodiment, the memory controller 520 capable of controlling the operation of the semiconductor memory device 100 may be implemented as part of the host 510 or may be implemented as a chip separate from the host 510.

FIG. 13 illustrates another embodiment of a computer system including the semiconductor memory device shown in FIG. 1.

Referring to FIG. 13, a computer system 600 including the semiconductor memory device 100 illustrated in FIG. 1 may be an image processing device, such as a digital camera or a mobile phone or a smartphone to which a digital camera is attached. Can be implemented.

The computer system 600 includes a memory controller 620 that can control data processing operations such as a write operation or a read operation of the host 610, the semiconductor memory device 100, and the semiconductor memory device 100. The computer system 600 further includes an image sensor 630 and a display 640.

The image sensor 630 of the computer system 600 converts the optical image into digital signals, and the converted digital signals are sent to the host 610 or the memory controller 620. Under the control of the host 610, the converted digital signals may be displayed through the display 640 or stored in the semiconductor memory device 100 through the memory controller 620.

In addition, the data stored in the semiconductor memory device 100 is displayed through the display 640 under the control of the host 610 or the memory controller 620.

According to an embodiment, the memory controller 620 that can control the operation of the semiconductor memory device 100 may be implemented as part of the host 610 or may be implemented as a separate chip from the host 610.

FIG. 14 illustrates another embodiment of a computer system including the semiconductor memory device shown in FIG. 1.

Referring to FIG. 14, the computer system 700 including the semiconductor memory device 100 illustrated in FIG. 1 may be implemented by a host computer 810 and a memory card or a smart card. Can be. Computer system 700 includes a host computer 710 and a memory card 730.

The host computer 710 includes a host 740 and a host interface 720. The memory card 730 includes a semiconductor memory device 100, a memory controller 750, and a card interface 760. The memory controller 750 may control the exchange of data between the semiconductor memory device 100 and the card interface 760.

According to an embodiment, the card interface 760 may be a secure digital (SD) card interface or a multi-media card (MMC) interface, but is not limited thereto.

When the memory card 730 is mounted in the host computer 710, the card interface 760 may interface data exchange between the host 740 and the memory controller 750 according to the protocol of the host 740.

According to an embodiment, the card interface 760 may support Universal Serial Bus (USB) protocol and InterChip (USB) -USB protocol. Here, the card interface may mean hardware capable of supporting a protocol used by the host computer 710, software mounted on the hardware, or a signal transmission scheme.

When computer system 700 is connected with a host interface 720 of a host computer 710 such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box, The host interface 720 may perform data communication with the semiconductor memory device 100 through the card interface 760 and the memory controller 750 under the control of the host 740.

Although the preferred embodiments have been illustrated and described above, the invention is not limited to the specific embodiments described above, and does not depart from the gist of the invention as claimed in the claims. Various modifications may be made by the vibrator, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

100: memory device 110: command / address receiving unit
120: command / address decoder 130: memory cell array
131: first bank group 133: second bank group
140: write / read circuit 141: first write / read circuit
143: second write / read circuit 150: input / output data processing unit
160: input and output circuit 170: first bank group control unit
171: Write / read control unit 173: First latch
175: second latch
180: second bank group control unit
191: third latch 195: multiplexer
192: first read latch 193: second read latch
DATA_A: first write data DATA_B: second write data
DATA_A_1: First latch data DATA_A_2: Bank group write data
EN_A: first multiplexer control signal EN_B: second multiplexer control signal
SA_A: first read data SA_B: second read data
2nd_En_A: Latch Control Signal CMD: Command
CMD_A_i: first internal command CMD_B_i: second internal command
MUX_EN: mux enable signal SA_A ', SA_B': delay data
310: first access data 320: second access data
MUX_OUT: selection data

Claims (10)

The burst length is b (b is an integer greater than or equal to 2), k (k is an integer greater than or equal to 2 and less) core accesses per command, and the memory device receives a command. In
A memory cell array including a plurality of bank groups;
A plurality of bank group controllers provided for each bank group and generating a multiplexer control signal for selecting some of read data of a corresponding bank group; And
A multiplexer for sequentially outputting read data of the plurality of bank groups in accordance with the multiplexer control signal received from the plurality of bank group controllers,
Each data included in the output data of the multiplexer is
Have the same length of time,
The delay time between access to one bank group of the plurality of bank groups and next access to the one bank group is four clock cycles, access to the one bank group and the one A memory device wherein the delay between a bank group and access to another bank group is two clock cycles. The method of claim 1,
The read data,
First read data by the first core access and second read data by the second core access,
The multiplexer
And at least a portion adjacent to the second read data among the data sequences of the first read data and at least a portion adjacent to the first read data among the data sequences of the second read data according to the multiplexer control signal. The method of claim 1, wherein the multiplexer control signal is
Synchronized with the read data,
The memory device is
And a third latch configured to output delay data, which delays read data by a first access, from the read data to the multiplexer. The method of claim 1,
b = k * n,
N is the number of the bank group. The memory device of claim 4, wherein the memory device
Further comprising a mode register,
The mode register is
And setting the value of n. delete The memory device of claim 1, wherein the memory device
Receive the command and memory write data,
The plurality of bank group controllers
Receiving data corresponding to a corresponding bank group among the memory write data, and generating bank group write data adjusted such that each data included in the received data is continuously connected and has the same time space, And a memory device for outputting to the corresponding bank group. Burst length is b (b is an integer greater than or equal to 2), k (k is an integer greater than or equal to 2 or less) core accesses per command (CMD), and command and memory writes ( A memory device for receiving data)
A memory cell array including a plurality of bank groups; And
Each bank group is provided, and receives data corresponding to a corresponding bank group among the memory write data, and adjusts each data included in the received data to be continuous and have the same time space. A plurality of bank group controllers for generating bank group write data and outputting the bank group write data to the corresponding bank group;
The delay time between access to one bank group of the plurality of bank groups and next access to the one bank group is four clock cycles, access to the one bank group and the one A memory device wherein the delay between a bank group and access to another bank group is two clock cycles. The method of claim 8, wherein each bank group control unit is
Selecting a command corresponding to a corresponding bank group among the commands, overlapping the number of core accesses to generate an internal command of the corresponding bank group, and generating a latch control signal including a pulse corresponding to an operation command of the internal command. Memory device including a control signal generation unit to. The method of claim 9, wherein each bank group control unit
A first latch for latching the received data and outputting a gap between the received data and removing the gap; And
And a second latch configured to latch output data of the first latch according to the latch control signal to generate bank group write data in which each data included in the output data has the same length of time.

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