KR102061873B1 - Liquid Crystal Display Device and Manufacturing Method the same - Google Patents

Abstract

The present invention is a lower substrate; A gate electrode formed on the lower substrate, a first insulating film formed on the gate electrode, an oxide layer formed on the first insulating film, a channel region portion and an oxide layer formed on the oxide layer and positioned in an island shape in a central region of the oxide layer. A thin film transistor including an etch stopper including a source drain region portion separated into one side and the other side, and a source electrode and a drain electrode formed on the etch stopper of the peripheral portion separated into one side and the other side of the oxide layer; A second insulating film formed on the thin film transistor and exposing one side of the oxide layer, a portion of the source electrode, and the other side of the oxide layer and a portion of the drain electrode; A third insulating layer formed on the second insulating layer and exposing one side of the oxide layer, a portion of the source electrode, the other side of the oxide layer, and a portion of the drain electrode; And a first transparent electrode formed on the third insulating layer and electrically connected to one side of the oxide layer and a part of the source electrode, and a second separated electrode from the first transparent electrode and electrically connected to the other side of the oxide layer and a part of the drain electrode. A liquid crystal display device including a transparent electrode having a transparent electrode is provided.

Description

Liquid Crystal Display Device and Manufacturing Method the Same

The present invention relates to a liquid crystal display device and a manufacturing method thereof.

With the development of information technology, the market for a display device, which is a connection medium between a user and information, is growing. Accordingly, flat panel displays (FPDs) such as liquid crystal displays (LCDs), organic light emitting diodes (OLEDs), and plasma display panels (PDPs) may be used. Usage is increasing.

Among the flat panel display devices described above, a liquid crystal display device capable of realizing high resolution and miniaturization as well as a large size is widely used. The liquid crystal display displays an image by emitting light incident from the backlight unit by adjusting the arrangement direction of the liquid crystal layer by an electric field applied to the pixel electrode and the common electrode included in the liquid crystal display panel. The liquid crystal display device is manufactured by being divided into various driving methods according to the structure of the thin film transistor, the pixel electrode, and the common electrode included in the liquid crystal display panel.

On the other hand, when manufacturing a liquid crystal display device based on the oxide thin film transistor, there is a problem that the oxide located under the wet during the wet etching the source drain metal. In order to prevent the problem of damaging the oxide, a method of using an etch stopper has been conventionally proposed. However, the conventionally proposed method has caused an increase in the mask process (approximately 6 mask processes were required) by applying the etch stopper. In addition, the conventionally proposed method has difficulty in implementing a channel length of 10 μm or less due to an increase in the length of the etch stopper.

The present invention for solving the above problems of the background technology and the liquid crystal display device that can reduce the mask process compared to the conventional while using an etch stopper by changing the contact structure between the oxide layer, the source electrode and the drain electrode constituting the thin film transistor; It is to provide a preparation method thereof.

The present invention as a means for solving the above problems the lower substrate; A gate electrode formed on the lower substrate, a first insulating film formed on the gate electrode, an oxide layer formed on the first insulating film, a channel region portion and an oxide layer formed on the oxide layer and positioned in an island shape in a central region of the oxide layer. A thin film transistor including an etch stopper including a source drain region portion separated into one side and the other side, and a source electrode and a drain electrode formed on the etch stopper of the peripheral portion separated into one side and the other side of the oxide layer; A second insulating film formed on the thin film transistor and exposing one side of the oxide layer, a portion of the source electrode, and the other side of the oxide layer and a portion of the drain electrode; A third insulating layer formed on the second insulating layer and exposing one side of the oxide layer, a portion of the source electrode, the other side of the oxide layer, and a portion of the drain electrode; And a first transparent electrode formed on the third insulating layer and electrically connected to one side of the oxide layer and a part of the source electrode, and a second separated electrode from the first transparent electrode and electrically connected to the other side of the oxide layer and a part of the drain electrode. A liquid crystal display device including a transparent electrode having a transparent electrode is provided.

The transparent electrode includes a third transparent electrode spaced apart from the second transparent electrode on the transmission region, the second transparent electrode is defined as a pixel electrode, the third transparent electrode is defined as a common electrode, the pixel electrode and the common electrode Can be non-overlapping.

The second transparent electrode may be defined as a pixel electrode, and a common electrode forming an electric field with the pixel electrode may be formed on the upper substrate bonded to the lower substrate.

In another aspect, the present invention provides a gate electrode formed on a lower substrate, a first insulating film formed on the gate electrode, an oxide layer formed on the first insulating film, a channel formed on the oxide layer and positioned in an island shape in a central region of the oxide layer. A thin film transistor including an etch stopper including a region portion and a source drain region portion separated into one side and the other side of the oxide layer, and a source electrode and a drain electrode formed on the etch stopper of the peripheral portion separated into one side and the other side of the oxide layer. Forming; Forming a second insulating layer and a third insulating layer formed on the thin film transistor and exposing one side of the oxide layer, a portion of the source electrode, and the other side of the oxide layer and a portion of the drain electrode; And a first transparent electrode formed on the third insulating layer and electrically connected to one side of the oxide layer and a part of the source electrode, and a second separated electrode from the first transparent electrode and electrically connected to the other side of the oxide layer and a part of the drain electrode. It provides a method for manufacturing a liquid crystal display device comprising the step of forming a transparent electrode having a transparent electrode.

The transparent electrode includes a third transparent electrode spaced apart from the second transparent electrode on the transmission region, the second transparent electrode is defined as a pixel electrode, the third transparent electrode is defined as a common electrode, the pixel electrode and the common electrode Can be non-overlapping.

The second transparent electrode may be defined as a pixel electrode, and a common electrode forming an electric field with the pixel electrode may be formed on the upper substrate bonded to the lower substrate.

The forming of the thin film transistor may include defining a thin film transistor region including a channel region, a data line region, and a transmission region on a lower substrate, and forming a gate metal, a first insulating layer, an oxide layer, and a first photoresist on the lower substrate. Sequentially forming the first photoresist to align the first mask on the lower substrate and to form an island shape on the thin film transistor region, and using the first photoresist to form a gate metal, a first insulating film, Forming an oxide layer in an island shape, sequentially forming an etch stopper, a source drain metal, and a second photoresist on the lower substrate so as to cover the oxide layer, and aligning the second mask on the lower substrate; The second photoresist is exposed and developed, and the source drain metal is referenced to the channel region using the second photoresist. Separated, and may include the step of forming a source electrode and a drain electrode.

The forming of the second insulating film and the third insulating film may include sequentially forming a second insulating film, a third insulating film, and a third photoresist on the lower substrate so as to cover the source electrode and the drain electrode; Aligning the mask, exposing and developing the third photoresist, and forming an island-shaped structure in the center of the channel region using the third photoresist, and simultaneously forming an oxide layer, a source electrode, and a side of the island-shaped structure. Exposing a portion of the drain electrode.

The forming of the transparent electrode may include sequentially forming the transparent electrode and the fourth photoresist on the lower substrate to cover the third insulating layer, aligning the fourth mask on the lower substrate, and exposing the fourth photoresist. Developing and separating the transparent electrode using the fourth photoresist.

The separating of the transparent electrode may include a first transparent electrode electrically connecting one side of the oxide layer exposed through the source region and the source electrode, and a second electrode electrically connecting the drain electrode and the other side of the exposed oxide layer through the drain region. The transparent electrode may be separated to be divided into a third transparent electrode spaced apart from the second transparent electrode on the transparent electrode and the transmission region.

According to the present invention, the liquid crystal display device can be manufactured in a four mask process using an etch stopper by changing the contact structure between the oxide layer, the source electrode, and the drain electrode constituting the thin film transistor. In addition, the present invention has the effect of manufacturing a liquid crystal display device that can freely change the channel length using a mask even if the length of the etch stopper increases. In addition, the present invention has the effect of manufacturing a liquid crystal display device that can improve the performance of the device based on the oxide thin film transistor.

1 is a block diagram schematically showing a liquid crystal display device;
FIG. 2 is a circuit diagram schematically illustrating a subpixel illustrated in FIG. 1. FIG.
3 is a plan view of a sub pixel according to an embodiment of the present invention;
4 through 15 are process flow diagrams based on the cross-sectional structure of the region A1-A2 shown in FIG.
16 is a plan view of the thin film transistor region shown in FIG. 15;
17 is a plan view of a sub pixel according to the second embodiment of the present invention;
18 through 29 are process flow diagrams based on the cross-sectional structure of the region A1-A2 shown in FIG.

Hereinafter, with reference to the accompanying drawings, the specific content for the practice of the present invention will be described.

First Embodiment

FIG. 1 is a block diagram schematically illustrating a liquid crystal display, and FIG. 2 is a circuit diagram schematically illustrating a subpixel illustrated in FIG. 1.

As shown in FIG. 1 and FIG. 2, the LCD includes a timing controller 130, a gate driver 140, a data driver 150, a liquid crystal panel 160, and a backlight unit 170.

The timing controller 130 receives the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal Data Enable, DE, the clock signal CLK, and the data signal DATA from the outside. The timing controller 130 controls the operation timing of the data driver 150 and the gate driver 140 using timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. Since the timing controller 130 may determine the frame period by counting the data enable signal of one horizontal period, the vertical synchronization signal and the horizontal synchronization signal supplied from the outside may be omitted.

The control signals generated by the timing controller 130 include a gate timing control signal GDC for controlling the operation timing of the gate driver 140 and a data timing control signal DDC for controlling the operation timing of the data driver 150. ) May be included. The gate timing control signal GDC includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (Gate Output Enable, GOE), and the like. The gate start pulse GSP is supplied to a gate drive integrated circuit (IC) where the first gate signal is generated.

The gate shift clock GSC is a clock signal commonly input to the gate drive ICs and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs. The data timing control signal DDC includes a source start pulse (Source, Start Pulse, SSP), a source sampling clock (SSC), a source output enable signal (Source Output Enable, SOE), and the like. The timing controller 130 supplies the data signal DATA to the data driver 150 together with the data timing control signal DDC.

The gate driver 140 outputs the gate signal while shifting the level of the gate voltage in response to the gate timing control signal GDC supplied from the timing controller 130. The gate driver 140 supplies a gate signal to the liquid crystal panel 160 through the gate lines GL. The gate driver 140 may be formed in an IC form or may be formed in a gate in panel method in the liquid crystal panel 160.

The data driver 150 samples, latches, and converts the data signal DATA to a gamma reference voltage in response to the data timing control signal DDC supplied from the timing controller 130. The data driver 150 supplies the data signal DATA to the liquid crystal panel 160 through the data lines DL. The data driver 150 is formed in the form of an IC.

The liquid crystal panel 160 includes a lower substrate on which a thin film transistor and the like are formed, an upper substrate on which a color filter and the like are formed, and a liquid crystal layer disposed therebetween. An alignment layer for setting a pre-tilt angle of the liquid crystal is formed in the lower substrate and the inner upper layer of the lower substrate. The lower polarizer is attached to the lower surface of the lower substrate, and the upper polarizer is attached to the upper surface of the upper substrate. In addition, the liquid crystal panel 160 may be implemented in any form such as a transmissive liquid crystal display, a transflective liquid crystal display, and a reflective liquid crystal display.

The liquid crystal panel 160 displays an image corresponding to the gate signal supplied from the gate driver 140 and the data signal DATA supplied from the data driver 150. The liquid crystal panel 160 includes sub pixels for controlling light provided through the backlight unit 170. One subpixel SP includes a thin film transistor TFT, a storage capacitor Cst, and a liquid crystal layer Clc.

The gate electrode of the thin film transistor TFT is connected to the gate line GL1 and the source electrode is connected to the data line DL1. One end of the storage capacitor Cst is connected to the drain electrode of the thin film transistor TFT and the other end thereof is connected to the common voltage line Vcom. The liquid crystal layer Clc is formed between the pixel electrode 1 connected to the drain electrode of the thin film transistor TFT and the common electrodes 2 and Vcom.

The backlight unit 170 provides light to the liquid crystal panel 160. The backlight unit 170 includes a light emitting diode (hereinafter referred to as an LED), an LED driver for driving an LED, a light guide plate for converting light emitted from the LED into a surface light source, an optical sheet for condensing and diffusing light emitted from the light guide plate, and the like. . The backlight unit 170 may provide light to the liquid crystal panel 160 by using not only an LED but also other light sources.

Hereinafter, the present invention will be described with reference to the subpixels formed in the liquid crystal panel 160.

3 is a plan view of a subpixel according to an exemplary embodiment of the present invention.

As shown in FIG. 3, the subpixel according to the first embodiment of the present invention is implemented in an in plane switching (IPS) mode or a fringe field switching (FFS) mode. The subpixel is defined by the first data line DL1 arranged in the vertical direction y and the first gate line GL1 arranged in the horizontal direction x. As illustrated, the first data line DL1 has an inequality (<) shape inclined with respect to the center area of the subpixel.

The subpixel has a thin film transistor TFT connected to the first data line DL1 and the first gate line GL1. The semiconductor layer of the thin film transistor TFT is made of oxide. The subpixel has a pixel electrode Pixel connected to the drain electrode of the thin film transistor TFT and a common electrode Vcom connected to the common voltage line.

As illustrated, the pixel electrode Pixel and the common electrode Vcom have a finger having an inequality (<) shape inclined with respect to the center area of the subpixel. The pixel electrode Pixel and the common electrode Vcom are formed on the lower substrate. Finger parts of the pixel electrode Pixel and the common electrode Vcom are formed on the same layer in the transmission area TA of the subpixel. Finger parts of the pixel electrode Pixel and the common electrode Vcom are spaced apart from each other so as to be non-overlapping in the transmission area TA of the subpixel.

In the above description and illustrated drawings, the first data line DL1, the pixel electrode Pixel, and the common electrode Vcom have an inclined slope similar to an inequality (<) shape. However, this is just one example. The first data line DL1, the pixel electrode Pixel, and the common electrode Vcom may have a straight line shape.

On the other hand, the liquid crystal display of the transverse electric field mode based on the oxide thin film transistor has an advantage of high resolution charging because the current mobility is 10 times higher than that of the amorphous silicon (a-Si) thin film transistor. However, in the case of the oxide semiconductor layer, since there is no etching selectivity with the metal layer, the oxide semiconductor layer is removed when exposed to the etchant or the molecular structure is damaged, thereby degrading the characteristics of the thin film transistor. In order to improve this, the conventionally proposed method uses an etch stopper to prevent a problem of damaging an oxide disposed under the wet drain metal during wet etching. However, the conventionally proposed method has caused an increase in the mask process (approximately 6 mask processes were required) by using the etch stopper. In addition, the conventionally proposed method has difficulty in implementing a channel length of 10 μm or less due to an increase in the length of the etch stopper due to the margin between the oxide layer, the source electrode, and the drain electrode.

In order to solve the above problems, the first embodiment of the present invention provides a structure and method for reducing the mask process while using an etch stopper and improving the performance of the device by implementing a channel length of 10 μm or less. Suggest together.

Hereinafter, a first embodiment of the present invention will be described based on the cross-sectional structure of the region A1-A2 shown in FIG. 3.

4 through 15 are process flowcharts based on the cross-sectional structure of the region A1-A2 shown in FIG. 3, and FIG. 16 is a plan view of the thin film transistor region illustrated in FIG. 15.

[First Mask Process: See FIG. 3, FIG. 4 to FIG. 8]

The thin film transistor region TFTA including the channel region CHA, the data line region DA, and the transmission region TA are respectively defined on the lower substrate 110, and the gate metal 111 is formed on the lower substrate 110. ). Gate metal 111 is one or an alloy thereof selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and copper (Cu) It may be, and may be formed of a single layer or multiple layers.

The first insulating layer 112, the oxide layer 113, and the first photoresist PR1 are sequentially stacked on the gate metal 111. The insulating film 112 is selected from a silicon oxide film (SiOx), a silicon nitride film (SiNx), or the like.

The first mask M1 is aligned, exposed to light, and developed on the lower substrate 110. The first mask M1 is selected as a halftone mask. The first mask M1 has a blocking portion NOPN corresponding to the channel region CHA positioned in the center region of the thin film transistor region TFTA, and has a transflective portion HOPN around the data line region DA. ) And a permeation | transmission part FOPN corresponding to the permeation | transmission area | region TA are used. When the first mask M1 is removed and the first photoresist PR1 is developed, the channel region CHA positioned in the center region of the thin film transistor region TFTA has a shape protruding from the peripheral region.

The gate metal 111 is formed by etching the lower substrate 110 using the first photoresist PR1 and located in the remaining data line area DA and the transmission area TA except for the thin film transistor area TFTA. 1 The insulating film 112 and the oxide layer 113 are removed. As a result, only the portion corresponding to the thin film transistor region TFTA is present in the gate metal 111, the first insulating layer 112, and the oxide layer 113. The gate metal 111 present in the portion corresponding to the thin film transistor region TFTA becomes the gate electrode of the thin film transistor.

The first photoresist PR1 is ashed to lower the level (height) of the first photoresist PR1. When the first photoresist PR1 is ashed, only the channel region CHA positioned in the center region of the thin film transistor region TFTA exists and the peripheral region of the thin film transistor region TFTA corresponding to the rest is removed.

The oxide layer 113 is patterned by using the first photoresist PR1 remaining in the channel region CHA positioned in the center region of the thin film transistor region TFTA, and the first photoresist PR1 is removed. As a result, the oxide layer 113 is present only in the channel region CHA positioned in the center region of the thin film transistor region TFTA. Thereafter, the remaining first photoresist PR1 is removed.

[Second mask process: see FIGS. 3, 9-11]

An etch stopper 114, an source drain metal 115, and a second photoresist PR2 are sequentially stacked on the entire surface of the lower substrate 110 to cover the oxide layer 113. The source drain metal 115 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and copper (Cu). It may be an alloy, and may be formed of a single layer or multiple layers.

The second mask M2 is aligned, exposed to light, and developed on the lower substrate 110. The second mask M2 is selected as the photo mask. The second mask M2 has a transmissive portion OPN corresponding to a region narrower than the channel region CHA positioned in the central region of the thin film transistor region TFTA and blocks the data line region DA. And having a transmissive part OPN corresponding to a part of the transmissive area TA. When the lower substrate 110 is etched using the second photoresist PR2, the source drain metal 115 is separated into the source electrode 115a and the drain electrode 115b. Thereafter, the remaining second photoresist PR2 is removed.

[Third Mask Process: See FIGS. 3, 12, and 13]

The second insulating film 116, the third insulating film 117, and the third photoresist PR3 are sequentially stacked on the entire surface of the lower substrate 110 to cover the source electrode 115a and the drain electrode 115b. do. The second insulating film 116 is selected from a silicon oxide film (SiOx), a silicon nitride film (SiNx), or the like. Unlike the second insulating layer 116, the third insulating layer 117 is selected as a material for planarizing a surface, for example, an organic layer such as polyacrylate (Pac).

The third mask M3 is aligned, exposed to light, and developed on the lower substrate 110. The third mask M3 is selected as a photo mask. The third mask M3 has a blocking portion NOPN corresponding to a region narrower than the channel region CHA positioned in the center region of the thin film transistor region TFTA and is adjacent to the channel region CHA and is adjacent to the source electrode 115a. And a transmission part OPN corresponding to the drain electrode 115b and a blocking part NOPN blocking the remaining area of the data line area DA and the transmission area TA.

When the second and third insulating layers 116 and 117 are etched using the third photoresist PR3, a portion of the source electrode 115a is disposed in the third insulating layer 117 adjacent to one side of the channel region CHA. A drain region DA exposing a portion of the drain electrode 115b and d is formed adjacent to the other side of the exposed source region SA and the channel region CHA. The source area SA and the drain area DA become contact holes. In this case, portions of one side and the other side of the oxide layer 113 positioned in the channel region CHA are also exposed through the source region SA and the drain region DA, respectively. For this reason, the etch stoppers 114a, 114b, 114c are respectively separated corresponding to the source area SA, the channel area CHA, and the drain area DA. Here, the etch stoppers 114b positioned on the center region of the channel region CHA are present in an island shape, and the etch stoppers 114a and 114c separated from the etch stoppers 114a and 114c are present on the front surface of the lower substrate 110. Thereafter, the remaining third photoresist PR3 is removed.

[Fourth Mask Process: See FIGS. 3, 14, and 15]

The transparent electrode 118 and the fourth photoresist PR4 are sequentially stacked on the entire surface of the lower substrate 110 including the source area SA, the channel area CHA, and the drain area DA. In this case, a part of the transparent electrode 118 is formed to fill a space (contact hole) formed in the source area SA and the drain area DA. The transparent electrode 118 has transparency such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO) or graphene (graphene). It is chosen as the front curtain. The transparent electrode 118 becomes the pixel electrode Pixel and the common electrode Vcom as shown in FIG. 3 through a subsequent process.

The fourth mask M4 is aligned, exposed to light, and developed on the lower substrate 110. The fourth mask M4 is selected as the photo mask. The fourth mask M4 has a blocking portion NOPN corresponding to the thin film transistor region TFTA, but has a transmissive portion OPN corresponding to the center region of the channel region CHA, and a transmissive portion corresponding to the transmissive region TA. Alternating between OPN and NOPN is used.

When the transparent electrode 118 is etched using the fourth photoresist PR4, the transparent electrode 118 is mutually formed on the source region SA, the channel region CHA, the drain region DA, and the transmission region TA. Are separated. The first transparent electrode 118a positioned on the source area SA electrically connects the source electrode 115a and one side of the oxide layer 113. The second and third transparent electrodes 118a and 118b disposed on the channel region CHA are divided into a source electrode 115a portion and a drain electrode 115b portion. The second transparent electrode 118b disposed on the drain region DA electrically connects the drain electrode 115b and the other side of the oxide layer 113.

One of the second and third transparent electrodes 118b and 118c positioned on the transmission area TA becomes the pixel electrodes 118b and Pixel electrically connected to the drain electrode 115b, and the other one is connected to the common voltage line. Electrically connected common electrodes 118c and Vcom are used. That is, the second and third transparent electrodes 118b and 118c positioned on the transmission area TA become the finger parts of the pixel electrode 118b and the common electrode 118c. Thereafter, the remaining fourth photoresist PR4 is removed.

On the other hand, in the structure described above, the channel length CL is made larger than the channel region CHA by placing an island-shaped structure in the channel region CHA and patterning the periphery (source and drain regions) as shown in FIG. 16. It can be formed short. As a result, according to the first embodiment of the present invention, the channel length CL may be implemented up to 6 μm or less depending on the structure of the mask.

Second Embodiment

17 is a plan view of a sub pixel according to the second embodiment of the present invention.

As shown in FIG. 17, the subpixel according to the second embodiment of the present invention is implemented in a twisted nematic (TN) mode. The subpixel is defined by the first data line DL1 arranged in the vertical direction y and the first gate line GL1 arranged in the horizontal direction x. The first data line DL1 has a shape that is wired in a straight line.

The subpixel has a thin film transistor TFT connected to the first data line DL1 and the first gate line GL1. The semiconductor layer of the thin film transistor TFT is made of oxide. The subpixel has a pixel electrode Pixel connected to the drain electrode of the thin film transistor TFT and a common electrode Vcom connected to the common voltage line.

The pixel electrode Pixel is formed in a plate shape on the lower substrate to be positioned in the transmission area TA of the subpixel, while the common electrode Vcom is formed in a plate shape on the entire surface of the upper substrate. Here, the common electrode Vcom is referred to as showing a part of it on a plane to show its shape.

On the other hand, the liquid crystal display of the transverse electric field mode based on the oxide thin film transistor has an advantage of high resolution charging because the current mobility is 10 times higher than that of the amorphous silicon (a-Si) thin film transistor. However, the conventionally proposed method has caused an increase in the mask process (approximately 6 mask processes were required) due to the problem of damaging the oxide located under the wet drain metal during wet etching or the use of an etch stopper. . In addition, the conventionally proposed method has difficulty in implementing a channel length of 10 μm or less due to an increase in the length of the etch stopper.

In order to solve the above problems, the second embodiment of the present invention provides a structure and method for reducing the mask process while using an etch stopper and improving the performance of the device by implementing a channel length of 10 μm or less. Suggest together.

Hereinafter, a second embodiment of the present invention will be described based on the cross-sectional structure of the region A1-A2 shown in FIG. However, the common electrode Vcom used in the TN mode is formed on the upper substrate, and its structure and a method of forming the same correspond to techniques for the main pipe, and thus detailed description thereof will be omitted.

18 to 29 are process flowcharts based on the cross-sectional structure of the region A1-A2 shown in FIG. 17.

[First Mask Process: See Figs. 17, 18-22]

The thin film transistor region TFTA including the channel region CHA, the data line region DA, and the transmission region TA are respectively defined on the lower substrate 110, and the gate metal 111 is formed on the lower substrate 110. ). Gate metal 111 is one or an alloy thereof selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and copper (Cu) It may be, and may be formed of a single layer or multiple layers.

The first insulating layer 112, the oxide layer 113, and the first photoresist PR1 are sequentially stacked on the gate metal 111. The insulating film 112 is selected from a silicon oxide film (SiOx), a silicon nitride film (SiNx), or the like.

The first mask M1 is aligned, exposed to light, and developed on the lower substrate 110. The first mask M1 is selected as a halftone mask. The first mask M1 has a blocking portion NOPN corresponding to the channel region CHA positioned in the center region of the thin film transistor region TFTA, and has a transflective portion HOPN around the data line region DA. ) And a permeation | transmission part FOPN corresponding to the permeation | transmission area | region TA are used. When the first mask M1 is removed and the first photoresist PR1 is developed, the channel region CHA positioned in the center region of the thin film transistor region TFTA has a shape protruding from the peripheral region.

The gate metal 111 is formed by etching the lower substrate 110 using the first photoresist PR1 and located in the remaining data line area DA and the transmission area TA except for the thin film transistor area TFTA. 1 The insulating film 112 and the oxide layer 113 are removed. As a result, only the portion corresponding to the thin film transistor region TFTA is present in the gate metal 111, the first insulating layer 112, and the oxide layer 113. The gate metal 111 present in the portion corresponding to the thin film transistor region TFTA becomes the gate electrode of the thin film transistor.

The first photoresist PR1 is ashed to lower the level (height) of the first photoresist PR1. When the first photoresist PR1 is ashed, only the channel region CHA positioned in the center region of the thin film transistor region TFTA exists and the peripheral region of the thin film transistor region TFTA corresponding to the rest is removed.

The oxide layer 113 is patterned by using the first photoresist PR1 remaining in the channel region CHA positioned in the center region of the thin film transistor region TFTA, and the first photoresist PR1 is removed. As a result, the oxide layer 113 is present only in the channel region CHA positioned in the center region of the thin film transistor region TFTA. Thereafter, the remaining first photoresist PR1 is removed.

[Second mask process: see Figs. 17, 23-25]

An etch stopper 114, an source drain metal 115, and a second photoresist PR2 are sequentially stacked on the entire surface of the lower substrate 110 to cover the oxide layer 113. The source drain metal 115 is one selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and copper (Cu). It may be an alloy, and may be formed of a single layer or multiple layers.

The second mask M2 is aligned, exposed to light, and developed on the lower substrate 110. The second mask M2 is selected as the photo mask. The second mask M2 has a transmissive portion OPN corresponding to a region narrower than the channel region CHA positioned in the central region of the thin film transistor region TFTA and blocks the data line region DA. And having a transmissive part OPN corresponding to a part of the transmissive area TA. When the lower substrate 110 is etched using the second photoresist PR2, the source drain metal 115 is separated into the source electrode 115a and the drain electrode 115b. Thereafter, the remaining second photoresist PR2 is removed.

[Third Mask Process: See FIGS. 17, 26 and 27]

The second insulating film 116, the third insulating film 117, and the third photoresist PR3 are sequentially stacked on the entire surface of the lower substrate 110 to cover the source electrode 115a and the drain electrode 115b. do. The second insulating film 116 is selected from a silicon oxide film (SiOx), a silicon nitride film (SiNx), or the like. Unlike the second insulating layer 116, the third insulating layer 117 is selected as a material for planarizing a surface, for example, an organic layer such as polyacrylate (Pac).

The third mask M3 is aligned, exposed to light, and developed on the lower substrate 110. The third mask M3 is selected as a photo mask. The third mask M3 has a blocking portion NOPN corresponding to a region narrower than the channel region CHA positioned in the center region of the thin film transistor region TFTA and is adjacent to the channel region CHA and is adjacent to the source electrode 115a. And a transmission part OPN corresponding to the drain electrode 115b and a blocking part NOPN blocking the remaining area of the data line area DA and the transmission area TA.

When the second and third insulating layers 116 and 117 are etched using the third photoresist PR3, a portion of the source electrode 115a is disposed in the third insulating layer 117 adjacent to one side of the channel region CHA. A drain region DA exposing a part of the drain electrode 115b is formed adjacent to the other side of the source region SA and the channel region CHA. The source area SA and the drain area DA become contact holes. In this case, portions of one side and the other side of the oxide layer 113 positioned in the channel region CHA are also exposed through the source region SA and the drain region DA, respectively. For this reason, the etch stoppers 114a, 114b, and 114c are respectively separated corresponding to the source region SA, the channel region CHA, and the drain region DA. Here, the etch stoppers 114b positioned on the center region of the channel region CHA are present in an island shape, and the etch stoppers 114a and 114c separated from the etch stoppers 114a and 114c are present on the front surface of the lower substrate 110. Thereafter, the remaining third photoresist PR3 is removed.

[Fourth Mask Process: See FIGS. 17, 28, and 29]

The transparent electrode 118 and the fourth photoresist PR4 are sequentially stacked on the entire surface of the lower substrate 110 including the source area SA, the channel area CHA, and the drain area DA. In this case, a part of the transparent electrode 118 is formed to fill a space (contact hole) formed in the source area SA and the drain area DA. The transparent electrode 118 has transparency such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO) or graphene (graphene). It is chosen as the front curtain. The transparent electrode 118 becomes the pixel electrode Pixel and the common electrode Vcom as shown in FIG. 17 through a subsequent process.

The fourth mask M4 is aligned, exposed to light, and developed on the lower substrate 110. The fourth mask M4 is selected as the photo mask. The fourth mask M4 has a blocking portion NOPN corresponding to the thin film transistor region TFTA and the transmissive region TA and a transmissive portion OPN corresponding to the data line region DA.

When the transparent electrode 118 is etched using the fourth photoresist PR4, the transparent electrode 118 is separated from each other on the source region SA and the channel region CHA. The first transparent electrode 118a positioned on the source area SA electrically connects the source electrode 115a and one side of the oxide layer 113. The first and second transparent electrodes 118a and 118b disposed on the channel region CHA are divided into a source electrode 115a portion and a drain electrode 115b portion. The second transparent electrode 118b disposed on the drain region DA electrically connects the drain electrode 115b and the other side of the oxide layer 113. The second transparent electrode 118b positioned on the transmission area TA becomes the pixel electrode 118b electrically connected to the drain electrode 115b. Thereafter, the remaining fourth photoresist PR4 is removed.

As described above, the present invention can manufacture a liquid crystal display by changing the contact structure between the oxide layer, the source electrode, and the drain electrode constituting the thin film transistor while using an etch stopper (four mask processes compared to conventional methods). It can be effective. In addition, the present invention has the effect of manufacturing a liquid crystal display device that can freely change the channel length using a mask even if the length of the etch stopper increases. In addition, the present invention has the effect of manufacturing a liquid crystal display device that can improve the performance of the device based on the oxide thin film transistor.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art without changing the technical spirit or essential features of the present invention. It will be appreciated that it may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. In addition, all changes or modifications derived from the meaning and scope of the claims and equivalent concepts should be construed as being included in the scope of the present invention.

130: timing controller 140: gate driver
150: data driver 160: liquid crystal panel
170: backlight unit 110: lower substrate
DA: data line area CHA: channel area
TFTA: thin film transistor region TA: transmission region
113: oxide layer Pixel, 1, 118b: pixel electrode
Vcom, 2, 118c: common electrodes M1 to M4: first to fourth masks
PR1 to PR4: first to fourth photoresist

Claims (12)

Lower substrate;
A gate electrode formed on the lower substrate, a first insulating film formed on the gate electrode, an oxide layer formed on the first insulating film, a channel region formed on the oxide layer and positioned in an island shape in a central region of the oxide layer A thin film transistor including an etch stopper including a portion and a source drain region portion separated from one side and the other side of the oxide layer, and a source electrode and a drain electrode formed on an etch stopper of a peripheral portion separated from one side and the other side of the oxide layer. ;
A second insulating layer formed on the thin film transistor and exposing one side of the oxide layer, a portion of the source electrode, another side of the oxide layer, and a portion of the drain electrode;
A third insulating layer formed on the second insulating layer and exposing one side of the oxide layer, a portion of the source electrode, the other side of the oxide layer, and a portion of the drain electrode; And
A first transparent electrode formed on the third insulating layer and electrically connected to one side of the oxide layer and a portion of the source electrode, and separated from the first transparent electrode, and electrically connecting the other side of the oxide layer and a part of the drain electrode; Including a transparent electrode having a second transparent electrode connected to,
And the oxide layer is formed to protrude in a pattern smaller than that of the gate electrode and the first insulating layer.
The method of claim 1,
The transparent electrode
A third transparent electrode spaced apart from the second transparent electrode on the transmission region and separated;
And the second transparent electrode is defined as a pixel electrode, the third transparent electrode is defined as a common electrode, and the pixel electrode and the common electrode are non-overlapping.
The method of claim 1,
And the second transparent electrode is defined as a pixel electrode, and a common electrode forming an electric field with the pixel electrode is formed on an upper substrate bonded to the lower substrate.
A gate electrode formed on a lower substrate, a first insulating film formed on the gate electrode, an oxide layer formed on the first insulating film, and a channel region portion formed on the oxide layer and positioned in an island shape in a central region of the oxide layer. And an etch stopper including a source drain region portion separated into one side and the other side of the oxide layer, and a thin film transistor including a source electrode and a drain electrode formed on an etch stopper of a peripheral portion separated into one side and the other side of the oxide layer. Forming;
Forming a second insulating layer and a third insulating layer formed on the thin film transistor and exposing one side of the oxide layer, a portion of the source electrode, another side of the oxide layer, and a portion of the drain electrode; And
A first transparent electrode formed on the third insulating layer and electrically connected to one side of the oxide layer and a portion of the source electrode, and separated from the first transparent electrode, and electrically connecting the other side of the oxide layer and a part of the drain electrode; Forming a transparent electrode having a second transparent electrode connected thereto;
And the oxide layer is formed to be protruded to be smaller than the gate electrode and the first insulating layer.
The method of claim 4, wherein
The transparent electrode
A third transparent electrode spaced apart from the second transparent electrode on the transmission region and separated;
And the second transparent electrode is defined as a pixel electrode, the third transparent electrode is defined as a common electrode, and the pixel electrode and the common electrode are non-overlapping.
The method of claim 4, wherein
And the second transparent electrode is defined as a pixel electrode, and a common electrode forming an electric field with the pixel electrode is formed on an upper substrate bonded to the lower substrate.
The method of claim 4, wherein
Forming the thin film transistor is
A thin film transistor region, a data line region, and a transmission region including channel regions are respectively defined on the lower substrate, and a gate metal, the first insulating layer, the oxide layer, and a first photoresist are sequentially formed on the lower substrate. To do that,
The first photoresist is exposed and developed to align a first mask on the lower substrate and have an island shape on the thin film transistor region, and the gate metal, the first insulating layer, and the oxide using the first photoresist. Forming the layer into an island shape,
Sequentially forming an etch stopper, a source drain metal, and a second photoresist on the lower substrate to cover the oxide layer;
Aligning the second mask on the lower substrate, exposing and developing the second photoresist, and separating the source drain metal based on the channel region using the second photoresist, wherein the source electrode and the drain electrode Method of manufacturing a liquid crystal display device comprising the step of forming a.
The method of claim 7, wherein
Forming the second insulating film and the third insulating film is
Sequentially forming the second insulating film, the third insulating film, and a third photoresist on the lower substrate to cover the source electrode and the drain electrode;
Aligning a third mask on the lower substrate, exposing and developing the third photoresist, and forming an island-shaped structure in the center of the channel region using the third photoresist, and at the same time, the island-shaped structure And exposing a portion of the oxide layer, the source electrode, and the drain electrode to one side and the other side of the liquid crystal display device.
The method of claim 8,
Forming the transparent electrode
Sequentially forming the transparent electrode and the fourth photoresist on the lower substrate to cover the third insulating layer;
And aligning a fourth mask on the lower substrate, exposing and developing the fourth photoresist, and separating the transparent electrode by using the fourth photoresist.
The method of claim 9,
Separating the transparent electrode
A first transparent electrode electrically connecting one side of the oxide layer exposed through the source region and the source electrode, and a second transparent electrode electrically connecting the other side of the oxide layer exposed through the drain region and the drain electrode And separating the transparent electrode to be divided into a third transparent electrode spaced apart from the second transparent electrode on the transmission area.
The method of claim 1,
And a channel length of the thin film transistor is shorter than that of the channel region.
The method of claim 1,
And a source drain metal disposed on the channel region of the etch stopper and a third insulating layer disposed on the source drain metal having the same island shape.

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