KR102042530B1 - Thin film transistor array substrate and method of fabricating the same - Google Patents

Abstract

The present invention relates to a thin film transistor array substrate capable of reducing capacitance generated between a vertical gate line and a data line, and a method of manufacturing the same. The thin film transistor array substrate of the present invention includes a horizontal gate line formed on a substrate; Gate electrodes; A gate insulating layer formed on the substrate to cover the horizontal gate line and the gate electrode, the gate insulating layer including a gate contact hole exposing the horizontal gate line; A vertical gate wiring formed on the gate insulating film so as to intersect the semiconductor layer formed on the gate insulating film so as to overlap the gate electrode and the horizontal gate wiring; Source and drain electrodes spaced apart from each other on the semiconductor layer; A first passivation layer formed on the gate insulating layer to expose a portion of the source electrode, the drain electrode and the vertical gate line and the gate contact hole; A pixel electrode formed on the first passivation layer and connected to the drain electrode exposed by the first passivation layer; A gate connection pattern connecting the source connection pattern connected to the source electrode exposed by the first passivation layer and the horizontal gate line exposed through the gate contact hole and the vertical gate line exposed by the first passivation layer to each other. ; And a data line formed on the source connection pattern.

Description

Thin Film Transistor Array Substrate and Method for Manufacturing the Same {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array substrate, and more particularly, to a thin film transistor array substrate capable of reducing capacitance generated between a vertical gate line and a data line and a method of manufacturing the same.

As the information society develops, the demand for display devices is increasing in various forms, and in recent years, liquid crystal display devices (LCDs), plasma display panels (PDPs), electro luminescent displays (ELD), and vacuum fluorescent (VFD) Various flat panel display devices such as displays have been studied, and some of them are already used as display devices in various devices.

Among them, the liquid crystal display device is most used while replacing the CRT (Cathode Ray Tube) for the use of the mobile image display device due to the characteristics and advantages of the excellent image quality, light weight, thinness, and low power consumption. Liquid crystal display devices have been developed in various ways such as monitors of televisions and computers that receive and display broadcast signals in addition to mobile applications such as monitors of notebook computers.

The liquid crystal display includes a color filter array substrate having a color filter, a thin film transistor array substrate having a thin film transistor, and a liquid crystal layer formed between the color filter array substrate and the thin film transistor array substrate.

A plurality of gate lines and data lines intersect each other in the thin film transistor array substrate to define a pixel area. A data driver (Data D-IC) for supplying a data signal to the data line and a gate driver (Gate D-IC) for supplying a scan signal to the gate line are formed.

However, in general, the data driver and the gate driver are formed on the other side of the thin film transistor array substrate. For example, the data driver is provided above the substrate, and the gate driver is provided on the left and right sides of the substrate. Accordingly, the bezel area of the thin film transistor array substrate increases.

Therefore, in order to reduce the bezel area, both the data driver and the gate driver are provided on one side of the thin film transistor array substrate, and the vertical gate wiring in a direction parallel to the data wiring is provided. Then, the vertical gate wiring and the horizontal gate wiring are connected to each other.

Hereinafter, a general thin film transistor array substrate having vertical gate lines will be described with reference to the accompanying drawings.

1 is a cross-sectional view of a typical thin film transistor array substrate having vertical gate wirings.

Referring to FIG. 1, a vertical gate line 11a is formed on a substrate 10, and the horizontal gate line 11 overlaps the vertical gate line 11a with a first gate insulating layer 12a therebetween. At this time, the horizontal gate wiring 11 and the vertical gate wiring 11a are connected to each other through a gate contact hole formed in the first gate insulating film 12a. The gate electrode 11b is defined as a part of the horizontal gate line 11.

The second gate insulating film 12b is formed to cover the horizontal gate wiring 11 and the gate electrode 11b, and the semiconductor layer 13 is formed on the second gate insulating film 12b. The source electrode 14a and the drain electrode 14b are spaced apart from each other on the semiconductor layer 13. The source electrode 14a extends from the data line 14 formed to be parallel to the vertical gate line 11a.

The first passivation film 15a is formed to cover the source electrode 14a and the drain electrode 14b, and the pixel electrode 16 connected to the drain electrode 14b is formed on the first passivation film 15a. The second passivation layer 15b is formed to cover the pixel electrode 16, and the common electrode 17 is formed on the second passivation layer 15b.

By the way, like the area A, the vertical gate line 11a and the data line 114 are overlapped with the second gate insulating film 12b interposed therebetween. In general, since the gate wiring and the data wiring are formed to vertically intersect, signal interference between the thin film transistor array substrate and the general thin film transistor array substrate occurs only in an area where the gate wiring and the data wiring cross each other.

However, as described above, since the vertical gate line 11a is parallel to the data line 114 and formed to overlap the data line 114, the overlapping area is widened, which greatly increases the capacitance. As a result, signal interference between the vertical gate line 11a and the data line is greatly increased, resulting in a significant decrease in signal characteristics of the thin film transistor array substrate.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a thin film transistor array substrate and a method of manufacturing the same may be provided by increasing a distance between the vertical gate line and the data line, thereby minimizing signal interference between the vertical gate line and the data line. To provide, the purpose is.

The thin film transistor array substrate of the present invention for achieving the above object comprises a horizontal gate wiring and a gate electrode formed on the substrate; A gate insulating layer formed on the substrate to cover the horizontal gate line and the gate electrode, the gate insulating layer including a gate contact hole exposing the horizontal gate line; A vertical gate wiring formed on the gate insulating film so as to intersect the semiconductor layer formed on the gate insulating film so as to overlap the gate electrode and the horizontal gate wiring; Source and drain electrodes spaced apart from each other on the semiconductor layer; A first passivation layer formed on the gate insulating layer to expose a portion of the source electrode, the drain electrode and the vertical gate line and the gate contact hole; A pixel electrode formed on the first passivation layer and connected to the drain electrode exposed by the first passivation layer; A gate connection pattern connecting the source connection pattern connected to the source electrode exposed by the first passivation layer and the horizontal gate line exposed through the gate contact hole and the vertical gate line exposed by the first passivation layer to each other. ; And a data line formed on the source connection pattern.

The first passivation layer is formed of an organic insulating material.

The first passivation layer is a photo active compound.

The thickness of the first protective film is 1.5 μm to 2.5 μm.

The data line overlaps the vertical gate line.

A second passivation layer formed on the first passivation layer to cover the pixel electrode, the source connection pattern, and the gate connection pattern; And a common electrode formed on the second passivation layer.

In addition, a method of manufacturing a thin film transistor array substrate for achieving the same object comprises the steps of forming a horizontal gate wiring and a gate electrode on the substrate; Forming a gate insulating layer on the substrate to cover the horizontal gate line and the gate electrode, the gate insulating layer including a gate contact hole exposing the horizontal gate line; Forming a semiconductor layer on the gate insulating layer to overlap the gate electrode; Forming a vertical gate line on the gate insulating layer to cross the horizontal gate line; Forming a source electrode and a drain electrode on the semiconductor layer to be spaced apart from each other; Forming a first passivation layer on the gate insulating layer to expose a portion of the source electrode, the drain electrode and the vertical gate line and the gate contact hole; A pixel electrode connected to the drain electrode exposed by the first passivation layer, a source connection pattern connected to the source electrode exposed by the first passivation layer, and the horizontal gate wiring exposed through the gate contact hole and the first electrode; Forming a gate connection pattern connecting the vertical gate lines exposed by the first passivation layer to each other; And forming a data line on the source connection pattern.

The semiconductor layer, the source electrode, the drain electrode, and the vertical gate wiring are formed using the same mask.

The pixel electrode, the source connection pattern, the gate connection pattern, and the data line are formed using the same mask.

The thin film transistor array substrate and the method of manufacturing the same of the present invention as described above form a data wiring on the first protective film formed to cover the thin film transistor, thereby providing a thick first protective film between the data wiring and the vertical gate wiring. Furthermore, since the first passivation layer is formed of a material having a low dielectric constant, it is possible to prevent the capacitance from increasing between the vertical gate line and the data line. Accordingly, signal interference between the vertical gate line and the data line can be prevented to prevent signal distortion of the thin film transistor.

1 is a cross-sectional view of a typical thin film transistor array substrate having vertical gate wirings.
2A is a plan view of a thin film transistor array substrate of the present invention.
FIG. 2B is a cross-sectional view taken along the line II ′ of FIG. 2A.
3A to 3F are process plan views illustrating a method of manufacturing the thin film transistor array substrate of the present invention.
4A to 4F are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate of the present invention.

Hereinafter, the thin film transistor array substrate of the present invention will be described.

2A is a plan view of a thin film transistor array substrate of the present invention, and FIG. 2B is a cross-sectional view taken along line II ′ of FIG. 2A.

As shown in FIGS. 2A and 2B, the thin film transistor array substrate of the present invention includes a substrate 110, a horizontal gate wiring 111, a vertical gate wiring 111a connected to the horizontal gate wiring 111, a data wiring 114, and the like. The thin film transistor includes a thin film transistor, a first passivation layer 115a, a pixel electrode 116a, a second passivation layer 115b, and a common electrode 117.

The pixel region is defined by the horizontal gate line 111 and the data line 114 crossing each other. In particular, in order to reduce the bezel area, a vertical gate line 111a parallel to the data line 114 and overlapping with the data line 114 is provided, and the vertical gate line 111a and the horizontal gate line 111 are provided. It is connected to each other through the gate connection pattern 116b. Therefore, a gate driver Gate D-IC for supplying a scan signal to the horizontal gate line 111 may be formed above the substrate 110 or may be formed below the substrate 110, like the data driver D-IC. Can be.

In detail, the thin film transistor includes a gate electrode 111b, a gate insulating layer 112, a semiconductor layer 113a, a source electrode 114a, and a drain electrode 114b. In this case, the gate electrode 111b protrudes from the horizontal gate line 111 or is defined as a partial region of the horizontal gate line 111. In the drawing, the gate electrode 111b is defined as a partial region of the horizontal gate line 111.

The gate insulating film 112 is formed to cover the gate electrode 111b. The gate insulating layer 112 is formed of a material such as silicon oxide (SiOx), silicon nitride (SiNx), or the like. In this case, the gate insulating layer 112 may include a gate contact hole formed to expose the horizontal gate line 111.

The semiconductor layer 113a is formed on the gate insulating layer 112 to overlap the gate electrode 111b, and the source electrode 114a and the drain electrode 114b spaced apart from each other are formed on the semiconductor layer 113a. The vertical gate line 111a is formed on the gate insulating film 112. The vertical gate line 111a is formed to cross the horizontal gate line 111 with the gate insulating layer 112 interposed therebetween.

When the semiconductor layer 113a, the vertical gate wiring 111a, the source electrode 114a, and the drain electrode 114b are formed in the same mask process using a halftone mask, a semiconductor pattern (below the vertical gate wiring 111a) is formed. 113b) is further formed.

The first passivation layer 115a is formed on the substrate 110 to cover the vertical gate wiring 111a, the source electrode 114a, and the drain electrode 114b. In this case, the first passivation layer 115a is formed of an organic insulating material, and particularly preferably formed of a material having a low dielectric constant. As described above, the first passivation layer 115a may be a photoactive compound. This is to minimize capacitance caused by overlapping of the vertical gate line 111a and the data line 114. In particular, the thickness of the first protective film 115a is preferably 1.5 µm to 2.5 µm.

As described above, the general thin film transistor array substrate is overlapped with only the gate insulating film having vertical gate wiring and data wiring interposed therebetween. However, in general, the thickness of the gate insulating film is very thin, which is 1 m or less. As a result, the distance between the vertical gate line and the data line becomes closer, and the capacitance increases.

Moreover, since the vertical gate wiring is parallel to the data wiring and formed to overlap with the data wiring, the overlapping area is very large. As a result, signal interference between the vertical gate line and the data line is greatly increased, resulting in a significant decrease in signal characteristics of the thin film transistor array substrate.

However, as shown in Equation 1, the capacitance C generated between the data line 114 and the vertical gate line 111a has a dielectric constant? Of the first passivation layer 115a and the vertical gate line 111a and the data line. It is proportional to the area A where the 114 overlaps, and is inversely proportional to the thickness of the first passivation film 115a, that is, the distance d between the vertical gate line 111a and the data line 114.

Accordingly, the thin film transistor array substrate of the present invention forms the data wiring 114 on the first passivation film 115a, thereby forming a thick first passivation film 115a between the data wiring 114 and the vertical gate wiring 111a. Is provided. In this case, since the first passivation layer 115a is formed of a material having a low dielectric constant, an increase in capacitance between the vertical gate line 111a and the data line 114 can be prevented. Accordingly, signal interference between the vertical gate line and the data line can be prevented to prevent signal distortion of the thin film transistor.

The first passivation layer 115a exposes the gate contact hole formed in the gate insulating layer 112 and simultaneously exposes a portion of the vertical gate line 111a and the source electrode 114a and the drain electrode. And a second contact hole 202H exposing 114b.

The source connection pattern 116c and the pixel electrode 116a are formed of a transparent conductive material on the first passivation layer 115a. Transparent conductive materials include tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). to be.

The source connection pattern 116c is used to connect the source electrode 114a and the data line 114 exposed through the second contact hole 202H to each other, and is formed of a transparent conductive material. The data line 114 is formed on the source connection pattern 116c to overlap the vertical gate line 111a. Therefore, the data line 114 and the source electrode 114a are connected through the source connection pattern 116c. In addition, a pixel electrode 116a connected to the drain electrode 114b exposed through the second contact hole 202H is formed on the second passivation layer 115a. The pixel electrode 116a is formed in the form of a cylindrical electrode.

The gate connection pattern 116b is formed of the same material as the source connection pattern 116c and the pixel electrode 116a. The gate connection pattern 116b connects the vertical gate line 111a exposed through the first contact hole 201H and the horizontal gate line 111 exposed through the gate contact hole formed in the gate insulating layer 112. That is, the vertical gate line 111a and the horizontal gate line 111 provided on the different layers have the gate connection pattern 116b connected to each other, and the scan signal of the vertical gate line 111a is passed through the gate connection pattern 116b. Is transferred to the horizontal gate wiring 111.

The second passivation layer 115b is formed on the data line 114 to cover the entire surface of the substrate 110. The second passivation layer 115b is formed of an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or the like. The common electrode 117 is formed on the second passivation film 115b. The common electrode 117 is formed on the entire surface of the substrate 110 and has a plurality of slits exposing the second passivation layer 115b. The common electrode 117 as described above overlaps the pixel electrode 116a with the second passivation layer 115b therebetween to generate a fringe electric field.

That is, the thin film transistor array substrate of the present invention includes a data line 114 on the first passivation layer 115a, and a source electrode formed on the same layer as the vertical gate line 111a via the source connection pattern 116c ( 114a) and the data wiring 114 are connected to each other. That is, the first passivation layer 115a is formed of a material having a low dielectric constant between the vertical gate line 111a and the data line 114 to increase the capacitance between the vertical gate line 111a and the data line 114. It can prevent.

Hereinafter, a method of manufacturing a thin film transistor array substrate according to the present invention will be described in detail.

3A to 3F are process plan views illustrating the method of manufacturing the thin film transistor array substrate of the present invention, and FIGS. 4A to 4F are process cross-sectional views illustrating the method of manufacturing the thin film transistor array substrate of the present invention.

3A and 4A, the horizontal gate wiring 111 and the gate electrode 111b are formed on the substrate 110. In this case, the gate electrode 111b protrudes from the horizontal gate line 111 or is defined as a partial region of the horizontal gate line 111. The horizontal gate line 111 and the gate electrode 111b are formed of an opaque conductive material. Opaque conductive materials are Mo, Ti, Cu, AlNd, Al, Cr, Mo alloys, Cu alloys, Al alloys, and the like.

3B and 4B, the gate insulating layer 112 is formed on the substrate 110 to cover the horizontal gate line 111 and the gate electrode 111b. The gate insulating layer 112 is formed of an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or the like. In this case, the gate insulating layer 112 is formed to have a gate contact hole 112H exposing a portion of the horizontal gate line 111 to connect the vertical gate line and the horizontal gate line 111 to be described later.

3C and 4C, the semiconductor layer 113a, the source electrode 114a, the drain electrode 114b, and the vertical gate line 111a are formed on the gate insulating layer 112. In the drawing, the semiconductor layer 113a, the source electrode 114a, the drain electrode 114b, and the vertical gate wiring 111a are formed by the same mask process using a halftone mask. The vertical gate line 111a, the source electrode 114a, and the drain electrode 114b are formed of the opaque conductive material described above.

Specifically, the semiconductor layer 113a is formed on the gate insulating film 112 so as to overlap the gate electrode 111b, and the source electrode 114a and the drain electrode 114b are formed on the semiconductor layer 113a, and Spacing is formed. The vertical gate line 111a is formed to intersect with the horizontal gate line 111 and the gate insulating layer 112 therebetween. In particular, since the semiconductor layer 113a and the vertical gate line 111a are formed in the same mask process as described above, the semiconductor pattern 113b is formed under the vertical gate line 111a by the same material as the semiconductor layer 113a. do.

When the semiconductor layer 113a, the source electrode 114a, the drain electrode 114b and the vertical gate line 111a are formed using different masks, the semiconductor pattern 113b is provided under the vertical gate line 111a. It doesn't work.

3D and 4D, after the first passivation layer 115a is formed on the gate insulating layer 112 to cover the vertical gate wiring 111a, the source electrode 114a, and the drain electrode 114b, the first protective film 115a is formed. The first protective film 115a is selectively removed to form the first contact hole 201H and the second contact hole 202H.

The first contact hole 201H exposes the gate contact hole 200H formed in the gate insulating layer 112, and simultaneously exposes a portion of the vertical gate line 111a. The second contact hole 202H exposes the source electrode 114a and the drain electrode 114b.

In this case, the first passivation layer 115a is formed of an organic insulating material, and particularly preferably formed of a material having a low dielectric constant. As described above, the first passivation layer 115a may be a photoactive compound. This is to minimize capacitance caused by overlapping the vertical gate line 111a and the data line 114. In particular, the thickness of the first protective film 115a is preferably 1.5 µm to 2.5 µm.

3E and 4E, a transparent conductive material and an opaque conductive material are sequentially formed on the first passivation layer 115a. The opaque conductive material is patterned to form the data line 114, and the transparent conductive material is patterned to form the pixel electrode 116a, the gate connection pattern 116b, and the source connection pattern 116c. At this time, it is preferable to use a halftone mask.

Specifically, a transparent conductive material and an opaque conductive material are sequentially formed on the first passivation layer 115a. Transparent conductive materials include tin oxide (TO), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). to be. And the opaque conductive material is Mo, Ti, Cu, AlNd, Al, Cr, Mo alloy, Cu alloy, Al alloy and the like.

Then, the first photoresist pattern is formed on the opaque conductive material by using a halftone mask. The first photoresist pattern is formed to correspond only to a region where the pixel electrode 116a, the gate connection pattern 116b, and the source connection pattern 116c are to be formed. In particular, in order to form a data line with an opaque conductive material on a portion of the source connection pattern 116c, the thickness of the first photoresist pattern of the region for forming the data line 114 is formed to be thicker than the thickness of the remaining regions. It is desirable to.

Then, the exposed opaque conductive material and the transparent conductive material are removed using the first photoresist pattern as a mask. Next, the first photoresist pattern is ashed to form a second photoresist pattern remaining only in the region where the data line 114 is to be formed. The exposed opaque conductive material is removed using the second photoresist pattern as a mask to form the pixel electrode 116a, the gate connection pattern 116b, and the source connection pattern 116c made of only a transparent conductive material. The second photoresist pattern is removed to form the data line 114 on the source connection pattern 116c.

In detail, the pixel electrode 116a is connected to the drain electrode 114b exposed through the second contact hole 202H, and is formed in the form of a cylindrical electrode. The source connection pattern 116c is also connected to the source electrode 114a exposed through the second contact hole 202H, and the data signal of the data line 114 formed on the source connection pattern 116c is the source connection pattern. It is applied to the source electrode 114a via 116c. In addition, the gate connection pattern 116b connects the vertical gate wiring 111a exposed through the first contact hole 201H and the horizontal gate wiring 111 exposed by the gate contact hole 200H.

3F and 4F, a second passivation layer 115b is formed on the first passivation layer 115a to cover the pixel electrode 116a, the gate connection pattern 116b, and the source connection pattern 116c. In this case, the second passivation layer 115b is formed of an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or the like.

The common electrode 117 is formed on the second passivation film 115b. The common electrode 117 is formed on the entire surface of the substrate 110 and has a plurality of slits exposing the second passivation layer 115b. The common electrode 117 as described above overlaps the pixel electrode 116a with the second passivation layer 115b therebetween to generate a fringe electric field.

That is, the thin film transistor array substrate and the method of manufacturing the same of the present invention as described above form the data line 114 on the first passivation layer 115a formed to cover the thin film transistor, thereby forming the data line 114 and the vertical gate line ( A thick first protective film 115a is provided between the 111a layers. Furthermore, since the first passivation layer 115a is formed of a material having a low dielectric constant, an increase in capacitance between the vertical gate line 111a and the data line 114 can be prevented. Accordingly, signal interference between the vertical gate line and the data line can be prevented to prevent signal distortion of the thin film transistor.

On the other hand, the present invention described above is not limited to the above-described embodiment and the accompanying drawings, it is possible that various substitutions, modifications and changes within the scope without departing from the technical spirit of the present invention It will be apparent to those of ordinary skill in Esau.

110: substrate 111: horizontal gate wiring
111a: vertical gate wiring 111b: gate electrode
112: gate insulating film 113a: semiconductor layer
113b: semiconductor pattern 114: data wiring
114a: source electrode 114b: drain electrode
115a: first protective film 115b: second protective film
116a: pixel electrode 116b: gate connection pattern
116c: source connection pattern 117: common electrode
200H: gate contact hole 201H: first contact hole
202H: second contact hole

Claims (14)

A horizontal gate wiring and a gate electrode formed on the substrate;
A gate insulating layer formed on the substrate to cover the horizontal gate line and the gate electrode, the gate insulating layer including a gate contact hole exposing the horizontal gate line;
A vertical gate wiring formed on the gate insulating film so as to intersect the semiconductor layer formed on the gate insulating film so as to overlap the gate electrode and the horizontal gate wiring;
Source and drain electrodes spaced apart from each other on the semiconductor layer;
A first passivation layer formed on the gate insulating layer to expose a portion of the source electrode, the drain electrode and the vertical gate line and the gate contact hole;
A pixel electrode formed on the first passivation layer and connected to the drain electrode exposed by the first passivation layer;
A gate connection pattern connecting the source connection pattern connected to the source electrode exposed by the first passivation layer and the horizontal gate line exposed through the gate contact hole and the vertical gate line exposed by the first passivation layer to each other. ; And
And a data line formed on the source connection pattern. The method of claim 1,
The thin film transistor array substrate of claim 1, wherein the first passivation layer is formed of an organic insulating material. The method of claim 2,
The thin film transistor array substrate of claim 1, wherein the first passivation layer is a photo active compound. The method of claim 1,
The thickness of the first passivation layer is a thin film transistor array substrate, characterized in that 1.5㎛ to 2.5㎛. The method of claim 1,
And the data line overlaps the vertical gate line. The method of claim 1,
A second passivation layer formed on the first passivation layer to cover the pixel electrode, the source connection pattern, and the gate connection pattern; And
The thin film transistor array substrate of claim 2, further comprising a common electrode formed on the second passivation layer. Forming a horizontal gate wiring and a gate electrode on the substrate;
Forming a gate insulating layer on the substrate to cover the horizontal gate line and the gate electrode, the gate insulating layer including a gate contact hole exposing the horizontal gate line;
Forming a semiconductor layer on the gate insulating layer to overlap the gate electrode;
Forming a vertical gate line on the gate insulating layer to cross the horizontal gate line;
Forming a source electrode and a drain electrode on the semiconductor layer to be spaced apart from each other;
Forming a first passivation layer on the gate insulating layer to expose a portion of the source electrode, the drain electrode and the vertical gate line and the gate contact hole;
A pixel electrode connected to the drain electrode exposed by the first passivation layer, a source connection pattern connected to the source electrode exposed by the first passivation layer, and the horizontal gate wiring exposed through the gate contact hole and the first electrode; Forming a gate connection pattern connecting the vertical gate lines exposed by the first passivation layer to each other; And
And forming a data line on the source connection pattern. The method of claim 7, wherein
The first passivation layer is formed of an organic insulating material. The method of claim 8,
The first passivation layer is a photoactive compound, characterized in that the manufacturing method of the thin film transistor array substrate. The method of claim 7, wherein
The thickness of the first passivation layer is a method of manufacturing a thin film transistor array substrate, characterized in that 1.5㎛ to 2.5㎛. The method of claim 7, wherein
And the semiconductor layer, the source electrode, the drain electrode, and the vertical gate line are formed using the same mask. The method of claim 7, wherein
The pixel electrode, the source connection pattern, the gate connection pattern and the data line are formed using the same mask. The method of claim 7, wherein
And the data line is formed to overlap the vertical gate line. The method of claim 7, wherein
After forming a data line on the source connection pattern,
Forming a second passivation layer on the first passivation layer to cover the pixel electrode, the source connection pattern, and the gate connection pattern; And
And forming a common electrode on the second passivation layer.

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