KR102031365B1 - Scan Driver and Display Device Using the same - Google Patents

Abstract

The invention provides a level shifter for outputting start signals, clock signals, and reset signals; And a shift register configured to shift and output the scan signal in response to the start signals, the clock signals, and the reset signals, wherein the Nth stages of the stages receive the Nth clock signal in response to the potential of the Q node. It is generated at the output terminal of the Nth stage by using the pull-up transistor which outputs to the output terminal of the Nth stage, the Q node charging / discharging unit which charges and discharges the Q node, and the Nth potential and its clock signal which is its clock signal. Provided is a scan driver including a ripple remover for removing the ripple.

Description

Scan driver and display device using the same {Scan Driver and Display Device Using the same}

The present invention relates to a scan driver and a display device using the same.

With the development of information technology, the market for a display device, which is a connection medium between a user and information, is growing. Accordingly, the use of display devices such as organic light emitting display (OLED), liquid crystal display (LCD), plasma display panel (PDP), and the like is increasing.

Some of the aforementioned display devices, for example, a liquid crystal display or an organic light emitting display device, include a display panel including a plurality of subpixels arranged in a matrix form and a driving unit for driving the display panel. The driver includes a scan driver for supplying a scan signal (or gate signal) to the display panel and a data driver for supplying a data signal to the display panel.

When the display device is supplied with a scan signal and a data signal to subpixels arranged in a matrix form, the display device emits light so that an image can be displayed. The scan driver outputting the scan signal is classified into an external circuit mounted on an external substrate of the display panel in an integrated circuit form and an embedded type formed in the display panel in the form of a gate in panel formed through a thin film transistor process.

The built-in scan driver is made of amorphous silicon, an oxide thin film transistor, or the like. In the case of the oxide thin film transistor, the current transfer characteristics are superior to that of the amorphous silicon thin film transistor, thereby reducing the circuit size. However, the oxide thin film transistor has a disadvantage in that the threshold voltage recovery characteristic due to the stress bias is lower than that of the amorphous silicon thin film transistor.

However, the embedded scan driver composed of an oxide thin film transistor or an amorphous silicon thin film transistor is treated as the same problem to stabilize the Q node and the scan low voltage in order to increase the reliability and life of the circuit.

The present invention for solving the above problems of the background art is to stabilize the Q node and the scan low voltage to increase the lifetime and reliability of the shift register embedded in the GIP method.

The present invention provides a level shifter for outputting start signals, clock signals, and reset signals. And a shift register configured to shift and output the scan signal in response to the start signals, the clock signals, and the reset signals, wherein the Nth stages of the stages receive the Nth clock signal in response to the potential of the Q node. It is generated at the output terminal of the Nth stage by using the pull-up transistor which outputs to the output terminal of the Nth stage, the Q node charging / discharging unit which charges and discharges the Q node, and the Nth potential and its clock signal which is its clock signal. Provided is a scan driver including a ripple remover for removing the ripple.

The ripple removing unit may remove the ripple generated at the output terminal of the Nth stage when the potential of the Q node is discharged and the Nth clock signal is logic high.

The ripple removing unit may electrically connect the output terminal of the Nth stage and the low potential voltage terminal supplied with the low potential voltage to remove the ripple generated at the output terminal of the Nth stage.

The ripple removing unit outputs the N-th clock signal when the potential of the Q node is discharged, and outputs the N-th clock signal when the potential of the Q node is charged, and the N-clock output from the first circuit portion. In response to the signal may include a second circuit portion for removing the ripple generated at the output terminal of the N-th stage as the N-th clock signal.

The first circuit unit includes a first compensation transistor in which a gate electrode and a first electrode are commonly connected to an Nth clock signal line to which an Nth clock signal is supplied, and a second electrode is connected to a first node, and a gate electrode is connected to a Q node. And a second compensation transistor having a first electrode connected to the first node, a second electrode connected to the low potential voltage terminal, a gate electrode connected to the first node, and a first electrode connected to the Nth clock signal line. The circuit part may include a third compensation transistor connected to a second electrode.

The second circuit unit may include a fourth compensation transistor having a gate electrode connected to a second electrode of the third compensation transistor, a first electrode connected to an output terminal of the Nth stage, and a second electrode connected to a low potential voltage terminal. .

In another aspect, the present invention is a display panel; A data driver connected to data lines of the display panel; And a shift register connected to the scan lines of the display panel and configured to shift and output the scan signal in response to the start signals, the clock signals, and the reset signals. A pull-up transistor for outputting the N-th clock signal to the output terminal of the N-th stage corresponding to the potential, a Q-node charging and discharging unit for charging and discharging the Q-node, a potential of the Q-node, and an N-clock signal as its clock signal The present invention provides a display device including a ripple removing unit for removing ripples generated at an output terminal of an Nth stage.

When the potential of the Q node is discharged and the Nth clock signal is logic high, the ripple removing unit electrically connects the output terminal of the Nth stage and the low potential voltage terminal supplied with the low potential voltage to the output terminal of the Nth stage. Ripple generated in the can be eliminated.

The ripple removing unit outputs the N-th clock signal when the potential of the Q node is discharged, and outputs the N-th clock signal when the potential of the Q node is charged, and the N-clock output from the first circuit portion. In response to the signal may include a second circuit portion for removing the ripple generated at the output terminal of the N-th stage as the N-th clock signal.

The first circuit unit includes a first compensation transistor in which a gate electrode and a first electrode are commonly connected to an Nth clock signal line to which an Nth clock signal is supplied, and a second electrode is connected to a first node, and a gate electrode is connected to a Q node. And a second compensation transistor having a first electrode connected to the first node, a second electrode connected to the low potential voltage terminal, a gate electrode connected to the first node, and a first electrode connected to the Nth clock signal line. The circuit part may include a third compensation transistor connected to a second electrode.

The second circuit unit may include a fourth compensation transistor having a gate electrode connected to a second electrode of the third compensation transistor, a first electrode connected to an output terminal of the Nth stage, and a second electrode connected to a low potential voltage terminal. .

The present invention has an effect of increasing the lifetime and reliability of the shift register embedded in the GIP method by improving or eliminating the ripple generated in the output terminal of its stage every time its clock signal is input. In addition, the present invention can remove the noise, such as ripple and stabilize the Q node and the scan low voltage, it is possible to improve the life and reliability when implementing the shift resistor in the oxide thin film transistor or amorphous silicon thin film transistor.

1 is a schematic block diagram of a display device;
FIG. 2 is a diagram illustrating a configuration of a subpixel illustrated in FIG. 1. FIG.
3 is a block configuration diagram for each stage of a shift register according to an experimental example.
4 is an exemplary circuit configuration of a stage according to an experimental example.
5 is an exemplary waveform diagram illustrating signals and output signals supplied to a stage according to an experimental example.
6 is a block configuration diagram for each stage of the shift register according to the embodiment;
7 is a schematic circuit diagram illustrating a stage according to an embodiment.
8 illustrates a detailed circuit configuration of a stage according to an embodiment.
9 is an exemplary waveform diagram illustrating signals and output signals supplied to a stage according to an exemplary embodiment.
Fig. 10 is a graph comparing and evaluating the ripple levels of scan signals output from shift registers of the experimental example and the example.

Hereinafter, with reference to the accompanying drawings, the specific content for the practice of the present invention will be described.

FIG. 1 is a schematic block diagram of a display device, and FIG. 2 is a diagram illustrating a configuration of a subpixel illustrated in FIG. 1.

As shown in FIG. 1, the display device includes a display panel 100, a timing controller 110, a data driver 120, and scan drivers 130 and 140.

The display panel 10 includes subpixels separated from and connected to the data lines DL and the scan lines GL. The display panel 10 includes a display area 100A in which subpixels are formed and a non-display area 100B in which various signal lines or pads are formed outside the display area 100A. The display panel 100 may be implemented as a liquid crystal display (LCD), an organic light emitting display (OLED), an electrophoretic display (EPD), or the like.

As shown in FIG. 2, one sub-pixel SP is supplied in response to a scan signal supplied through the switching transistor SW and the switching transistor SW connected to the scan line GL1 and the data line DL1. Pixel circuit PC that operates in response to the data signal DATA is included. The subpixel SP is implemented as a liquid crystal display panel including a liquid crystal element or an organic light emitting display panel including an organic light emitting element according to the configuration of the pixel circuit PC.

When the display panel 100 is configured as a liquid crystal display panel, it is a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in plane switching (IPS) mode, a fringe field switching (FFS) mode, or an electrically controlled wired fringefringence (ECB). Implemented in mode. When the display panel 100 is configured as an organic light emitting display panel, the display panel 100 may be implemented in a top-emission method, a bottom-emission method, or a dual-emission method.

The timing controller 110 receives a timing signal such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a dot clock through an LVDS or TMDS interface receiving circuit connected to the image board. The timing controller 110 generates timing control signals for controlling operation timings of the data driver 120 and the scan drivers 130 and 140 based on the input timing signal.

The data driver 120 includes a plurality of source drive integrated circuits (ICs). The source drive ICs receive the digital video data RGB and the source timing control signal DDC from the timing controller 110. The source drive ICs convert the digital video data RGB into a gamma voltage in response to the source timing control signal DDC to generate a data voltage, and transmit the data voltage through the data lines DL of the display panel 100. Supply. The source drive ICs are connected to the data lines DL of the display panel 100 by a chip on glass (COG) process or a tape automated bonding (TAB) process.

The scan driver 130, 140 includes a level shifter 130 and a shift register 140. The scan drivers 130 and 140 are formed by a gate in panel (GIP) method in which the level shifter 130 and the shift register 140 are divided. The level shifter 130 is formed on an external substrate connected to the display panel 100 in the form of an IC.

The level shifter 130 shifts the levels of the clock signals clk, the reset signals, and the start signals vst under the control of the timing controller 11 and supplies the shift register 140 to the shift register 140. The shift register 140 is formed in the form of a thin film transistor in the non-display area 100B positioned on the left and right sides of the display area 100A of the display panel 100 by the GIP method. The shift register 140 includes stages for shifting and outputting a scan signal in response to clock signals clk, reset signals, and start signals vst. Stages included in the shift register 140 sequentially output scan signals through output terminals.

Meanwhile, the shift register 140 may be formed of an oxide thin film transistor or an amorphous silicon thin film transistor. The oxide thin film transistor has an advantage in that the current can be reduced in size compared to the amorphous silicon thin film transistor, thereby reducing the circuit size. However, the oxide thin film transistor has a disadvantage in that the threshold voltage recovery characteristic due to the stress bias is lower than that of the amorphous silicon thin film transistor. This is because in the case of amorphous silicon thin film transistors, the threshold voltage is kept constant over time (clamping voltage saturation), but in the case of oxide thin film transistors, the threshold voltage is continuously shifted in the positive direction over time. (Clamping Voltage Not Saturation).

The present invention proposes a method of removing noise such as ripple and stabilizing the Q node and the scan low voltage in order to increase the lifetime and reliability of the shift register 140 embedded in the GIP method. According to this method, when the shift register 140 is implemented as an oxide thin film transistor or an amorphous silicon thin film transistor, lifespan and reliability may be improved.

Hereinafter, the shift register of the GIP type which can improve the lifetime and reliability in comparison with the experimental example and the embodiment will be described.

Experimental Example

3 is a block diagram illustrating stages of a shift register according to an experimental example, FIG. 4 is an exemplary circuit diagram illustrating a circuit configuration of a stage according to an experimental example, and FIG. 5 illustrates signals and output signals supplied to a stage according to an experimental example. This is an example of waveforms.

As shown in FIG. 3, the shift register according to the experimental example includes stages STG1 to STG11. The stages STG1 to STG11 are arranged to be connected in cascade.

Stages STG1 to STG11 are supplied with six phase clock signals, a reset signal, a low potential voltage and a start signal. To this end, the stages STG1 to STG11 include clock signal lines CLK1 to CLK6 for supplying clock signals of six phases, a first reset signal line RESET_1 for supplying a reset signal, and a low potential for supplying a low potential voltage. It is connected to start signal lines VST1 and VST2 that supply a voltage line VSS and start signals.

Meanwhile, the illustrated block shows odd-numbered stages STG1 to STG11 formed on one side of the display panel. Accordingly, the stages STG2 to STG12 of even lines are formed on the other side of the opposite side, and the reset signal supplied to the stages STG2 to STG12 of even lines is provided through a second reset signal line (eg, RESET_2). Supplied.

The first stage STG1 may include a first clock signal supplied through the first and second start signals supplied through the first and second start signal lines VST1 and VST2 and a first clock signal line CLK1, The third clock signal supplied through the third clock signal line CLK3, the fifth clock signal supplied through the fifth clock signal line CLK5, and the sixth clock signal supplied through the sixth clock signal line CLK6. Operate in response to The first stage STG1 receives the scan signal Vg_Out_5 output from the output terminal Gout of the fifth stage STG5, which is the next stage, and discharges the Q node based on the scan signal Vg_Out_5.

The third stage STG3 receives the first clock signal supplied through the first clock signal line CLK1, the second clock signal supplied through the second clock signal line CLK2, and the third clock signal line CLK3. It operates in response to the third clock signal supplied through the fifth clock signal and the fifth clock signal line CLK5. Stages that are cascaded like the third stage STG3 do not receive the first and second start signals from the first and second start signal lines VST1 and VST2. Instead, the first scan signal Vg_Out_1 output from the output terminal Gout of the first stage STG1, which is the front stage, is used as the first start signal, and the output terminal Gout of the fifth stage STG5, which is the next stage, is used. The fifth scan signal Vg_Out_5 outputted from the < RTI ID = 0.0 > The third stage STG3 receives the seventh scan signal Vg_Out_7 output from the output terminal Gout of the seventh stage STG7, which is the next stage, and discharges the Q node based on the seventh scan signal Vg_Out_7.

All stages included in the shift register in the same form as the first and third stages STG1 and STG3 described above use the scan signals output from the output terminals of the preceding and next stages and are also scanned from themselves. It is cascaded in the form of supplying the signal to the next stage.

According to the above configuration and connection relationship, the odd-numbered stages STG1 to STG11 and the even-numbered stages STG2 to STG12 sequentially scan the first scan signal Vg_Out_1 to the twelfth scan corresponding to the scan high voltage. The signal Vg_Out_12 is output.

Subsequently, the odd-numbered stages STG1 to STG11 and the even-numbered stages STG2 to STG12 output first scan signals Vg_Out_1 to twelfth scan signals Vg_Out_12 corresponding to scan high voltages, and then to the next. The first scan signal Vg_Out_1 to the twelfth scan signal Vg_Out_12 corresponding to the scan low voltage are maintained during the frame period.

As shown in FIG. 4, the stage according to the experimental example includes Q node charging and discharging units T1, T3n, T3c, and T3r and output circuit units T5, T7c, T7d, T7c_1, and CB.

The Q node charge / discharge units T1, T3n, T3c, and T3r include a first transistor T1, a second transistor T3n, a third transistor T3c, and a fourth transistor T3r. The output circuit units T5, T7c, T7d, T7c_1, and CB include a fifth transistor T5, a sixth transistor T7c, a seventh transistor T7d, an eighth transistor T7c_1, and a capacitor CB.

The role of the Q-node charge / discharge units T1, T3n, T3c, and T3r and the output circuit units T5, T7c, T7d, T7c_1, and CB, and the connection relationship therebetween will be described below.

In the first transistor T1, the gate electrode and the first electrode are connected to the output terminal Gout [N-2] of the N-2th stage, and the second electrode is connected to the Q node Q. The first transistor T1 charges the Q node Q in response to the N-2 scan signal output from the output terminal Gout [N-2] of the N-2th stage.

The second transistor T3n has a gate electrode connected to the output terminal Gout [N + 2] of the N + 2 stage, a first electrode connected to the Q node Q, and a low potential voltage terminal VSS. Two electrodes are connected. The second transistor T3n discharges the Q node Q in response to the scan signal output from the output terminal Gout [N + 2] of the N + 2th stage.

In the third transistor T3c, a gate electrode is connected to the N-1 clock signal line CLK [N-1], and a first electrode is connected to the output terminal Gout [N-1] of the N-1 stage. The second electrode is connected to the Q node Q. The third transistor T3c charges the Q node Q in response to the N-1 clock signal supplied from the N-1 clock signal line CLK [N-1].

In the fourth transistor T3r, a gate electrode is connected to the first reset signal line RESET_1, a first electrode is connected to the Q node Q, and a second electrode is connected to the low potential voltage terminal VSS. The fourth transistor T3r resets the Q node Q to a low potential voltage supplied from the low potential voltage terminal VSS in response to the first reset signal supplied from the first reset signal line RESET_1. .

In the fifth transistor T5, a gate electrode is connected to the Q node Q, a first electrode is connected to the Nth clock signal line CLK [N], and a fifth terminal T5 is connected to the output terminal Gout [N] of its stage. Two electrodes are connected. The fifth transistor T5 receives the Nth clock signal supplied from the Nth clock signal line CLK [N] corresponding to the potential of the Q node Q through the output terminal Gout [N] of its stage. It plays a role of outputting.

In the sixth transistor T7c, a gate electrode is connected to the N-2 clock signal line CLK [N-2], and a first electrode is connected to the output terminal Gout [N] of its stage. The second electrode is connected to the terminal VSS. The sixth transistor T7c has its low potential voltage supplied from the low potential voltage terminal VSS in response to the N-2 clock signal supplied from the N-2 clock signal line CLK [N-2]. The scan signal output through the output terminal Gout [N] of the stage is converted into a scan low voltage.

The seventh transistor T7d has a gate electrode connected to the output terminal Gout [N] of its stage, a first electrode connected to the Nth clock signal line CLK [N], and an output terminal of its stage The second electrode is connected to Gout [N]). The seventh transistor T7d receives the Nth clock signal supplied from the Nth clock signal line CLK [N] in response to the potential of the output terminal Gout [N] of its stage. It outputs through Gout [N]).

In the eighth transistor T7c_1, a gate electrode is connected to the N + 2th clock signal line CLK [N + 2], and a first electrode is connected to the output terminal Gout [N] of its stage. The second electrode is connected to the terminal VSS. The eighth transistor T7c_1 has its low potential voltage supplied from the low potential voltage terminal VSS in response to the N + 2th clock signal supplied from the N + 2th clock signal line CLK [N + 2]. The scan signal output through the output terminal Gout [N] of the stage is converted into a scan low voltage.

One end of the capacitor CB is connected to the Q node Q and the other end thereof is connected to the output terminal Gout [N] of its stage. The capacitor CB bootstraps the Q node Q using the potential between the Q node Q and the output terminal Gout [N] of its stage.

As shown in FIGS. 4 and 5, the first and second start signals vst1 and vst2 supplied through the first and second start signal lines VST1 and VST2 are generated so that some sections overlap each other. . In this case, the first and second start signals vst1 and vst2 may be generated such that half of one horizontal period overlaps, but is not limited thereto.

The first to sixth clock signals clk1 to clk6 supplied through the first to sixth clock signal lines CLK1 to CLK6 are generated such that some sections overlap each other. In this case, the first to sixth clock signals clk1 to clk6 may be generated such that 1/2 of one horizontal period overlaps, but is not limited thereto.

The time at which the first and second start signals vst1 and vst2 and the first to sixth clock signals clk1 to clk6 maintain logic high is generated to partially overlap as described above. The order in which these signals are generated at logic high becomes the first and second start signals vst1 and vst2, and the first, second, third, fourth, fifth and sixth clock signals clk1 to clk6. But it is not limited thereto.

The first reset signal DMY Reset1 supplied through the first reset signal line RESET_1 is generated at a logic high once every one frame. The first reset signal DMY Reset1 may be generated at a logic high once at the end of one frame, but is not limited thereto.

When the stages of the shift register are driven by the above signal system, the Q node Q of the first stage STG1 is charged by the first start signal vst1 and bootstrap by the first clock signal clk1. This happens. At this time, the third transistor T3c operates in response to the second start signal vst2, the eighth transistor T7c_1 operates in response to the third clock signal clk3, and the sixth transistor T7c operates in the fifth transistor T7c. It can be seen that it operates in response to the 5 clock signal clk5.

As described above, when the Q node Q of the first stage STG1 is charged by the first start signal vst1 and bootstrap occurs by the first clock signal clk1, the output terminal of the first stage STG1 is generated. The first scan signal Vg_Out_1 corresponding to the scan high voltage is output to Gout.

When the stages of the shift register are driven by the above-described signal system, the Q node Q of the third stage STG3 may have the first scan signal Vg_Out_1 output from the output terminal Gout of the first stage STG1. Charge is generated by the third clock signal clk3. At this time, the third transistor T3c operates in response to the second clock signal clk2, the eighth transistor T7c_1 operates in response to the fifth clock signal clk5, and the sixth transistor T7c operates in the fifth transistor T7c. It can be seen that it operates in response to the one clock signal clk1.

As described above, the Q node Q of the third stage STG2 is charged by the first scan signal Vg_Out_1 outputted from the output terminal Gout of the first stage STG1 and is driven by the third clock signal clk3. When a bootstrap occurs, the third scan signal Vg_Out_3 corresponding to the scan high voltage is output to the output terminal Gout of the third stage STG3.

On the other hand, the stages configured as described above supply signals to the third transistor T3c that removes noise and the sixth transistor T7c corresponding to the pull-down transistor to stabilize the Q node Q and the scan low voltage. do. For example, the first stage STG1 is reset and stabilized by the fifth scan signal Vg_Out_5 of the fifth stage after outputting the first scan signal, and the third stage STG3 is configured to reset the third scan signal. After the output, the data is reset and stabilized by the seventh scan signal Vg_Out_ of the seventh stage.

However, in the case of the sixth transistor T7c corresponding to the pull-down transistor, since there is no device or method capable of stabilizing during the clock signal coming in, the ripple occurs every time the clock signal comes in, so the scan low voltage Noise is generated when the corresponding scan signal is output.

EXAMPLE

The present invention solves a problem in which a ripple occurs whenever the clock signal of the sixth transistor T7c included in the shift register according to the experimental example is generated, thereby reducing noise when outputting a scan signal corresponding to a scan low voltage. It provides a GIP shift register that can be eliminated and improves lifetime and reliability.

6 is a block diagram illustrating stages of a shift register according to an embodiment, FIG. 7 is a schematic diagram illustrating a circuit configuration of a stage according to an embodiment, and FIG. 8 is a diagram illustrating a detailed circuit configuration of a stage according to an embodiment. 9 is an exemplary waveform diagram illustrating signals and output signals supplied to a stage according to an exemplary embodiment, and FIG. 10 is a graph comparing and evaluating the ripple levels of scan signals output from a shift register of an experimental example and an exemplary embodiment.

As shown in FIG. 6, the shift register according to the embodiment includes stages STG1 to STG11. The stages STG1 to STG11 are arranged to be connected in cascade.

Stages STG1 to STG11 are supplied with six phase clock signals, a reset signal, a low potential voltage and a start signal. To this end, the stages STG1 to STG11 include clock signal lines CLK1 to CLK6 for supplying clock signals of six phases, a first reset signal line RESET_1 for supplying a reset signal, and a low potential for supplying a low potential voltage. It is connected to start signal lines VST1 and VST2 that supply a voltage line VSS and start signals.

Meanwhile, the illustrated block shows odd-numbered stages STG1 to STG11 formed on one side of the display panel. Accordingly, the stages STG2 to STG12 of even lines are formed on the other side of the opposite side, and the reset signal supplied to the stages STG2 to STG12 of even lines is provided through a second reset signal line (eg, RESET_2). Supplied.

The first stage STG1 may include a first clock signal supplied through the first and second start signals supplied through the first and second start signal lines VST1 and VST2 and a first clock signal line CLK1, The third clock signal supplied through the third clock signal line CLK3, the fifth clock signal supplied through the fifth clock signal line CLK5, and the sixth clock signal supplied through the sixth clock signal line CLK6. Operate in response to

The first stage STG1 receives the scan signal Vg_Out_5 output from the output terminal Gout of the fifth stage STG5, which is the next stage, and discharges the Q node based on the scan signal Vg_Out_5. The first stage STG1 removes ripple generated at the output terminal Gout of its stage by using its clock signal.

The third stage STG3 receives the first clock signal supplied through the first clock signal line CLK1, the second clock signal supplied through the second clock signal line CLK2, and the third clock signal line CLK3. It operates in response to the third clock signal supplied through the fifth clock signal and the fifth clock signal line CLK5. Stages that are cascaded like the third stage STG3 do not receive the first and second start signals from the first and second start signal lines VST1 and VST2. Instead, the first scan signal Vg_Out_1 output from the output terminal Gout of the first stage STG1, which is the front stage, is used as the first start signal, and the output terminal Gout of the fifth stage STG5, which is the next stage, is used. The fifth scan signal Vg_Out_5 outputted from the < RTI ID = 0.0 >

The third stage STG3 receives the seventh scan signal Vg_Out_7 output from the output terminal Gout of the seventh stage STG7, which is the next stage, and discharges the Q node based on the seventh scan signal Vg_Out_7. The third stage STG3 removes ripple generated at the output terminal Gout of its stage by using its clock signal.

All stages included in the shift register in the same form as the first and third stages STG1 and STG3 described above use the scan signals output from the output terminals of the preceding and next stages and are also scanned from themselves. It is cascaded in the form of supplying the signal to the next stage.

According to the above configuration and connection relationship, the odd-numbered stages STG1 to STG11 and the even-numbered stages STG2 to STG12 sequentially scan the first scan signal Vg_Out_1 to the twelfth scan corresponding to the scan high voltage. The signal Vg_Out_12 is output.

Subsequently, the odd-numbered stages STG1 to STG11 and the even-numbered stages STG2 to STG12 output first scan signals Vg_Out_1 to twelfth scan signals Vg_Out_12 corresponding to scan high voltages, and then to the next. The first scan signal Vg_Out_1 to the twelfth scan signal Vg_Out_12 corresponding to the scan low voltage are maintained during the frame period.

As shown in FIG. 7, the stage according to the embodiment includes the Q node charging and discharging units T1, T3n, T3c, and T3r, the output circuit units T5, T7c, T7d, T7c_1, and CB, and the ripple removing unit RDC. do.

The Q node charge / discharge units T1, T3n, T3c, and T3r include a first transistor T1, a second transistor T3n, a third transistor T3c, and a fourth transistor T3r. The output circuit units T5, T7c, T7d, T7c_1, and CB include a fifth transistor T5, a sixth transistor T7c, a seventh transistor T7d, an eighth transistor T7c_1, and a capacitor CB.

The ripple removing unit RDC removes the ripple generated at the output terminal Gout [n] of its stage by using the potential of the Q node Q and its clock signal. The ripple removing unit RDC removes the ripple generated at the output terminal Gout [n] of its stage when the potential of the Q node Q is in a discharge state and its clock signal is logic high. The ripple removing unit RDC electrically connects the output terminal Gout [n] of its stage and the low potential voltage terminal VSS supplied with the low potential voltage to the output terminal Gout [n] of its stage. Eliminate ripples from

As shown in FIG. 8, the roles of the Q node charging and discharging units T1, T3n, T3c, and T3r, the output circuit units T5, T7c, T7d, T7c_1, and CB, and the ripple removing unit RDC, and their connection relations are illustrated. The explanation is as follows.

In the first transistor T1, the gate electrode and the first electrode are connected to the output terminal Gout [N-2] of the N-2th stage, and the second electrode is connected to the Q node Q. The first transistor T1 charges the Q node Q in response to the N-2 scan signal output from the output terminal Gout [N-2] of the N-2th stage.

The second transistor T3n has a gate electrode connected to the output terminal Gout [N + 2] of the N + 2 stage, a first electrode connected to the Q node Q, and a low potential voltage terminal VSS. Two electrodes are connected. The second transistor T3n discharges the Q node Q in response to the scan signal output from the output terminal Gout [N + 2] of the N + 2th stage.

In the third transistor T3c, a gate electrode is connected to the N-1 clock signal line CLK [N-1], and a first electrode is connected to the output terminal Gout [N-1] of the N-1 stage. The second electrode is connected to the Q node Q. The third transistor T3c charges the Q node Q in response to the N-1 clock signal supplied from the N-1 clock signal line CLK [N-1].

In the fourth transistor T3r, a gate electrode is connected to the first reset signal line RESET_1, a first electrode is connected to the Q node Q, and a second electrode is connected to the low potential voltage terminal VSS. The fourth transistor T3r resets the Q node Q to a low potential voltage supplied from the low potential voltage terminal VSS in response to the first reset signal supplied from the first reset signal line RESET_1. .

In the fifth transistor T5, a gate electrode is connected to the Q node Q, a first electrode is connected to the Nth clock signal line CLK [N], and a fifth terminal T5 is connected to the output terminal Gout [N] of its stage. Two electrodes are connected. The fifth transistor T5 receives the Nth clock signal supplied from the Nth clock signal line CLK [N] corresponding to the potential of the Q node Q through the output terminal Gout [N] of its stage. It plays a role of outputting.

In the sixth transistor T7c, a gate electrode is connected to the N-2 clock signal line CLK [N-2], and a first electrode is connected to the output terminal Gout [N] of its stage. The second electrode is connected to the terminal VSS. The sixth transistor T7c has its low potential voltage supplied from the low potential voltage terminal VSS in response to the N-2 clock signal supplied from the N-2 clock signal line CLK [N-2]. The scan signal output through the output terminal Gout [N] of the stage is converted into a scan low voltage.

The seventh transistor T7d has a gate electrode connected to the output terminal Gout [N] of its stage, a first electrode connected to the Nth clock signal line CLK [N], and an output terminal of its stage The second electrode is connected to Gout [N]). The seventh transistor T7d receives the Nth clock signal supplied from the Nth clock signal line CLK [N] in response to the potential of the output terminal Gout [N] of its stage. It outputs through Gout [N]).

In the eighth transistor T7c_1, a gate electrode is connected to the N + 2th clock signal line CLK [N + 2], and a first electrode is connected to the output terminal Gout [N] of its stage. The second electrode is connected to the terminal VSS. The eighth transistor T7c_1 has its low potential voltage supplied from the low potential voltage terminal VSS in response to the N + 2th clock signal supplied from the N + 2th clock signal line CLK [N + 2]. The scan signal output through the output terminal Gout [N] of the stage is converted into a scan low voltage.

One end of the capacitor CB is connected to the Q node Q and the other end thereof is connected to the output terminal Gout [N] of its stage. The capacitor CB bootstraps the Q node Q using the potential between the Q node Q and the output terminal Gout [N] of its stage.

The ripple removing unit RDC outputs a clock signal of its own when the potential of the Q node Q is discharged, and outputs its own clock signal when the potential of the Q node Q is charged. RDC1) and second circuit portion RDC2 for removing ripples generated at output terminal Gout [n] of its stage as its clock signal in response to its clock signal output from first circuit portion RDC1. Included.

The first circuit part RDC1 outputs its own clock signal when the potential of the Q node Q is discharged, and not outputs its own clock signal when the potential of the Q node Q is charged. Therefore, from the standpoint of the Q node Q, since the first circuit part RDC1 operates opposite to its state of charge, the first circuit part RDC1 outputs a signal for controlling the second circuit part RDC2 like the interleaver.

The first circuit portion RDC1 includes a first compensation transistor T8a, a second compensation transistor T8b, and a third compensation transistor T8c, and the second circuit portion RDC2 includes a fourth compensation transistor T8d. do.

In the first compensation transistor T8a, the gate electrode and the first electrode are commonly connected to the Nth clock signal line CLK [n] to which the Nth clock signal is supplied, and the second electrode is connected to the first node A. do. In the second compensation transistor T8b, a gate electrode is connected to the Q node Q, a first electrode is connected to the first node A, and a second electrode is connected to the low potential voltage terminal VSS. In the third compensation transistor T8c, a gate electrode is connected to the first node A, a first electrode is connected to the Nth clock signal line CLK [n], and a second electrode is connected to the second circuit portion RDC2. do. In the fourth compensation transistor T8d, a gate electrode is connected to the second electrode of the third compensation transistor T8c, and a first electrode is connected to the output terminal Gout [n] of its stage, and the low potential voltage terminal VSS is connected. ) Is connected to the second electrode.

As shown in FIGS. 8 and 9, the first and second start signals vst1 and vst2 supplied through the first and second start signal lines VST1 and VST2 are generated so that some sections overlap each other. . In this case, the first and second start signals vst1 and vst2 may be generated such that half of one horizontal period overlaps, but is not limited thereto.

The first to sixth clock signals clk1 to clk6 supplied through the first to sixth clock signal lines CLK1 to CLK6 are generated such that some sections overlap each other. In this case, the first to sixth clock signals clk1 to clk6 may be generated such that half of one horizontal period overlaps, but is not limited thereto.

The time at which the first and second start signals vst1 and vst2 and the first to sixth clock signals clk1 to clk6 maintain logic high is generated to partially overlap as described above. The order in which these signals are generated at logic high becomes the first and second start signals vst1 and vst2, and the first, second, third, fourth, fifth and sixth clock signals clk1 to clk6. But it is not limited thereto.

The first reset signal DMY Reset1 supplied through the first reset signal line RESET_1 is generated at a logic high once every one frame. The first reset signal DMY Reset1 may be generated at a logic high once at the end of one frame, but is not limited thereto.

When the stages of the shift register are driven by the above signal system, the Q node Q of the first stage STG1 is charged by the first start signal vst1 and bootstrap by the first clock signal clk1. This happens. At this time, the third transistor T3c operates in response to the second start signal vst2, the eighth transistor T7c_1 operates in response to the third clock signal clk3, and the sixth transistor T7c operates in the fifth transistor T7c. It can be seen that it operates in response to the 5 clock signal clk5.

As described above, when the Q node Q of the first stage STG1 is charged by the first start signal vst1 and bootstrap occurs by the first clock signal clk1, the output terminal of the first stage STG1 is generated. The first scan signal Vg_Out_1 corresponding to the scan high voltage is output to Gout.

When the stages of the shift register are driven by the above-described signal system, the Q node Q of the third stage STG3 may have the first scan signal Vg_Out_1 output from the output terminal Gout of the first stage STG1. Charge is generated by the third clock signal clk3. At this time, the third transistor T3c operates in response to the second clock signal clk2, the eighth transistor T7c_1 operates in response to the fifth clock signal clk5, and the sixth transistor T7c operates in the fifth transistor T7c. It can be seen that it operates in response to the one clock signal clk1.

As described above, the Q node Q of the third stage STG2 is charged by the first scan signal Vg_Out_1 outputted from the output terminal Gout of the first stage STG1 and is driven by the third clock signal clk3. When a bootstrap occurs, the third scan signal Vg_Out_3 corresponding to the scan high voltage is output to the output terminal Gout of the third stage STG3.

On the other hand, the stages configured as described above are the third transistor (T3c) for removing noise to stabilize the Q node (Q) and the scan low voltage, the sixth transistor (T7c) corresponding to the pull-down transistor and the ripple cancellation unit Supply a signal to (RDC). For example, the first stage STG1 is reset and stabilized by the fifth scan signal Vg_Out_5 of the fifth stage after outputting the first scan signal, and the third stage STG3 is configured to reset the third scan signal. After the output, the data is reset and stabilized by the seventh scan signal Vg_Out_ of the seventh stage.

Meanwhile, in the case of the sixth transistor T7c corresponding to the pull-down transistor, the sixth transistor T7c is stabilized by the operation of the ripple removing unit RDC during the period in which its clock signal is input. Specifically, the ripple cancellation unit RDC electrically connects the output terminal Gout [n] of its stage and the low potential voltage terminal VSS supplied with the low potential voltage whenever its clock signal is input. To eliminate the ripples generated at the output terminal Gout [n] of its own stage.

In this regard, comparing the waveforms of the TP1a and TP2a parts shown in the experimental example of FIG. 5 with the waveforms of the TP1b and TP2b parts shown in the embodiment of FIG. 9, the difference between the experiment and the embodiment will be clearly distinguished.

As can be seen from a graph comparing and evaluating the ripple levels of the scan signals output from the shift registers of the experimental example and the example shown in FIG. 10, the experimental example (a) has a large ripple RP in response to its clock signal. In the embodiment (b), since the ripple cancellation unit RDC operates in response to its clock signal, the ripple RP is suppressed to be generated or removed at a low width.

As a result, the scan driver of the experimental example increases the ripple due to the negative shift of the initial threshold voltage (Vth-Shift), whereas the scan driver of the embodiment shows no tendency of ripple and the initial threshold voltage margin increases by about 0.8V. Able to know. That is, the scan driver of the experimental example shows an initial threshold voltage margin of -0.5V, but the scan driver of the embodiment shows an initial threshold voltage margin of -1.3V.

Therefore, the problem that noise is generated when the scan signal corresponding to the scan low voltage is generated by the operation of the ripple canceling unit RDC is improved or eliminated.

As described above, the present invention has the effect of improving or eliminating the ripple generated at the output terminal of its stage every time its clock signal is input to increase the lifespan and reliability of the shift register embedded in the GIP method. In addition, the present invention can remove the noise, such as ripple and stabilize the Q node and the scan low voltage, it is possible to improve the life and reliability when implementing the shift resistor in the oxide thin film transistor or amorphous silicon thin film transistor.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, the technical configuration of the present invention described above may be modified in other specific forms by those skilled in the art to which the present invention pertains without changing its technical spirit or essential features. It will be appreciated that it may be practiced. Therefore, the embodiments described above are to be understood as illustrative and not restrictive in all aspects. In addition, the scope of the present invention is shown by the claims below, rather than the above detailed description. Also, it is to be construed that all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention.

100: display panel 130, 140: scan driver
STG1 to STG11: stages T1: first transistor
T3n: second transistor T3c: third transistor
T3r: fourth transistor T5: fifth transistor
T7c: 6th transistor T7d: 7th transistor
T7c_1: 8th transistor CB: capacitor
RDC: ripple removing section T8a: first compensation transistor
T8b: second compensation transistor T8c: third compensation transistor
T8d: fourth compensation transistor

Claims (11)

A level shifter for outputting start signals, clock signals, and reset signals; And
A shift register configured to shift and output a scan signal in response to the start signals, the clock signals, and the reset signals,
Nth stage of the stages
A pull-up transistor for outputting an Nth clock signal to an output terminal of the Nth stage corresponding to the potential of the Q node;
Q node charging and discharging unit for charging and discharging the Q node,
And a ripple removing unit for removing ripples generated at an output terminal of the Nth stage by using the potential of the Q node and the Nth clock signal as its clock signal.
The ripple removing unit
And a ripple generated from the output terminal of the Nth stage by electrically connecting the output terminal of the Nth stage and the low potential voltage terminal supplied with the low potential voltage. The method of claim 1,
The ripple removing unit
When the potential of the Q node is in a discharge state and the Nth clock signal is logic high,
And a ripple generated from an output terminal of the Nth stage. delete The method of claim 1,
The ripple removing unit
A first circuit part configured to output the Nth clock signal when the potential of the Q node is discharged, and not output the Nth clock signal when the potential of the Q node is charged;
And a second circuit unit configured to remove, as the Nth clock signal, a ripple generated at an output terminal of the Nth stage in response to the Nth clock signal output from the first circuit unit. The method of claim 4, wherein
The first circuit part
A first compensation transistor having a gate electrode and a first electrode connected to the Nth clock signal line supplied with the Nth clock signal in common, and a second electrode connected to the first node;
A second compensation transistor having a gate electrode connected to the Q node, a first electrode connected to a first node, and a second electrode connected to the low potential voltage terminal;
And a third compensation transistor having a gate electrode connected to the first node, a first electrode connected to the Nth clock signal line, and a second electrode connected to the second circuit part. The method of claim 5,
The second circuit portion
And a fourth compensation transistor having a gate electrode connected to the second electrode of the third compensation transistor, a first electrode connected to an output terminal of the Nth stage, and a second electrode connected to the low potential voltage terminal. Display panel;
A data driver connected to data lines of the display panel; And
A shift register connected to scan lines of the display panel and configured to shift and output a scan signal in response to start signals, clock signals, and reset signals,
Nth stage of the stages
A pull-up transistor for outputting an Nth clock signal to an output terminal of the Nth stage corresponding to the potential of the Q node;
Q node charging and discharging unit for charging and discharging the Q node,
And a ripple removing unit for removing ripples generated at an output terminal of the Nth stage by using the potential of the Q node and the Nth clock signal as its clock signal.
The ripple removing unit
When the potential of the Q node is in a discharge state and the Nth clock signal is logic high,
And a ripple generated at the output terminal of the Nth stage by electrically connecting the output terminal of the Nth stage and the low potential voltage terminal supplied with the low potential voltage. delete The method of claim 7, wherein
The ripple removing unit
A first circuit part configured to output the Nth clock signal when the potential of the Q node is discharged, and not output the Nth clock signal when the potential of the Q node is charged;
And a second circuit unit configured to remove the ripple generated at the output terminal of the Nth stage as the Nth clock signal in response to the Nth clock signal output from the first circuit unit. The method of claim 9,
The first circuit part
A first compensation transistor having a gate electrode and a first electrode connected to the Nth clock signal line supplied with the Nth clock signal in common, and a second electrode connected to the first node;
A second compensation transistor having a gate electrode connected to the Q node, a first electrode connected to a first node, and a second electrode connected to the low potential voltage terminal;
And a third compensation transistor having a gate electrode connected to the first node, a first electrode connected to the Nth clock signal line, and a second electrode connected to the second circuit part. The method of claim 10,
The second circuit portion
And a fourth compensation transistor having a gate electrode connected to the second electrode of the third compensation transistor, a first electrode connected to an output terminal of the Nth stage, and a second electrode connected to the low potential voltage terminal.

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