KR102030908B1 - Frequency mixer using low-power CMOS(complementary metal oxide semiconductor) - Google Patents

Abstract

A frequency mixer using a low power CMOS is disclosed. A frequency mixer using a low power CMOS includes a plurality of CMOS transistors and a transconductor stage including a plurality of CMOS transistors constituted by a pair of NMOS transistors and PMOS transistors. A first switching stage connected to a first source terminal and a power source of some CMOS transistors of the CMOS transistors, and a second switching stage connected to a second source terminal and ground of the remaining CMOS transistors of the plurality of CMOS transistors; It includes, but the RF signal is input to the gate terminal of the plurality of CMOS transistors, the IF signal is output from the drain terminal of the plurality of CMOS transistors.

Description

Frequency mixer using low-power CMOS (complementary metal oxide semiconductor)

The present invention relates to a frequency mixer using low power CMOS.

1 is a view showing the structure of a radio frequency (RF) receiver. In the RF receiver for wireless communication shown in FIG. 1, a frequency mixer (downlink) converts an RF signal input from an antenna into an intermediate frequency (IF) or a baseband signal (IF). It performs the role of converting. These frequency mixers should be designed with low power consumption circuits to reduce power consumption of the RF receiver. In particular, the power consumption of RF receivers for Internet of Things (IoT) applications must be on the order of tens to hundreds of micro-watts.

2 is a diagram illustrating a configuration of a general frequency mixer. As shown in FIG. 2, a typical frequency mixer is composed of a transconductor stage and a switching stage. The transconductor stage receives the RF signal, converts it into current, and amplifies it. The switching stage multiplies a signal of an RF frequency component and a local oscillator (LO) frequency signal to generate a signal having a frequency equal to the subtraction of the LO frequency from the RF frequency, thereby down converting the RF frequency of the input RF signal. Play a role of This down-converted frequency is referred to as intermediate frequency (IF) or baseband frequency (Baseband Frequency).

3 is a diagram illustrating a circuit of a conventional Gilbert-Cell frequency mixer. Gilbert cell frequency mixers are the oldest and most commonly used active downconversion frequency mixers.

In the Gilbert cell frequency mixer shown in FIG. 3, an RF signal is input to the gate terminals of the NMOS transistors M ₅ and M ₆ . The input RF signal to the source terminal of the switching stage consisting of M ₅ and by the transconductor stage transconductance (transconductance) operation consisting of M ₆ is converted into a current signal, since M _1, M _2, M ₃ and M ₄ Delivered. In this _{case, M 1, M 2, M} 3 and by the LO signal applied to the gate terminal of M _{4, M 1, M 2, M} 3 and M ₄ has a switching operation for periodically repeating on and off (On-Off) Do this. Accordingly, at the drain terminals of M ₁ , M ₂ , M _3, and M ₄ , an IF signal (V _{IF +} , V _IF- ) or a baseband signal generated from two input RF signals (V _{RF +} , V _RF- ) is output. do.

The minimum supply voltage of the Gilbert cell frequency mixer can be represented by the following equation.

That is, the minimum supply voltage V _{DD, min} is determined by the sum of the overdrive voltages V _OV5 and V _OV1 of the transconductor stage and the switch stage and the voltage I _D5 R _L applied to the resistor R _L. Here, the overdrive voltage is obtained by subtracting the threshold voltage from the gate-source voltage of the MOSFET.

4 is a diagram illustrating a circuit of a conventional AC-coupled folded-switching frequency mixer.

The AC-coupled Folded-Switching frequency mixer is a reconstruction of the portion corresponding to the transconductor stage in the frequency mixer of FIG. 3 using transistors M ₅ , M ₆ , M ₇ and M ₈ , as shown in FIG. 4. That is, the transconductor stage may be configured by connecting the drain terminals of the NMOS transistors M ₅ and M _{7 and} the drain terminals of the PMOS transistors M ₆ and M ₈ , respectively. With this connection, the transconductance Gm of the transconductor stage can be improved as shown in the following equation.

The frequency mixer shown in FIG. 4 has increased the total transconductance value of the transconductor stage, thereby lowering the current consumption to obtain the same transconductance. The lower the current consumption, the lower the overdrive voltage accordingly. Thus, under the condition of having the same RF performance, the frequency mixer of FIG. 4 allows the use of M ₅ having a smaller overdrive voltage compared to the frequency mixer of FIG. This may lower the overall minimum supply voltage of the frequency mixer.

In the Gilbert cell frequency mixer of FIG. 3, the maximum and minimum values of LO signals that can be applied to the gate terminals of M ₁ , M ₂ , M _3, and M ₄ are limited as in the following equation.

This condition causes the transistors of the transconductor stage and the transistors of the switching stage to operate in the saturation region. If the LO signal leaves this condition, the linearity of the frequency mixer is severely compromised. This condition limits the voltage magnitude of the input LO signal, which leads to deterioration of switching performance. As a result, the conversion gain performance of the entire frequency mixer is reduced. In order to improve such performance degradation, a new frequency mixer shown in FIG. 5 has been proposed.

5 shows a circuit of a conventional Switched-Gm frequency mixer.

The Switched-Gm frequency mixer uses transistors M ₅ , M ₆ , M _7, and M ₈ , as shown in FIG. 5, to remove the voltage magnitude constraints of the LO signal input from the Gilbert cell frequency mixer shown in FIG. 3. The configured switching stage is connected to the source terminals of transistors M ₁ , M ₂ , M ₃ and M ₄ of the transconductor stage.

The NMOS transistors M ₅ and M ₇ and the PMOS transistors M ₆ and M ₈ are alternately turned on and off by the LO signal applied to the gate terminals of M ₅ , M ₆ , M ₇ and M ₈ . As a result, the supply voltage V _DD and ground GND are alternately input to the source terminals of M ₁ , M ₂ , M _3, and M ₄ to perform a switching operation of the frequency mixer. Unlike the Gilbert cell frequency mixer, the Switched-Gm frequency mixer has no limitation on the voltage magnitude of the LO signal applied to the gate terminals of the transistors M ₅ , M ₆ , M ₇ and M ₈ of the switching stage. Thus, the possibility of performance degradation due to the voltage magnitude limitation of the LO signal is reduced. In addition, since the noise generated by the switching operation is a common mode signal, it is easily removed from the differential output, which improves the noise performance of the entire circuit.

The present invention is to provide a novel frequency mixer using a low power CMOS that improves the circuit structure of the conventional Switched-Gm frequency mixer and improves performance such as voltage gain and noise figure without increasing current consumption.

According to an aspect of the present invention, a frequency mixer for receiving a radio frequency (RF) signal and down-converting a frequency to output an IF (Intermediate Frequency) signal is disclosed.

A frequency mixer using a low power CMOS according to an embodiment of the present invention includes a transconductor stage including a plurality of CMOS transistors configured as a pair of NMOS transistors and PMOS transistors. ), A first switching stage connected to a first source terminal and a power supply of some CMOS transistors of the plurality of CMOS transistors, and a second source terminal of the remaining CMOS transistors of the plurality of CMOS transistors; A second switching stage connected to ground, wherein the RF signal is input to the gate terminal of the plurality of CMOS transistors, the IF signal is output from the drain terminal of the plurality of CMOS transistors.

The gate terminal and the drain terminal of the plurality of CMOS transistors are connected by a resistor for self biasing.

The transconductor stage may include a first CMOS transistor comprising a first PMOS transistor and a second NMOS transistor, a second CMOS transistor comprising a third PMOS transistor and a fourth NMOS transistor, and a fifth PMOS transistor. And a third CMOS transistor composed of a sixth NMOS transistor, and a fourth CMOS transistor composed of a seventh PMOS transistor and an eighth NMOS transistor.

A V _{RF +} signal is input to a gate terminal of the first CMOS transistor and a fourth CMOS transistor, a V _RF− signal is input to a gate terminal of the second CMOS transistor and the third CMOS transistor. The V _IF− signal is output at the drain terminals of the first and third CMOS transistors, and the V _{IF +} signal is output at the drain terminals of the second and fourth CMOS transistors.

A first source terminal of the first CMOS transistor and a first source terminal of the second CMOS transistor are connected at a first node, and a second source terminal of the first CMOS transistor and a second source of the second CMOS transistor are connected. A source terminal is connected at a second node, a first source terminal of the third CMOS transistor and a first source terminal of the fourth CMOS transistor are connected at a third node, and a second source of the third CMOS transistor A stage and a second source terminal of the fourth CMOS transistor are connected at the fourth node.

In the second switching stage, a drain terminal is connected to the second node, a drain terminal is connected to the fourth node, and a drain terminal is connected to the ground, and a source terminal is connected to the ground. And a tenth NMOS transistor.

The first switching stage may include a drain terminal connected to the first node, a drain terminal connected to a source terminal connected to the power supply unit, and a drain terminal connected to the third node, and a source terminal connected to the power supply unit. And a twelfth PMOS transistor.

LO signals are input to the gate terminals of the transistors of the first switching stage and the second switching stage, and the LO signal input to the first switching stage and the LO signal input to the second switching stage are 180. It has a phase difference of degrees.

The V _{LO +} signal is input to the gate terminal of the eleventh PMOS transistor of the first switching stage, and the V _LO− signal is input to the gate terminal of the ninth NMOS transistor of the second switching stage.

The first gate terminal of the first PMOS transistor 12 of the switching stage, the said V _LO- signal is input to the second gate terminal of the tenth en MOS transistor of the switching stage there is the V _{LO +} signal is input.

The frequency mixer using the low power CMOS according to the embodiment of the present invention can improve the performance such as the voltage gain and the noise figure without increasing the current consumption compared to the conventional switched-Gm frequency mixer.

1 is a view showing the structure of a radio frequency (RF) receiver.
2 is a diagram illustrating a configuration of a general frequency mixer.
3 shows a circuit of a conventional Gilbert-Cell frequency mixer.
4 shows a circuit of a conventional AC-coupled folded-switching frequency mixer.
5 shows a circuit of a conventional Switched-Gm frequency mixer.
Figure 6 shows a circuit of a frequency mixer using a low power CMOS according to an embodiment of the present invention.
7 shows simulation results for a frequency mixer according to an embodiment of the present invention.

As used herein, the singular forms "a", "an" and "the" include plural forms unless the context clearly indicates otherwise. In this specification, terms such as “consisting of” or “comprising” should not be construed as necessarily including all of the various components or steps described in the specification, and some of the components or some steps It should be construed that it may not be included or may further include additional components or steps. In addition, the terms "... unit", "module", etc. described in the specification mean a unit for processing at least one function or operation, which may be implemented in hardware or software or a combination of hardware and software. .

The frequency mixer using the low power CMOS of the present invention is configured such that the transconductor stage has a current reuse structure, and a circuit for applying a new switching stage circuit and an appropriate bias voltage for efficient switching operation. Apply.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

6 is a diagram illustrating a circuit of a frequency mixer using a low power CMOS according to an embodiment of the present invention.

Referring to FIG. 6, a frequency mixer using a low power CMOS according to an embodiment of the present invention includes a transconductor stage 10, a first switching stage 20, and a second switching stage 30.

The frequency mixer using the low power CMOS according to the embodiment of the present invention may be a switched-Gm frequency mixer having a new structure. The biggest difference between the frequency mixer according to the embodiment of the present invention and the conventional Switched-Gm frequency mixer is in the configuration of the transconductor stage 10 and the switching stages 20 and 30. In the transconductor stage 10 of the frequency mixer according to the embodiment of the present invention, the transistors M ₁ to M ₈ of the transconductor stage 10 have a current in order to limit the increase in current consumption and improve the conversion gain. It can be configured to have a reuse structure.

As shown in FIG. 6, the transconductor stage 10 is composed of pairs of NMOS transistors and PMOS transistors, that is, low power CMOS transistors.

That is, 6, the transconductor stage 10 is a PMOS transistor M ₁ and the NMOS transistor M ₂ a first CMOS transistor 11, the PMOS transistor M ₃ and the NMOS transistor M ₄ consisting of Second CMOS transistor 12 configured, Third CMOS transistor 13 composed of PMOS transistor M ₅ and NMOS transistor M ₆ and Fourth transistor composed of PMOS transistor M ₇ and NMOS transistor M ₈ . CMOS transistor 14 is included.

In this case, the first CMOS transistor 11 and the second CMOS transistor 12 are connected to source terminals, and the third CMOS transistor 13 and the fourth CMOS transistor 14 are also connected to source terminals.

That is, the first source terminal of the first CMOS transistor 11 and the first source terminal of the second CMOS transistor 12 are connected at the first node n1, and the second source of the first CMOS transistor 11 is connected. The source terminal and the second source terminal of the second CMOS transistor 12 are connected at the second node n2.

In the same manner, the first source terminal of the third CMOS transistor 13 and the first source terminal of the fourth CMOS transistor 14 are connected at the third node n3, and the third CMOS transistor 13 The second source terminal of) and the second source terminal of the fourth CMOS transistor 14 are connected at the fourth node n4.

The first switching stage 20 and the second switching stage 30 to be described later are connected to the first to fourth nodes.

At this time, an RF signal is input to the gate terminal of each of the CMOS transistors 11, 12, 13, and 14, and an IF generated from the input RF signal at the drain terminal of each of the CMOS transistors 11, 12, 13, and 14. (Intermediate Frequency) signal is output.

Specifically, a V _{RF +} signal is input to the gate terminals of the first and fourth CMOS transistors 11 and 14, and the gates of the second and third CMOS transistors 12 and 13 are input. The V _RF signal is input to the stage.

The V _{IF −} signal is output from the drain terminals of the first CMOS transistor 11 and the third CMOS transistor 13, and the drains of the second CMOS transistor 12 and the fourth CMOS transistor 14 are output. At the stage, the V _{IF +} signal is output.

The transconductor stage 10 having such a complementary Gm structure may have a current reuse structure.

In addition, in the transconductor stage 10 having a complementary Gm structure, a gate terminal and a drain terminal of each CMOS transistor 11, 12, 13, and 14 are connected through a resistor for self biasing.

That is, as shown in FIG. 6, the gate terminal and the drain terminal of the first CMOS transistor 11 are connected to the resistor R ₁ , and the gate terminal and the drain terminal of the second CMOS transistor 12 are connected to the resistor R ₂ . The gate terminal and the drain terminal of the third CMOS transistor 13 are connected to the resistor R ₃ , and the gate terminal and the drain terminal of the fourth CMOS transistor 14 are connected to the resistor R ₄ .

In order to more efficiently switch the transconductor stage 10 having such a current reuse structure and operate the mixer circuit in a double balanced type, as shown in FIG. 6, the transconductor stage 10 The first switching stage 20 and the second switching stage 30 are connected to the first source terminal or the second source terminal of the predetermined CMOS transistor, respectively.

Here, the first switching stage 20 includes the PMOS transistors M ₁₁ and M ₁₂ , and the second switching stage 30 includes the NMOS transistors M ₉ and M ₁₀ .

In the first switching stage 20, a source terminal is connected to a power supply unit V _DD , a drain terminal is connected to a transconductor stage 10, and a local oscillator (LO) signal is input to a gate terminal.

In the second switching stage 30, the source terminal is connected to the ground, the drain terminal is connected to the transconductor stage 10, and the LO signal is input to the gate terminal.

At this time, the LO signal input to the PMOS transistor gate terminal of the first switching stage 20 and the NMOS transistor gate terminal of the second switching stage 30 have a phase difference of 180 degrees.

That is, the first to-be-gate terminal of the MOS transistor M ₁₁ of the switching stage 20 is input to the V _{LO +} signal, and the gate terminal of the second NMOS transistor of the switching stage (30) M _9, the V _LO- signal input .

On the contrary, the V _LO− signal is input to the gate terminal of the PMOS transistor M ₁₂ of the first switching stage 20, and the V _{LO +} signal is input to the gate terminal of the NMOS transistor M ₁₀ of the second switching stage 30. .

Accordingly, the NMOS transistor M ₉ , the PMOS transistor M _11, and the NMOS transistor M ₁₀ and the PMOS transistor M ₁₂ have the same switching on and off states, thereby further improving the switching effect of the transconductor stage 10. It can be operated in a double balanced structure.

Compared with the conventional Switched-Gm frequency mixer of FIG. 5, the frequency mixer using the low power CMOS according to the embodiment of the present invention obtains the same transconductance value because the transconductor stage 10 has a current reuse structure. Low current consumption for

That is, the conventional Switched-Gm frequency mixer of FIG. 5 has a transconductor stage consisting of NMOS transistors of M ₁ , M ₂ , M _3, and M ₄ , whereas the frequency mixer according to an embodiment of the present invention has an NMOS ( NMOS transistors and PMOS transistor pairs 11, 12, 13, and 14. Thus, the frequency mixer according to the embodiment of the present invention has the advantage that the current consumption for obtaining the same transconductance value is reduced to about 70% compared to the conventional Switched-Gm frequency mixer of FIG.

In another advantage, the conventional Switched-Gm frequency mixer of FIG. 5 has a load terminal of M ₉ and M ₁₀ connected to the transconductor stage so that the required supply voltage is increased as much as that. By using the output of the transconductor stage 10 as a current and the load stages subsequently connected in series, voltage consumption by the load stages was eliminated.

7 is a view showing a simulation result for the frequency mixer according to the embodiment of the present invention.

In order to verify the operation and performance of the frequency mixer according to the embodiment of the present invention, a circuit was designed in a 65 nm CMOS process, and performance verification was performed by simulation. In addition, for the performance comparison with the conventional frequency mixer, a simulation was performed after the circuit of the conventional Switched-Gm frequency mixer of FIG. 5 was designed in the same process.

Design values of the frequency mixer circuit of FIG. 6 according to an embodiment of the present invention are shown in Table 1 below.

W / L (m) of M1, M3, M5, M7 12 / 0.08 W / L (m) of M2, M4, M6, M8 4 / 0.08 W / L (m) of M9, M10 4 / 0.06 W / L (m) of M11, M12 12 / 0.06 R1, R2, R3, R4 (k) 51 R _B (k) 51 C _B (fF) 520 V _DCP (mV) 700 V _DCN (mV) 300 V _DD (V) One

And, the design value of the conventional Switched-Gm frequency mixer of Figure 5 is shown in Table 2 below.

W / L (m) of M1, M2, M3, M4 4 / 0.06 M5, M7, W / L (m) 3 / 0.06 M6, M8, W / L (m) 6 / 0.06 W / L (m) of M9, M10 60 / 0.06 R1, R2 (k) 60 VDD (V) One

The frequency mixer circuit according to an embodiment of the present invention is designed to operate under very low power consumption of several hundred microwatts for IoT applications.

The RF signal of FIG. 7A and the LO signal of FIG. 7B are equally applied to the frequency mixer and the conventional frequency mixer according to the embodiment of the present invention. Accordingly, the waveforms of the IF output signals of the frequency mixer and the conventional frequency mixer according to the embodiment of the present invention are shown as shown in FIGS. 7C and 7D, respectively.

As shown in (c) and (d) of Figure 7, the frequency mixer according to the embodiment of the present invention outputs the IF output signal 7.4dB or about 2.3 times larger than the conventional frequency mixer.

The main performance of the frequency mixer and the conventional frequency mixer according to an embodiment of the present invention can be summarized as shown in Table 3 below.

Voltage gain (dB) Noise figure
(dB) Input P1dB
(dBm) IIP3
(dBm) Power consumption (mW)
@ 1 V supply Conventional circuit 3.25 26.44 -2.66 6.69 0.38 Invention circuit 10.68 21.48 -3.53 4.24 0.34

As can be seen from Table 3, the frequency mixer according to the embodiment of the present invention can be seen that the voltage gain is 7.43dB, the noise figure is improved 4.98dB at a similar power consumption. The linearity characteristics of InputP1dB and IIP3 were found to be insignificant, with some deterioration but not significantly affecting system performance. As a result, it can be seen that the frequency mixer according to the embodiment of the present invention is superior to the conventional Switched-Gm frequency mixer of FIG. 5.

The embodiments of the present invention described above are disclosed for purposes of illustration, and those skilled in the art having ordinary knowledge of the present invention may make various modifications, changes, and additions within the spirit and scope of the present invention. Should be considered to be within the scope of the following claims.

10: Transconductor Stage
11: first CMOS transistor
12: second CMOS transistor
13: third CMOS transistor
14: fourth CMOS transistor
20: first switching stage
30: second switching stage

Claims (10)

In the frequency mixer that receives an RF (Radio Frequency) signal and down-converts the frequency to output an IF (Intermediate Frequency) signal,
A transconductor stage including a plurality of CMOS transistors composed of a pair of NMOS transistors and PMOS transistors;
A first switching stage connected to a first source terminal and a power supply unit of some CMOS transistors of the plurality of CMOS transistors; And
A second switching stage connected to a second source terminal and ground of the remaining CMOS transistors of the plurality of CMOS transistors,
The RF signal is input to a gate terminal of the plurality of CMOS transistors of the transconductor stage, and the IF signal is output from a drain terminal of the plurality of CMOS transistors of the transconductor stage,
A frequency mixer using a low power CMOS, characterized in that the LO (Local Oscillator) signal is input to the gate terminal of the first switching stage and the second switching stage.
The method of claim 1,
And a gate terminal and a drain terminal of the plurality of CMOS transistors are connected by a resistor for self biasing.
The method of claim 1,
The transconductor stage may include a first CMOS transistor comprising a first PMOS transistor and a second NMOS transistor, a second CMOS transistor comprising a third PMOS transistor and a fourth NMOS transistor, and a fifth PMOS transistor. And a third CMOS transistor comprising a sixth NMOS transistor and a fourth CMOS transistor comprising a seventh PMOS transistor and an eighth NMOS transistor.
The method of claim 3,
A V _{RF +} signal is input to a gate terminal of the first CMOS transistor and a fourth CMOS transistor, a V _RF- signal is input to a gate terminal of the second CMOS transistor and the third CMOS transistor.
A V _IF− signal is output at the drain terminals of the first and third CMOS transistors, and a V _{IF +} signal is output at the drain terminals of the second and fourth CMOS transistors. Frequency mixer using low power CMOS.
The method of claim 3,
A first source terminal of the first CMOS transistor and a first source terminal of the second CMOS transistor are connected at a first node, and a second source terminal of the first CMOS transistor and a second source of the second CMOS transistor are connected. The source end is connected at the second node,
The first source terminal of the third CMOS transistor and the first source terminal of the fourth CMOS transistor are connected at a third node, and the second source terminal of the third CMOS transistor and the second source of the fourth CMOS transistor are connected. A frequency mixer using a low power CMOS, characterized in that the source terminal is connected at the fourth node.
The method of claim 5,
The second switching stage,
A ninth NMOS transistor having a drain terminal connected to the second node and a source terminal connected to the ground; And
And a tenth NMOS transistor having a drain terminal connected to the fourth node and a source terminal connected to the ground.
The method of claim 6,
The first switching stage,
An eleventh PMOS transistor having a drain terminal connected to the first node and a source terminal connected to the power supply unit; And
And a twelfth PMOS transistor having a drain terminal connected to the third node and a source terminal connected to the power supply unit.
The method of claim 7, wherein
LO (Local Oscillator) signals are input to the gate terminals of the transistors of the first switching stage and the second switching stage,
The LO signal input to the first switching stage and the LO signal input to the second switching stage have a phase difference of 180 degrees.
The method of claim 7, wherein
The V _{LO +} signal is input to the gate terminal of the eleventh PMOS transistor of the first switching stage, and the V _LO− signal is input to the gate terminal of the ninth NMOS transistor of the second switching stage. Frequency mixer using low power CMOS.
The method of claim 9,
The first and the second gate terminal of the 12 PMOS transistor of the first switching stage has entered the V _LO- signal, characterized in that the second the tenth en gate terminal of the MOS transistor of the switching stage there is the V _{LO +} signal input Frequency mixer using low power CMOS.

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