KR102030465B1 - Lateral typed power semiconductor device - Google Patents

Abstract

The power semiconductor device of the present invention comprises a substrate containing silicon carbide (SiC); A source region of a first conductivity type and a drain region of a first conductivity type formed on the substrate to be spaced apart from each other in a horizontal direction; A channel region of a second conductivity type connected to the source region and opposite to the first conductivity type formed in the substrate between the source region and the drain region spaced apart from the drain region; A second conductivity type well region connected to the channel region and formed deeper in the substrate than the channel region so as to surround the source region; A drift region of a first conductivity type formed in the substrate between the channel region and the drain region; A gate insulating layer on the channel region; A gate electrode formed on the gate insulating layer to control turn-on and turn-off of the channel region; A source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region; An upper insulating layer formed on the substrate and electrically insulating the source electrode, the drain electrode, and the gate electrode; The source electrode, the source region of the first conductivity type, and the channel region may have an uneven shape in which convex patterns and concave patterns are alternately repeated on a cross-section parallel to an upper surface of the substrate.

Description

Lateral type power semiconductor device

The present invention relates to a power semiconductor device, and more particularly, to a power semiconductor device having a horizontal silicon carbide (SiC) MOSFET operating structure.

Power semiconductor devices are becoming smaller and higher in performance. Accordingly, power semiconductor devices require low heat generation and high durability. In particular, MOSFETs require low ON resistance, minimum threshold voltage variation, and minimum leakage current variation. To meet these requirements, silicon carbide semiconductors have become the topic of the power semiconductor market.

Silicon carbide (SiC) has about 10 times higher dielectric breakdown voltage than silicon (Si) and is superior in many aspects such as mobility, heat dissipation, and efficiency. Silicon carbide (SiC) has some technical limitations despite having many advantages as described above with respect to silicon (Si). First of all, doping and trenching require high temperature equipment and it is difficult to form structures with temperature spreading. Therefore, in the case of a general vertical silicon carbide (SiC) MOSFET, the main structure is formed within several micrometers of the entire epitaxial layer. In general, planar silicon carbide (SiC) MOSFETs have a high channel resistance, which may be attributed to silicon carbide (SiC) surface roughness and interfacial charge. Conventional trench silicon carbide (SiC) MOSFETs are difficult to etch and have poor surface conditions. Furthermore, even with etching, a strong electric field at the trench edges can be formed, so trench wall protection can be an issue. In addition, there is a ring termination in the edge region for horizontal breakdown voltage. The smaller the chip size, the smaller the active area relative to the total area.

Related prior arts are Republic of Korea Publication No. 20140057630 (2014.05.13. Publication, the name of the invention: IGBT and its manufacturing method).

An object of the present invention is to provide a lateral type power semiconductor device capable of overcoming the above-described problems of silicon carbide (SiC) MOSFETs. However, these problems are exemplary, and the scope of the present invention is not limited thereby.

A lateral type power semiconductor device according to one aspect of the present invention for solving the above problems is provided. The lateral type power semiconductor device includes a substrate including silicon carbide (SiC); A source region of a first conductivity type and a drain region of a first conductivity type formed on the substrate to be spaced apart from each other in a horizontal direction; A channel region of a second conductivity type connected to the source region and opposite to the first conductivity type formed in the substrate between the source region and the drain region spaced apart from the drain region; A second conductivity type well region connected to the channel region and formed deeper in the substrate than the channel region so as to surround the source region; A drift region of a first conductivity type formed in the substrate between the channel region and the drain region; A gate insulating layer on the channel region; A gate electrode formed on the gate insulating layer to control turn-on and turn-off of the channel region; A source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region; An upper insulating layer formed on the substrate and electrically insulating the source electrode, the drain electrode, and the gate electrode; The source electrode, the source region of the first conductivity type, and the channel region may have an uneven shape in which convex patterns and concave patterns are alternately repeated on a cross-section parallel to an upper surface of the substrate.

In the lateral type power semiconductor device, the source electrode, the source region of the first conductivity type, and the channel region may have an uneven shape in which a curved trench pattern is repeated.

In the lateral type power semiconductor device, the gate electrode may have an uneven shape in which a convex pattern and a concave pattern are alternately repeated on another cross-section parallel to the upper surface of the substrate.

The lateral type power semiconductor device is formed on the substrate on the second conductivity type well region so as to be electrically connected to the channel region when the channel region is turned on, and connected to the channel region. A bridge region of the first conductivity type having a doping concentration higher than the drift region of the first conductivity type and lower than the source region of the first conductivity type; It may further include.

In the lateral type power semiconductor device, a portion of the first conductivity type bridge region may be located under the gate electrode, and the other portion may be located on the second conductivity type well region outside the gate electrode. .

In the lateral type power semiconductor device, the length of the other portion of the bridge region may be longer than the length of the portion of the bridge region when viewed in a direction connecting the source region and the drain region.

In the lateral type power semiconductor device, silicon carbide in the other portion of the bridge region and the substrate surface portion in the drift region exposed from the gate electrode is subjected to a surface treatment to lower the surface roughness before the upper insulating layer is formed. Can be.

In the lateral type power semiconductor device, the second conductivity type well region may include: a first well region in which the channel region is formed while surrounding the source region; And a second well region surrounding the first well region and extending below the bridge region.

In the lateral type power semiconductor device, the second conductivity type well region may further include a third well region of a second conductivity type that is higher than the first well region in the first well region. The source electrode may be connected to the third well region through the source region.

In the lateral type power semiconductor device, the first conductivity type may be n type and the second conductivity type may be p type.

In the lateral type power semiconductor device, the source electrode and the drain electrode may have a lower pattern in contact with the source region and the drain region; An upper pattern in a pad form spaced apart from the upper portion of the lower pattern; A contact pattern connecting the lower pattern and the upper pattern up and down; Each may include.

In the lateral type power semiconductor device, the source electrode of the lower pattern in the edge region of the substrate extends longer in one direction on the upper surface of the substrate than the drain electrode, and the source electrode in a direction perpendicular to the one direction It may further extend into the T shape.

According to one embodiment of the present invention made as described above, it is possible to improve the channel resistance, increase the relative ratio of the active area in the chip area, and ensure the degree of freedom in forming the drift region structure, furthermore, the channel in the same area A lateral type power semiconductor device having an improved density can be implemented. Of course, the scope of the present invention is not limited by these effects.

1 is a cross-sectional view illustrating a portion of a lateral type power semiconductor device according to an embodiment of the present invention.
2 is a diagram illustrating a doping profile and electron movement of an active cell region in a lateral type power semiconductor device according to an exemplary embodiment of the present invention.
3 is an enlarged view illustrating a Z region of the lateral type power semiconductor device illustrated in FIG. 2.
4 is a diagram illustrating a partial configuration of a source electrode and a drain electrode of an edge region in a lateral type power semiconductor device according to an embodiment of the present invention.
5 is a diagram illustrating a part of an electrode structure in a lateral type power semiconductor device according to an embodiment of the present invention.
6 is a diagram illustrating an active cell array structure in a lateral type power semiconductor device according to an embodiment of the present invention.
7 is a diagram illustrating an electric field profile of a lateral type power semiconductor device according to an embodiment of the present invention.
8 is a plan view illustrating electron movement while illustrating some components of a lateral type power semiconductor device according to another embodiment of the present invention.
9 is a diagram schematically illustrating some components of a lateral type power semiconductor device according to another embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms, and the following embodiments are intended to complete the disclosure of the present invention, the scope of the invention to those skilled in the art It is provided to inform you completely. In addition, in the drawings, at least some of the components may be exaggerated or reduced in size. Like numbers in the drawings refer to like elements.

Power semiconductor devices are becoming smaller and higher in performance. Accordingly, power semiconductor devices require low heat generation and high durability. In particular, MOSFETs require low ON resistance, minimum threshold voltage variation, and minimum leakage current variation. To meet these requirements, silicon carbide semiconductors have become the topic of the power semiconductor market.

Silicon carbide (SiC) has about 10 times higher dielectric breakdown voltage than silicon (Si) and is superior in many aspects such as mobility, heat dissipation, and efficiency. Silicon carbide (SiC) has some technical limitations despite having many advantages as described above with respect to silicon (Si). First of all, doping and trenching require high temperature equipment and it is difficult to form structures with temperature spreading. Therefore, in the case of a general vertical silicon carbide (SiC) MOSFET, the main structure is formed within several micrometers of the entire epitaxial layer. In general, planar silicon carbide (SiC) MOSFETs have a high channel resistance, which may be attributed to silicon carbide (SiC) surface roughness and interfacial charge. Conventional trench silicon carbide (SiC) MOSFETs are difficult to etch and have poor surface conditions. Furthermore, even with etching, a strong electric field at the trench edges can be formed, so trench wall protection can be an issue. In addition, there is a ring termination in the edge region for horizontal breakdown voltage. The smaller the chip size, the smaller the active area relative to the total area.

An object of the present invention is to provide a lateral type power semiconductor device capable of overcoming the above-described problems of silicon carbide (SiC) MOSFETs.

In the present specification, the first conductivity type and the second conductivity type may have opposite conductivity types, and may be either of n-type and p-type. For example, the first conductivity type may be n-type and the second conductivity type may be p-type, and the accompanying drawings illustratively assume such a conductivity type configuration. However, the technical idea of the present invention is not limited thereto. For example, the first conductivity type may be p-type and the second conductivity type may be n-type.

1 is a cross-sectional view illustrating a portion of a lateral type power semiconductor device according to an embodiment of the present invention, and FIG. 2 is a doping of an active cell region in a lateral type power semiconductor device according to an embodiment of the present invention. FIG. 3 is a diagram illustrating a profile and electron movement, and FIG. 3 is an enlarged view illustrating a Z region of the lateral type power semiconductor device illustrated in FIG. 2.

1 to 3, a lateral type power semiconductor device according to an embodiment of the present invention is provided. The lateral type power semiconductor device includes a substrate 100 including silicon carbide (SiC); A source region 118 of the first conductivity type and a drain region 132 of the first conductivity type formed on the substrate 100 so as to be spaced apart from each other in the horizontal direction; A channel region of the second conductivity type connected to the source region 118 and opposite to the first conductivity type formed in the substrate 100 between the source region 118 and the drain region 132 spaced apart from the drain region 132. 115; A second conductivity type well region 112, 114, 116 connected to the channel region 115 and formed deeper than the channel region 115 in the substrate 100 so as to surround the source region 118; A drift region 105 of a first conductivity type formed in the substrate 100 between the channel region 115 and the drain region 132; A gate insulating layer (not shown) on the channel region 115; A gate electrode 170 formed on the gate insulating layer to control turn-on and turn-off of the channel region 115; A source electrode 150 electrically connected to the source region 118 and a drain electrode 160 electrically connected to the drift region 105; An upper insulating layer 190 formed on the substrate 100 to electrically insulate the source electrode 150, the drain electrode 160, and the gate electrode 170; It includes.

Inside the drain region 132, a doping region 134 of the first conductivity type having a higher impurity concentration than that of the drain region 132 may be formed. The drain region 132 may have a form surrounding the doped region 134 of the first conductivity type, and the drain electrode 160 may be configured to be connected to the doped region 134 of the first conductivity type. Meanwhile, the first conductive buffer layer 140 may be further provided below the substrate 100.

The lateral type power semiconductor device may include a portion of the well-conducting well region of the second conductivity type to be connected to the channel region 115 so that the lateral type power semiconductor device is electrically connected to the channel region 115 when the channel region 115 is turned on. A bridge region 120 of the first conductivity type formed in the substrate 100 on 112 and having a doping concentration higher than the drift region 105 of the first conductivity type and lower than the source region 118 of the first conductivity type; It may further include.

The bridge region 120 may be implemented through an implant process of a first conductivity type impurity, and a channel length of the lateral type power semiconductor device may be reduced by the bridge region 120, and a voltage may be formed through charge sharing.

In the lateral type power semiconductor device, the second conductivity type well regions 112, 114, and 116 have a channel region 115 formed around the source region 118 to form a first well region 114. ; And a second well region 112 that extends below the bridge region 120 while surrounding the first well region 114. The first well region 114 may determine threshold voltage and channel resistance, and the second well region 112 is provided for electric field and junction protection. On the other hand, it can be understood that the second well region 112 of the second conductivity type and the bridge region 120 of the first conductivity type are provided for short channel and resurf effect.

Further, the second conductivity type well regions 112, 114, and 116 may include a second conductivity type third well region 116 having a higher concentration than the first well region 114 in the first well region 114; It may further include. In this case, the source electrode 150 may also be connected to the third well region 116 through the source region 118. The third well region 116 may prevent metal punches.

In the lateral type power semiconductor device, a portion of the first conductivity type bridge region 120 is positioned under the gate electrode 170, and the other portion of the first conductivity type bridge region 120 is the gate electrode 170. ) May be positioned on the second well region 112 of the second conductivity type. In this case, the length of the other portion of the bridge region 120 may be longer than the length of a portion of the bridge region 120 when viewed in a direction connecting the source region 118 and the drain region 132.

On the other hand, in the direction from the source region to the drain region, the gate electrode 170 is configured to extend further outward than the channel region 115, the second well region 112 of the second conductivity type is the gate electrode 170 It can be configured to stretch further outward.

In the lateral type power semiconductor device having the above-described structure, the active region has a source and a drain formed in a stripe structure so that a current flows horizontally in the cross-section, an electric field is formed in a horizontal voltage, and a depletion layer is formed. In the turn-on state of the channel region 115, electrons flow from the source region 118 to the drain region 132, and in the drift region 105, an electron spreads by Coulomb's law.

In the lateral type power semiconductor device, the silicon carbide exposed at the other portion of the bridge region 120 and the surface of the substrate 100 in the drift region 105 is exposed from the gate electrode 170. It may be surface treatment to lower the surface roughness before it is formed.

In the lateral type power semiconductor device according to the present invention, the gate electrode 170 is not formed to cover all of the drift region 105, but the silicon carbide area of the surface portion of the substrate 100 exposed from the gate electrode 170. It may be necessary to secure enough. Silicon carbide on the exposed surface of the substrate 100 may be subjected to surface treatment (eg, surface cleaning) to lower surface roughness to reduce channel resistance.

On the other hand, the upper insulating layer 190 may be formed to have a sufficiently thick thickness in order to reduce the influence of the charge contained in the silicon carbide surface and region. For example, the upper insulating layer 190 may be formed to have a thickness of 1 micrometer or more in order to minimize the interface charge influence.

4 is a diagram illustrating a partial configuration of a source electrode and a drain electrode of an edge region in a lateral type power semiconductor device according to an embodiment of the present invention, and FIG. 5 is a lateral type according to an embodiment of the present invention. A part of the electrode structure in the power semiconductor device of FIG.

4 and 5, in the lateral type power semiconductor device, the source electrode and the drain electrode have a stripe-type lower pattern contacting the source region 118 of FIG. 1 and the drain region 132 of FIG. 1. 150, 160); Upper patterns 155 and 165 in the form of pads spaced apart from each other on the stripe-type lower patterns 150 and 160; And a contact pattern (not shown) connecting the lower patterns 150 and 160 of the stripe type and the upper patterns 155 and 165 of the pad shape up and down.

In the lateral-type power semiconductor device, the source electrode 150 of the stripe-type lower patterns 150 and 160 in the edge region of the substrate is oriented in one direction (Y in FIG. 4) on the upper surface of the substrate rather than the drain electrode 160. The source electrode 150 may further extend in a T-shape in a direction perpendicular to the one direction (the direction parallel to the X-axis direction in FIG. 4) while extending longer in the axial direction.

6 is a diagram illustrating an active cell array structure in a lateral type power semiconductor device according to an embodiment of the present invention.

Referring to FIG. 6, an active cell array structure in a lateral type power semiconductor device according to an embodiment of the present invention may include a substrate 100 including silicon carbide (SiC); A source electrode 150 electrically connected to a source region formed in the substrate 100 and a drain electrode 160 electrically connected to the drain region 132; A gate electrode 170 formed on the substrate 100; An upper insulating layer 190 formed on the substrate 100 to electrically insulate the source electrode 150, the drain electrode 160, and the gate electrode 170.

In the lateral type power semiconductor device illustrated in FIG. 1, only one source electrode 150 and one drain electrode 160 are assumed. However, in a real array structure, a structure between the source electrode 150 and the drain electrode 160 may be defined. Can be placed repeatedly. In this case, the pair of source electrode 150 and the drain electrode 160 may be provided in contact with each other.

The source electrode 150 and the drain electrode 160 illustrated in FIG. 6 may correspond to a cross section of the source electrode 150 and the drain electrode 160 extending in a direction parallel to the Y-axis direction illustrated in FIG. 4. It may correspond to the lower patterns 150 and 160 of the stripe type shown in FIG. 5.

7 is a diagram illustrating an electric field profile of a lateral type power semiconductor device according to an embodiment of the present invention. The area at the bottom of the graph may mean internal pressure.

Referring to FIG. 7, it can be seen that the electric field profile of the lateral type power semiconductor device according to the embodiment of the present invention can reduce the channel resistance, protect the lower portion of the gate, and implement a charge sharing structure for forming a high breakdown voltage. .

So far, a lateral type power semiconductor device according to an embodiment of the present invention has been described with reference to the drawings.

Looking at this from another perspective, the lateral type power semiconductor device is a silicon carbide lateral MOSFET technology, the metal region through which power is input and output; An insulating layer separating each signal; It may be divided into a silicon carbide region for MOSFET operation, and the silicon carbide region may be composed of an active region and an edge region.

The metal region has a source, a drain, and a gate pad disposed on an upper metal, and each metal is separated by an insulating layer. The lower metal is divided into a source and a drain, and is formed in a stripe type. Connected. Source and drain contacts are implemented by going through the recess etch.

In the lateral type power semiconductor device, the insulating layer may be formed as a thick region of 1 micrometer or more in order to separate the input and output signals and reduce the influence of the charge contained in the silicon carbide surface and region.

In the lateral type power semiconductor device, the silicon carbide region is divided into an active region and an edge region, and the active region is an region in which a current voltage is formed to actually drive the MOSFET, and the edge region is an region that determines the breaking performance of the MOSFET. to be. In the active region, a source and a drain are formed in a stripe structure so that a current flows horizontally in a cross section, a voltage is also formed in a horizontal electric field, and a depletion layer is formed. At the drain end, a high concentration N layer may be formed to prevent punching.

In the lateral-type power semiconductor device, the P body of the source terminal P layer for determining the threshold voltage and the channel resistance through a plurality of implants; A high concentration P layer preventing punching of metal; It can be composed of low concentration P layer for electric field and junction protection. The low concentration P layer may be implanted with a larger area than the gate poly to protect the bottom of the gate, and the surface layer may be characterized by reducing the channel length through N implants and forming a voltage through charge sharing.

On the other hand, in the lateral type power semiconductor device, the edge region is terminated in the horizontal direction of the lower metal in both ends of the source end, the drain in the vertical direction of the lower metal is shorter than the source ends. You can do Furthermore, the last source terminal formed in the horizontal direction of the edge region may be formed wider than the P body of the active region in consideration of the superior effect on the corner side, and the source terminal formed in the vertical direction of the edge region may have a chip corner and a stripe drain. Considering the superior effect of the last stage, it can be characterized by forming a large contact space and a P body layer.

The lateral type power semiconductor device, which discloses the above-described structure, is a lateral operation of silicon carbide MOSFETs, and improves channel resistance, which is an issue of general planar silicon carbide MOSFETs, through surface roughness improvement and thick insulating layer. It can be overcome by omitting the trench method and roughness which are issues of the general trench silicon carbide MOSFET. In addition, since ring and termination of a vertical structure of a general power semiconductor can be omitted, an active area ratio per total chip area can be maximized. The smaller the chip area, the greater the effect.

In the above-described lateral type power semiconductor device, a minimum cell pitch for forming breakdown voltage is required, which results in a low channel density per chip area. Hereinafter, another embodiment in which the channel density is improved in the lateral type power semiconductor device will be described. Another embodiment discloses a configuration in which the channel density is improved at the same cell pitch and the channel is bent through the trench to improve the density.

8 is a plan view illustrating electron movement while illustrating a partial configuration of a lateral type power semiconductor device according to another embodiment of the present invention, and FIG. 9 is a lateral type power semiconductor device according to another embodiment of the present invention. Some diagrammatically illustrates the configuration. Descriptions of components common to those of FIGS. 1 to 7 illustrating a lateral type power semiconductor device according to an exemplary embodiment of the present invention will be omitted here for convenience.

1, 8, and 9, a lateral type power semiconductor device according to another embodiment of the present invention may include a substrate 100 including silicon carbide (SiC); A source region 118 of the first conductivity type and a drain region 132 of the first conductivity type formed on the substrate 100 so as to be spaced apart from each other in the horizontal direction; A channel region of the second conductivity type connected to the source region 118 and opposite to the first conductivity type formed in the substrate 100 between the source region 118 and the drain region 132 spaced apart from the drain region 132. 115; A second conductivity type well region 112, 114, 116 connected to the channel region 115 and formed deeper than the channel region 115 in the substrate 100 so as to surround the source region 118; A drift region 105 of a first conductivity type formed in the substrate 100 between the channel region 115 and the drain region 132; A gate insulating layer (not shown) on the channel region 115; A gate electrode 170 formed on the gate insulating layer to control turn-on and turn-off of the channel region 115; A source electrode 150 electrically connected to the source region 118 and a drain electrode 160 electrically connected to the drift region 105; An upper insulating layer 190 formed on the substrate 100 to electrically insulate the source electrode 150, the drain electrode 160, and the gate electrode 170; A source electrode 160, a source region 118 of the first conductivity type, and a channel region 115 on a cross section (eg, an XY plane of FIG. 1) parallel to an upper surface of the substrate 100. Has a concave-convex shape in which the convex pattern A and the concave pattern B are alternately repeated.

The source electrode 160, the source region 118 of the first conductivity type, and the channel region 115 have irregularities in which convex patterns A and concave patterns B are alternately repeated in one unit cell. It has a shape. The unevenness may be understood separately from the change of direction of the source electrode implemented according to the stack arrangement of the plurality of unit cells.

In another aspect, the source electrode 160, the first conductivity type source region 118, and the channel region 115 have a concave-convex shape in which a curved trench pattern is repeated in one unit cell. Can be understood.

In another aspect, the source electrode 160, the first conductivity type source region 118 and the channel region 115 may be understood to have a zigzag shape in a unit cell. have.

The cross section of the convex pattern A cut along the line II 'of FIG. 9 and the cross section of the concave pattern B cut along the line II-II' correspond to a part of the cross-sectional structure shown in FIG. . However, the width of the source electrode 150 in the cross section of the convex pattern A cut along the line II 'of FIG. 9 is the source in the cross section of the concave pattern B cut along the line II-II'. Larger than the width of the electrode 150.

On the other hand, the lateral type power semiconductor device according to another embodiment of the present invention includes a gate electrode 170 formed on the gate insulating layer in one unit cell, and is parallel to the upper surface of the substrate 100 In another cross section, the gate electrode 170 may have a concave-convex shape in which a convex pattern and a concave pattern are alternately repeated. Accordingly, the gate electrode 170 in the cross section taken along the line II ′ of FIG. 9 is relatively drained from the gate electrode 170 in the cross section taken along the line II-II ′ of FIG. 9. 160).

According to the above configurations, it is possible to improve channel density at the same cell pitch.

Other components in the lateral type power semiconductor device according to another embodiment of the present invention will be described with reference to FIG. 1 along with FIGS. 8 and 9.

Inside the drain region 132, a doping region 134 of the first conductivity type having a higher impurity concentration than that of the drain region 132 may be formed. The drain region 132 may have a form surrounding the doped region 134 of the first conductivity type, and the drain electrode 160 may be configured to be connected to the doped region 134 of the first conductivity type. Meanwhile, the first conductive buffer layer 140 may be further provided below the substrate 100.

The lateral type power semiconductor device may include a portion of the well-conducting well region of the second conductivity type to be connected to the channel region 115 so that the lateral type power semiconductor device is electrically connected to the channel region 115 when the channel region 115 is turned on. A bridge region 120 of the first conductivity type formed in the substrate 100 on 112 and having a doping concentration higher than the drift region 105 of the first conductivity type and lower than the source region 118 of the first conductivity type; It may further include.

The bridge region 120 may be implemented through an implant process of a first conductivity type impurity, and a channel length of the lateral type power semiconductor device may be reduced by the bridge region 120, and a voltage may be formed through charge sharing.

In the lateral type power semiconductor device, the second conductivity type well regions 112, 114, and 116 have a channel region 115 formed around the source region 118 to form a first well region 114. ; And a second well region 112 that extends below the bridge region 120 while surrounding the first well region 114. The first well region 114 may determine threshold voltage and channel resistance, and the second well region 112 is provided for electric field and junction protection. On the other hand, it can be understood that the second well region 112 of the second conductivity type and the bridge region 120 of the first conductivity type are provided for short channel and resurf effect.

Further, the second conductivity type well regions 112, 114, and 116 may include a second conductivity type third well region 116 having a higher concentration than the first well region 114 in the first well region 114; It may further include. In this case, the source electrode 150 may also be connected to the third well region 116 through the source region 118. The third well region 116 may prevent metal punches.

In the lateral type power semiconductor device, a portion of the first conductivity type bridge region 120 is positioned under the gate electrode 170, and the other portion of the first conductivity type bridge region 120 is the gate electrode 170. ) May be positioned on the second well region 112 of the second conductivity type. In this case, the length of the other portion of the bridge region 120 may be longer than the length of a portion of the bridge region 120 when viewed in a direction connecting the source region 118 and the drain region 132.

On the other hand, in the direction from the source region to the drain region, the gate electrode 170 is configured to extend further outward than the channel region 115, the second well region 112 of the second conductivity type is the gate electrode 170 It can be configured to stretch further outward.

In the lateral type power semiconductor device having the above-described structure, a source and a drain are formed in the active region so that a current flows horizontally in a cross section, an electric field is formed in a horizontal voltage, and a depletion layer is formed. In the turn-on state of the channel region 115, electrons flow from the source region 118 to the drain region 132, and in the drift region 105, an electron spreads by Coulomb's law.

In the lateral type power semiconductor device, the silicon carbide exposed at the other portion of the bridge region 120 and the surface of the substrate 100 in the drift region 105 is exposed from the gate electrode 170. It may be surface treatment to lower the surface roughness before it is formed.

In the lateral type power semiconductor device according to the present invention, the gate electrode 170 is not formed to cover all of the drift region 105, but the silicon carbide area of the surface portion of the substrate 100 exposed from the gate electrode 170. It may be necessary to secure enough. Silicon carbide on the exposed surface of the substrate 100 may be subjected to surface treatment (eg, surface cleaning) to lower surface roughness to reduce channel resistance.

On the other hand, the upper insulating layer 190 may be formed to have a sufficiently thick thickness in order to reduce the influence of the charge contained in the silicon carbide surface and region. For example, the upper insulating layer 190 may be formed to have a thickness of 1 micrometer or more in order to minimize the interface charge influence.

The lateral type power semiconductor according to another embodiment of the present invention will be described with reference to FIGS. 4 and 5, which illustrate a part of an electrode structure in the lateral type power semiconductor device according to an embodiment of the present invention. Referring to the device, the source electrode and the drain electrode may include lower patterns 150 and 160 in contact with the source region 118 of FIG. 1 and the drain region 132 of FIG. 1; Upper patterns 155 and 165 in the form of pads spaced apart from each other on the lower patterns 150 and 160; And a contact pattern (not shown) connecting the lower patterns 150 and 160 of the stripe type and the upper patterns 155 and 165 of the pad shape up and down. Among them, the source electrode 150 extending in the Y-axis direction may be understood as having a concave-convex shape in which the convex pattern and the concave pattern are alternately repeated as shown in FIGS. 8 and 9.

In the edge region of the substrate, the source electrode 150 of the lower patterns 150 and 160 extends longer in one direction (the direction parallel to the Y-axis direction in FIG. 4) on the upper surface of the substrate than the drain electrode 160 and is a source electrode. 150 may further extend in a T shape in a direction perpendicular to the one direction (the direction parallel to the X-axis direction in FIG. 4).

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

100: substrate
105: drift region
112, 114, 116: well area
115: channel area
118: source region
132: drain region
150: source electrode
160: drain electrode
170: gate electrode
190: upper insulating layer

Claims (12)

A substrate comprising silicon carbide (SiC);
A source region of a first conductivity type and a drain region of a first conductivity type formed on the substrate to be spaced apart from each other in a horizontal direction;
A channel region of a second conductivity type connected to the source region and opposite to the first conductivity type formed in the substrate between the source region and the drain region spaced apart from the drain region;
A second conductivity type well region connected to the channel region and formed deeper in the substrate than the channel region so as to surround the source region;
A drift region of a first conductivity type formed in the substrate between the channel region and the drain region;
A gate insulating layer on the channel region;
A gate electrode formed on the gate insulating layer to control turn-on and turn-off of the channel region;
A source electrode electrically connected to the source region and a drain electrode electrically connected to the drain region;
An upper insulating layer formed on the substrate, the upper insulating layer electrically insulating the source electrode, the drain electrode, and the gate electrode; And
And formed in the substrate on the second conductivity type well region so as to be electrically connected to the channel region when the channel region is turned on, and higher than the drift region of the first conductivity type. A bridge region of the first conductivity type having a lower doping concentration than the source region of the first conductivity type; Including,
A portion of the first conductivity type bridge region is located under the gate electrode, and the other portion is located on the second conductivity type well region outside the gate electrode.
The source electrode, the source region of the first conductivity type and the channel region on the cross-section parallel to the upper surface of the substrate has a concave-convex shape in which the convex pattern and the concave pattern are alternately repeated,
Lateral type power semiconductor device.
The method of claim 1,
The source electrode, the source region of the first conductivity type and the channel region has a concave-convex shape in which the bent trench pattern is repeated,
Lateral type power semiconductor device.
The method of claim 1,
In another cross-section parallel to the upper surface of the substrate, the gate electrode has a concave-convex shape in which the convex pattern and the concave pattern are alternately repeated,
Lateral type power semiconductor device.
delete delete The method of claim 1,
A lateral type power semiconductor device in which the length of the other portion of the bridge region is longer than the length of a portion of the bridge region when viewed in a direction connecting the source region and the drain region.
The method of claim 1,
The silicon carbide of the other portion of the bridge region and the substrate surface portion of the drift region exposed from the gate electrode is subjected to a surface treatment for lowering the surface roughness before the upper insulating layer is formed.
The method of claim 1,
The well region of the second conductivity type is
A first well region 114 surrounding the source region to form the channel region; And
A second well region 112 surrounding the first well region and extending below the bridge region;
A lateral type power semiconductor device comprising a.
The method of claim 8,
The second conductivity type well region further includes a third conductivity type third well region 116 having a higher concentration than the first well region in the first well region 114.
And the source electrode is connected to the third well region through the source region.
The method according to any one of claims 1 to 3,
And the first conductivity type is n type and the second conductivity type is p type.
The method according to any one of claims 1 to 3,
The source electrode and the drain electrode may include a lower pattern in contact with the source region and the drain region; An upper pattern in a pad form spaced apart from the upper portion of the lower pattern; A contact pattern connecting the lower pattern and the upper pattern up and down; Each comprising a lateral type power semiconductor device.
The method of claim 11,
In the edge region of the substrate, the source electrode of the lower pattern extends longer in one direction on the upper surface of the substrate than the drain electrode, and the source electrode further extends in a T shape in a direction perpendicular to the one direction. A lateral type power semiconductor device.

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