KR101998702B1 - Slave device for a two- wire bus system - Google Patents

Abstract

The present invention relates to a slave device for a two-wire bus capable of communicating with a master device by setting a slave address without distinguishing between a data pin and a clock pin, A clock input terminal is connected to a clock pin to be connected and a data input terminal is connected to a data pin connected to a data line of the bus to decode a slave device address input to the data pin and is identical to a slave device address assigned to the data pin A normal connection bit layer unit for outputting an address setting acknowledgment signal, a data input terminal connected to the clock pin, a clock input terminal connected to the data pin, decodes a slave device address input to the clock pin, If it is the same as the slave address And a signal selection output unit for outputting an address setting acknowledgment signal output from the normal connection and cross connection bit layer unit to one of the clock pin and the data pin, ; And

Description

[0001] DESCRIPTION [0002] SLAVE DEVICE FOR A TWO-WIRE BUS SYSTEM [

The present invention relates to a slave device for a two-wire bus. More particularly, the present invention relates to a slave device for a two-wire bus capable of communicating with a master device by setting a slave address without separately connecting a data pin and a clock pin. .

와 같은 투-와이어 버스를 통해 데이터 통신하는 슬레이브 디바이스(101)는 클럭핀(105)과 데이터핀(104) 각각이 도 1에 도시한 바와 같이 투-와이어 버스(106,107)를 통해 마스터 디바이스(100)의 클럭핀(102)과 데이터핀(103)에 연결된다.Generally

A slave device 101 that communicates data via a two-wire bus such as the master pin 100 and the slave device 101 is configured such that each of the clock pin 105 and the data pin 104 is coupled to the master device 100 And a data pin 103. The data pin 103 is connected to the clock pin 102 and the data pin 103, respectively.

If two or more slave devices are connected to the two-wire bus to configure the system, address (ADD) pins 209 and 212 are used for each slave device 201 and 202, as shown in FIG. 2, Or modify the slave address of the two-wire bus using internal memory or some other additional process and method.

However, when an operator's error or the pin identification of the slave device is unclear, when the slave device's clock pin is connected to the data line of the two-wire bus and the data pin of the slave device is connected to the clock line of the two- There arises a problem that the data transmitted from the master device, for example, the address of the slave device, can not be normally received and malfunctions due to the address unsetting.

Korean Patent Publication No. 10-2009-0009904 Korean Patent Publication No. 10-2013-0061512 Korean Patent Publication No. 10-2006-0084003

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a system and method for use in a system using a two-wire bus, Wire bus, which can operate normally by setting an address assigned to the slave device.

It is still another object of the present invention to provide an address pin in addition to an address pin in addition to a clock pin and a data pin so as to address more slave device addresses than a slave device to which an existing address pin is added, And a slave device for a two-wire bus capable of improving the degree of freedom of layout of a system to be used.

According to an aspect of the present invention, there is provided a slave device for a two-wire bus,

A clock input terminal is connected to a clock pin connected to the clock line of the two-wire bus and a data input terminal is connected to a data pin connected to the data line of the bus to decode a slave device address input to the data pin, A normal connection bit layer unit for outputting an address setting acknowledgment signal if it is the same as the address of the slave device;

A data input terminal is connected to the clock pin, a clock input terminal is connected to the data pin, and a slave device address input to the clock pin is decoded. If the address is the same as the address of the slave device assigned to the slave device, A crossing bit layer unit;

And a signal selection output unit for selectively outputting an address setting acknowledgment signal output from the normal connection and cross connection bit layer unit to one of the clock pin and the data pin.

In the above-described slave device for a two-wire bus, the normal connection and cross connection bit layer units are provided in accordance with the number of slave devices connected to the two-wire bus,

The cross connection bit layer unit transmits a selection signal for transferring an address setting acknowledgment signal output from one of its data output terminal and a data output terminal of the normal connection bit layer unit to the two- And outputs it to an output unit.

According to another embodiment of the present invention, there is provided a slave device for a two-wire bus,

Each of the three pins is connected to one of a clock line and a data line of a two-wire bus, and the other pin is connected to a power supply terminal (VDD) or a ground line Connected to the ground (GND)

A clock input terminal and a data input terminal are connected to two of the three pins to decoat a slave device address input from the data line and output an address setting acknowledgment signal if the address is the same as the address of a slave device assigned to the slave device A plurality of bit layer units;

And a signal selection / output unit for selectively outputting an address setting acknowledgment signal output from any one of the plurality of bit layer units to one of the clock line and the data line.

In the slave device for a two-wire bus having such a configuration, the signal selection output section includes:

According to the combination of the bit values outputted as different values as the clock line and the data line, the power terminal and the ground terminal of the two-wire bus are connected to the clock input terminal and the data input terminal of each of the plurality of bit layer units, And an output path of the input address setting confirmation response signal is variably set,

The bit values,

A selection signal bit having a different logic level depending on whether the clock line and the data line are connected to the clock input terminal and the data input terminal, respectively;

A power connection signal bit output at a different logic level depending on whether or not a power terminal is connected to the data input terminal;

And a ground connection signal bit output at a different logic level depending on whether or not the data input terminal is connected to the ground terminal.

According to the above-mentioned problem solving means, the slave device for the two-wire bus according to the embodiment of the present invention is capable of connecting the clock line and the data line of the two-wire bus to the clock pin and the data pin, By adding a circuit configuration in which a plurality of bit layer units each responsive to a cross connection state are selectively provided and an address setting acknowledgment signal (ACK) generated from any one of them is selectively transferred to a data line of a two-wire bus, There is no need to separate the pins from the data pins and connect to the two-wire bus. Even if the data line of the two-wire bus is connected to the clock pin of the slave device by an operator's accident, have.

Further, according to another embodiment of the present invention, a slave device for two-wire bus further includes an address pin in addition to a clock pin and a data pin, and includes a plurality of bit layer units and a signal selection output section, It is possible to give more slave device addresses than the slave devices of the two-wire bus, and it is possible to improve the layout freedom of the system using the two-wire bus.

1 and 2 illustrate connection examples of a general two-wire bus system in which a master device and a slave device are connected via a two-wire bus;
Figures 3 and 4 illustrate connection examples of a two-wire bus system employing slave devices (301, 401, 402) for two-wire buses in accordance with an embodiment of the present invention.
5 is a diagram illustrating a detailed configuration of a slave device for a two-wire bus according to an embodiment of the present invention.
6 is a connection example of a two-wire bus system employing a slave device 501-515 for a two-wire bus according to another embodiment of the present invention.
Fig. 7 is a diagram showing a detailed configuration example of a slave device 501 for a two-wire bus shown in Fig. 6;
Fig. 8 is an exemplary logic level diagram of bit values output from the bit layer unit shown in Fig. 7; Fig.

It is to be understood that the specific structural or functional description of embodiments of the present invention disclosed herein is for illustrative purposes only and is not intended to limit the scope of the inventive concept But may be embodied in many different forms and is not limited to the embodiments set forth herein.

In addition, the embodiments according to the concept of the present invention can make various changes and have various forms, so that the embodiments are illustrated in the drawings and described in detail herein. It should be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms disclosed, but includes all modifications, equivalents, or alternatives falling within the spirit and scope of the invention.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

FIGS. 3 and 4 illustrate connection diagrams of a two-wire bus system employing slave devices 301, 401, and 402 for a two-wire bus according to an embodiment of the present invention.

The bus slave device 301 according to the embodiment of the present invention is connectable to the master device 300 via the two-wire buses 306 and 307 as shown in FIG. 3, 304 can be connected to the clock pin 302 of the master device 301 via the clock line 306 of the two-wire bus and the clock pin 305 of the slave device 301 is connected to the data line May be connected to the data pin 303 of the master device 301 via the bus 307.

As described above, the slave device 301 for the two-wire bus according to the embodiment of the present invention can separate the clock pin 305 and the data pin 304 from each other without connecting to the two-wire buses 306 and 307, ) And a two-wire bus protocol to set an address assigned to itself and operate normally.

4 shows a system in which slave devices 401 and 402 according to an embodiment of the present invention are connected to one master device 400 through a two-wire bus (a clock line and a data line).

The clock pin 407 of the first slave device 401 is connected to the clock pin 405 of the master device 400 via the clock line while the clock pin 405 of the second slave device 402 409 are connected to the data pins 406 of the master device 400 via the data lines.

The first slave device 400, in which the clock pin 407 and the data pin 408 are each connected to the clock line and the data line of the two-wire bus (this is referred to as a "normal connection"), The second slave device 402, which is connected to the data line and the clock line of the two-wire bus (this is referred to as a " cross connection "), is connected to the master device 400 and the two- It is possible to perform normal data communication after the address setting through the bus protocol.

5, which shows details of the configuration of one of the slave devices 301, 401, 402 used in the above-described two-wire bus system, the operation of the slave device for a two-wire bus according to the embodiment of the present invention I will explain in detail.

FIG. 5 is a detailed block diagram of a slave device for a two-wire bus according to an embodiment of the present invention. A slave device for a two-wire bus includes a normal connection bit layer unit A and a cross connection bit layer unit B And signal selection output sections C, D and TR.

5, the normal connection bit layer unit A includes a clock pin CLOCK connected to the clock line of the two-wire bus, a clock input terminal iCK connected to the data line of the bus, The data input terminal iDAT is connected to the data pin DATA to decode the slave device address (transmitted from the master device) input to the data pin DATA, and if it is the same as the slave address assigned to itself, ACK) to the data output terminal oDAT.

The address setting acknowledgment signal ACK is input to a second multiplexer D constituting a signal selection output section to be described later and is input to the second multiplexer D in accordance with the logic level of the selection signal output from the cross connection bit layer unit B, To the data line of the wire bus.

Meanwhile, another cross-connect bit layer unit B constituting a slave device for a two-wire bus has a data input terminal iDAT connected to a clock pin CLOCK constituting a slave device, When a clock input terminal iCK is connected to decode an address of a slave device input from the data line of the two-wire bus through the clock pin CLOCK and is identical to the slave address assigned to the slave device, an address setting acknowledgment signal ACK ) Through the data output terminal (oDAT).

The address setting acknowledgment signal ACK output from the cross connection bit layer unit B is input to the first multiplexer C constituting the signal selection output unit and is supplied to the first multiplexer C, (ACK) is transferred to the data line of the two-wire bus connected to the clock pin (CLOCK) according to the logic level of the selection signal output from the cross connection bit layer unit (B).

Further, the slave device for two-wire bus according to the embodiment of the present invention transmits the address setting acknowledgment signal ACK output from the normal connection and cross connection bit layer units A and B to the clock pin CLOCK of the slave device, And a data pin (DATA). The signal selection output section includes first and second multiplexers (C, D) and two switching elements Q1, Q2.

The cross connection bit layer unit B transmits the address setting acknowledgment signal ACK output from one of the data output terminal oDAT of the cross connection bit layer unit B and the data output terminal oDAT of the normal connection bit layer unit A, To a SEL_ALT terminal for outputting a selection signal SEL for transfer to a data bus of a wire bus, that is, a two-wire bus, to the first and second multiplexers C and D constituting the signal selection output section.

A plurality of normal connection and cross connection bit layer units (A, B) may be provided according to the number of slave devices connected to the two-wire bus. In this case, different bit addresses are assigned to the respective bit layer units.

For reference, each of the normal connection and cross connection bit layer units (A, B) recognizes the data line and the clock line of the two-wire bus connected to the clock pin (CLOCK) of the slave device and the data pin (DATA) .

Hereinafter, the operation of the slave device for two-wire bus having the above-described configuration will be described.

First, it is assumed that a clock line of a two-wire bus is connected to a clock pin (CLOCK) of a slave device shown in FIG. 5, and a data line is connected to a data pin (DATA).

If the start signal and the slave device address are transmitted from the master device in accordance with the two-wire bus protocol under this assumption, the normal connection bit layer unit A, on the basis of the clock input to the clock input terminal iCK, Decodes the address of the slave device to be input and checks whether the slave device address agrees with the address given to itself.

If the check result is YES, the normal connection bit layer unit A outputs a low level address setting acknowledgment signal ACK via the data output terminal oDAT. This address setting acknowledgment signal ACK is applied to the first input terminal 0 of the second multiplexer D and the second multiplexer D is applied to the low level The address setting acknowledgment signal ACK applied to the first input terminal 0 is inverted to the high level and applied to the gate terminal of the switching element Q2.

The data pin (DATA) of the slave device to which the data line of the two-wire bus is connected transits to the "low" level state and the master device outputs the address setting acknowledge signal (ACK) of "low" level through the data line It is recognized normally.

Assuming that the data line of the two-wire bus is connected to the clock pin (CLOCK) of the slave device and the clock line is connected to the data pin (DATA), the normal connection bit layer unit (A) In the cross connection bit layer unit B, the address of the slave device input through the clock pin (CLOCK) is decoded and the address setting acknowledge signal (ACK) of the 'low' level is received And output through a data output terminal (oDAT).

This address setting acknowledgment signal ACK is applied to the second input terminal 1 of the first multiplexer C and the first multiplexer C outputs a high level The address setting acknowledgment signal ACK applied to the second input terminal 1 is inverted to the high level and applied to the gate terminal of the switching element Q1.

The clock pin CLOCK of the slave device to which the data line of the two-wire bus is connected transits to the "low " level state and the master device outputs the address setting acknowledge signal ACK of the" It is recognized normally.

As described above, the slave device for the two-wire bus according to the embodiment of the present invention is capable of performing normal or cross-connection even when the clock line and the data line of the two-wire bus are normally or cross- By adding a circuit configuration in which a plurality of bit layer units A and B each responsive to the address setting acknowledge signal ACK generated from any one of them are selectively transmitted to the data line of the two-wire bus , It is unnecessary to connect the clock pin and the data pin to the two-wire bus, and even if the data line of the two-wire bus is connected to the clock pin of the slave device by an operator's accident, the two- There are advantages.

FIG. 6 illustrates a connection diagram of a two-wire bus system employing a slave device 501-515 for a two-wire bus according to another embodiment of the present invention, and FIG. And shows a detailed configuration diagram of a slave device 501 for a wire bus.

 In order to improve the layout freedom of the system using the two-wire bus, a slave device for a two-wire bus according to another embodiment of the present invention adds an address pin ADD as shown in FIG. 6 to a slave device 501-515) can be designed. 6, some of the slave devices 501-515 according to the embodiment of the present invention are connected to a clock line of a two-wire bus through a clock pin (CLOCK), and some are connected to a data pin (DATA) To the clock line of the two-wire bus, and some to the clock line of the two-wire bus through the address pin ADD. Also, some of the clock lines of the two-wire bus can be connected to the power supply (VDD).

As described above, the slave devices 501-515 for two-wire bus according to another embodiment of the present invention have a clock pin (CLOCK), a data pin (DATA) and an address (ADD) pin, Each of the pins is connected to either the clock line of the two-wire bus (the line connected to the master clock pin) and the data line (the line connected to the master data pin) and the remaining pin is connected to the power supply terminal (VDD) GND).

Such a slave device for a two-wire bus, as shown in Fig. 7,

The clock input terminal (iCK) and the data input terminal (iDAT) are connected to two pins among three pins (iCLOCK, iDATA, iADD) to decode the slave device address input from the data line of the two- A plurality of bit layer units (1-6) for outputting an address setting acknowledgment signal (ACK) through a data output terminal (oDAT) if the address is the same as the slave device address,

A signal selection output unit 700 for selectively outputting an address setting acknowledgment signal ACK output from any one of the plurality of bit layer units # 1- # 6 to a connected clock line or a data line, .

For reference, the signal selection output unit 700 outputs a clock signal to the clock input terminal iCK and data input terminal iDAT of each of the plurality of bit layer units # 1- # 6, (Bit layer unit # 1- # 6) according to combination information of bit values output as different values as a line, a data line, a power supply terminal (VDD) and a ground terminal (GND) The output path of the address setting confirmation response signal is variable.

The bit values are output to the clock input terminal (iCK) and the data input terminal (iDAT) of the bit layer unit through select signal bits (oSEL terminals) output at different logic levels depending on whether clock lines and data lines are connected )Wow,

A power connection signal bit (output through an oDH terminal) output at different logic levels depending on whether or not a power supply terminal (VDD) is connected to the data input terminal (iDAT)

And a ground connection signal bit (output through an oDL terminal) output at different logic levels depending on whether or not the ground terminal (GND) is connected to the data input terminal (iDAT).

That is, the signal selection output unit 700 includes a decoder and a multiplexer for decoding the combination information of the bit values, so that the slave device clock It is possible to recognize how the pin, the data pin, and the address pin are connected to the clock line, the data line, the power supply terminal (VDD), and the ground terminal (GND) of the two-wire bus, The output path can be set so that the address setting acknowledgment signal (ACK) generated in the bit layer unit can be transferred to the data line or the clock line of the two-wire bus.

Therefore, the slave device for two-wire bus according to another embodiment of the present invention further includes address pins in addition to the clock pin and the data pin, and includes a plurality of bit layer units and the signal selection output unit 700, It is possible to provide more slave device addresses than the existing slave devices added, and it is possible to improve the layout freedom of the system using the two-wire bus.

For reference, Table 1 below illustrates the pin connection state of each slave device 501-515 and the address of the slave device when configuring a two-wire bus system as illustrated in FIG. 6, and FIG. Wire bus system, the logic levels of the bit values output from the six bit layer units included in each slave device are illustrated.

Slave
device Slave
Address Clock pin Data pin Address pin 501 0010000b Clock line 516, Data line 517, VDD 502 0010001b Data line 517, Clock line 516, VDD 503 0010010b Data line 517, Clock line 516, GND 504 0010011b Clock line 516, Data line 517, GND 505 0010100b Clock line 516, GND Data line 517, 506 0010101b GND Clock line 516, Data line 517, 507 0010110b Data line 517, GND Clock line 516, 508 0010111b GND Data line 517, Clock line 516, 509 0011000b Clock line 516, VDD Data line 517, 510 0011001b VDD Clock line 516, Data line 517, 511 0011010b VDD Data line 517, Clock line 516, 512 0011011b Data line 517, VDD Clock line 516, 513 0011100b Data line 517, Clock line 516, Clock line 516, 514 0011101b Clock line 516, Data line 517, Clock line 516, 515 0011110b Clock line 516 Clock line 516, Data line 517,

While the invention has been shown and described with reference to certain embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims. For example, in the embodiment of the present invention, it is assumed that fifteen slave devices constitute a two-wire bus system, and each slave device includes six bit layer units for this purpose. Accordingly, the true scope of the present invention should be determined only by the appended claims.

Claims (7)

delete A clock input terminal is connected to a clock pin connected to the clock line of the two-wire bus and a data input terminal is connected to a data pin connected to the data line of the bus to decode a slave device address input to the data pin, A normal connection bit layer unit for outputting an address setting acknowledgment signal if it is the same as the assigned slave device address;
A data input terminal is connected to the clock pin and a clock input terminal is connected to the data pin to decode a slave device address input to the clock pin and output an address setting acknowledgment signal if the slave address is the same as the slave address given to the clock pin. A connection bit layer unit;
And a signal selection / output unit for selectively outputting an address setting acknowledgment signal output from the normal connection and cross connection bit layer unit to either the clock pin or the data pin, wherein the normal connection and cross connection bit layer unit ,
Wherein at least one slave device is provided according to the number of slave devices connected to the two-wire bus. The apparatus of claim 2, wherein the cross-connect bit layer unit is configured to select an address setting acknowledgment signal output from one of its data output terminal and a data output terminal of the normal connection bit layer unit to the two- And outputs a signal to the signal selection output unit. The apparatus of claim 2, wherein each of the normal connection and cross-
Wherein the data line and the clock line of the two-wire bus connected to the clock pin and the data pin are recognized and stored in the internal state register. Each of the three pins is connected to one of a clock line and a data line of a two-wire bus, and the other pin is connected to a power supply terminal (VDD) or a ground line Connected to the ground (GND)
A clock input terminal and a data input terminal are connected to two of the three pins to decode a device address inputted from the data line and output an address setting acknowledgment signal if the slave address is the same as the slave address assigned to the data line, A unit;
And a signal selection / output unit for selectively outputting an address setting acknowledgment signal output from any one of the plurality of bit layer units to one of the clock line and the data line. . The signal selection and output unit according to claim 5, wherein the signal selection output unit comprises:
According to the combination of the bit values outputted as different values as the clock line and the data line, the power terminal and the ground terminal of the two-wire bus are connected to the clock input terminal and the data input terminal of each of the plurality of bit layer units, And the output path of the input address setting acknowledgment signal is variablely set. 7. The method of claim 6,
A selection signal bit having a different logic level depending on whether the clock line and the data line are connected to the clock input terminal and the data input terminal, respectively;
A power connection signal bit output at a different logic level depending on whether or not a power terminal is connected to the data input terminal;
And a ground connection signal bit output at a different logic level depending on whether or not the ground connection is connected to the data input terminal.

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