KR101980748B1 - Timing controller and method for compressing target register configuration data - Google Patents

Abstract

The present invention relates to a timing controller and a method for compressing a target register configuration data for reducing a size of an external memory of a timing controller and reducing a read access time, Comparing the configuration data; Storing location and number information of an original target register configuration data different from the default register data; And storing the original register configuration data in a different order from the default register data, wherein the data is compressed and stored in an external nonvolatile memory.

Description

Timing controller and method for compressing target register configuration data [

The present invention relates to a liquid crystal display, and more particularly, to a timing controller and a method of compressing target register configuration data for reducing a size of an external memory of a timing controller and reducing a read access time.

2. Description of the Related Art In recent years, flat panel displays have been widely used as display devices due to their excellent image quality, light weight, thinness, and low power. As flat panel display devices, there are a liquid crystal display (LCD) device and an organic light emitting diode (OLED) display device. Most of these devices are commercialized and commercially available.

Among them, the liquid crystal display device displays images by using the electric and optical characteristics of the liquid crystal. Liquid crystals can have different anisotropic properties depending on the molecular axis and the direction of the short axis, such as refractive index and dielectric constant, and can easily control the molecular arrangement and optical properties. A liquid crystal display device using the same displays an image by changing the alignment direction of liquid crystal molecules according to the electric field size and adjusting the light transmittance transmitted through the polarizing plate.

Hereinafter, a conventional liquid crystal display device will be described with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of a general liquid crystal display device, and Fig. 2 is a specific configuration diagram of the timing control section of Fig.

1, a general liquid crystal display device includes a plurality of gate lines GL1 to GLn arranged at regular intervals in one direction and a plurality of gate lines GL1 to GLn arranged in a direction perpendicular to the plurality of gate lines GL1 to GLn And a liquid crystal capacitor Clc connected to the TFTs. The liquid crystal display device includes a plurality of data lines DL1 to DLm that are arranged in a row direction and define a pixel region, a thin film transistor (TFT) (2); A gate driver 6 for driving the gate lines GL1 to GLn of the liquid crystal panel 2; A data driver 4 for driving the data lines DL1 to DLm of the liquid crystal panel 2; And a timing controller 8 for aligning image data RGB input from the outside and supplying the data to the data driver 4 and controlling the data driver 4. [

Here, the liquid crystal capacitor Clc is composed of a pixel electrode connected to the TFT, and a common electrode arranged between the pixel electrode and the liquid crystal. The TFT supplies a video signal from each of the data lines DL1 to DLm to the pixel electrode in response to a scan pulse from each of the gate lines GL1 to GLn. The liquid crystal capacitor Clc charges the difference voltage between the video signal supplied to the pixel electrode and the common voltage, and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage. At this time, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line and the insulating film interposed therebetween.

The gate driver 6 sequentially drives the gate lines GL1 to GLn according to the gate control signal GCS from the timing controller 8. [ Specifically, the gate driver 4 outputs a gate start signal (GSP), a gate shift clock (GSC), a gate output enable (GOE) signal Or the like so that the scan pulses of the gate high voltage (VGH) level are sequentially supplied to the gate lines GL1 to GLn. And the gate low voltage is supplied for the remaining period in which the scan pulse is not supplied.

The data driver 4 receives a data control signal DCS from the timing controller 8, for example, a source start signal SSP, a source shift clock SSC, (Data) from the timing controller 8 to an analog voltage, that is, a video signal, using a source output enable (SOE) signal and an inversion signal (Pol Signal). Specifically, the data driver 4 latches the aligned data Data through the timing controller 8 in accordance with the SSC, and then, in response to the SOE signal, the data driver 4 supplies the scan pulses to the gate lines GL1 to GLn And supplies video signals for one horizontal line to each of the data lines DL1 to DLm for each horizontal period.

The timing controller 8 controls the data driver 4 and the gate driver 6 in accordance with external image data RGB and a plurality of synchronization signals DCLK, Hsync, Vsync, and DE. Specifically, the timing controller 8 arranges image data (RGB) input from the outside so as to be suitable for driving the liquid crystal panel 2, and supplies the image data to the data driver 4. A gate control signal GCS and a data control signal GCS are generated by using at least one of a synchronizing signal input from the outside, that is, a dot clock DCLK, a data enable signal DE, and horizontal and vertical synchronizing signals Hsync and Vsync DCS, and supplies them to the gate driver 6 and the data driver 4, respectively.

The timing controller 8 performing the above operation stores the default register data values for timing control and option setting in the timing controller 8a as shown in FIG. And a non-volatile memory 8b outside the chip is used to store target register configuration data for controlling the above-described operation.

The timing control unit 8a reads the target register configuration data from the nonvolatile memory 8b, loads the target register configuration data into the internal register 8c, and uses the target register configuration data.

However, such a conventional timing controller has the following problems.

That is, the target register configuration data is stored in the external nonvolatile memory, and the timing controller reads and loads the target register configuration data from the external nonvolatile memory, and performs the above-mentioned operation. That is, image data (RGB) inputted from the outside is aligned so as to be suitable for driving the liquid crystal panel 2 and supplied to the data driver 4. A gate control signal GCS and a data control signal GCS are generated by using at least one of a synchronizing signal input from the outside, that is, a dot clock DCLK, a data enable signal DE, and horizontal and vertical synchronizing signals Hsync and Vsync DCS, and supplies them to the gate driver 6 and the data driver 4, respectively.

Therefore, the conventional timing controller requires a nonvolatile memory having a large storage capacity, and the target register configuration data must be completely read from the nonvolatile memory, so that a large access time is required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a timing controller capable of reducing the size and access time of the timing controller external nonvolatile memory.

It is another object of the present invention to provide a method for compressing target register configuration data of a timing controller.

According to another aspect of the present invention, there is provided a timing controller including: an external nonvolatile memory for storing encoded target register configuration data; a register for storing default register data values for timing control and option setting; And a timing controller for controlling the gate driver and the data driver by using the decoded target register configuration data, and a decoder for decoding the target register configuration data stored in the nonvolatile memory.

The encoded target register configuration data stored in the external nonvolatile memory may include the original target register configuration data different from the default register data and the location information of the other original target register configuration data .

According to another aspect of the present invention, there is provided a method of compressing target register configuration data, the method comprising: comparing default register data and original target register configuration data in units of a predetermined number of bytes; Storing location and number information of an original target register configuration data different from the default register data; And storing the target register configuration data different from the default register data in order.

Herein, the compressed target register configuration data format is divided into an interface option data checksum and a main data checksum, a compression on / off option and compression method selection information are recorded in the interface option data checksum, The location and number information of the original target register configuration data different from the default register data and the original target register configuration data different from the default register data are recorded.

If the default register data and the target register configuration data are the same, the default register data is compared with the default register data. If the default register data is identical to the target register configuration data, the default register data is expressed as " 0 & And is used as information on the position and number of other data.

If the number of original target register configuration data other than the default register data is " n ", then " n + 1 "

The above-described timing controller and target register configuration data compression method according to the present invention has the following effects.

That is, since the target register configuration data is encoded (compressed) in the external nonvolatile memory storing the original target register configuration data and stored, the capacity of the external nonvolatile memory can be reduced and the data can be read from the external nonvolatile memory Access time can be reduced.

1 is a schematic diagram of a general liquid crystal display device
Fig. 2 is a specific configuration diagram of the timing control section of Fig.
3 is a specific configuration diagram of the timing control unit according to the present invention
4 is an explanatory diagram for explaining a method of compressing target register configuration data according to the present invention;

A method of compressing a timing controller and a target register configuration data according to the present invention will now be described in detail with reference to the accompanying drawings.

3 is a specific configuration diagram of a timing control unit according to the present invention.

Since the basic operation of the timing controller 8 is the same as that described with reference to FIG. 1, it will be omitted.

As shown in Fig. 3, the timing controller 8 according to the present invention includes a timing controller 8a and an external nonvolatile memory 8b.

The timing controller 8a includes a register 8c for storing a default register data value for timing control and option setting and a register 8c for storing a value And a decoder 8d for decoding the target register configuration data.

The external nonvolatile memory 8b stores the target register configuration data, which is not the target register configuration data for controlling the above operation, but the encoded target register configuration data.

The timing control unit 8a reads the target register configuration data from the nonvolatile memory 8b and loads the target register configuration data into the internal register 8c and uses the decoder 8d to convert the encoded target register configuration data into original data .

The encoding of the target register configuration data to be stored in the external nonvolatile memory is performed using a separate PC.

FIG. 4 is an explanatory diagram illustrating a method of encoding (compressing) target register configuration data to be stored in an external non-volatile memory of a timing controller according to the present invention.

Compression is performed by comparing the default register data stored in the internal register of the timing controller with the target register configuration data and storing only the target register configuration data having different values in the external nonvolatile memory.

To do so, a changed byte flag of 1 byte per register address of 8 bytes is used to recognize the target register configuration data different from the default register data.

Thus, the encoded (compressed) data size due to the addition of the variable byte flag has a range of 12.5% to 112.5% of the original data.

That is, if the default register data and the target register configuration data are the same, the encoded data size is 12.5%. If the default register data and the target register configuration data are different, the encoded data size is 112.5%.

Therefore, the compression on / off option is used to prevent the encoded data size from becoming larger than the original data size.

A compression (encoding) method according to the present invention will now be described with reference to specific embodiments.

An example of the default register data and the target register data is shown in Fig.

Addresses 0-7 are interface option data & checksum (head pocket), and the following addresses are main data and checksum.

As described above, the compression on / off option is recorded in the address 3 of the option data and the checksum, and the compression method selection is recorded in the address 4.

If the default register data and the target register configuration data are equal to each other, the default register data is compared with the default register data by 8 bytes. If the default register data and the target register configuration data are the same, they are expressed as " 0 & The location information of other data is recorded, and the other data is recorded separately.

 That is, when the 8 byte default register data of address 8-15 is compared with the target register configuration data, data of addresses 10 and 12 are different from each other in FIG. Therefore, if the default register data and the target register configuration data are the same, they are represented as " 0 "; otherwise, they are represented as " 0010 1000 " This means that the 3rd and 5th bytes out of the 8 bytes are different from the default register data, and if they are expressed in hexadecimal, it becomes "28". Therefore, the encoded data is recorded at address 8 as " 28 ", and the target register configuration data at addresses 10 and 12 is recorded at addresses 9 and 10 as " 20 "

The meaning of " 28 (0010 1000) " indicates that the other data are two and the positions are the third and fifth. That is, the position and the number of other data are the information.

As such, if the other data are two, a total of 3 (2 + 1) pieces of address data indicate the next variable byte flag.

If it is assumed that the other data is 4 and the data is different from the 3rd to 6th, it is indicated as "0011 1100", and if it is set to hexadecimal, "3C" will be recorded as the position and the number information. Since other data are sequentially recorded, it indicates that a total of 5 (4 + 1) pieces of address data is the next variable byte flag.

When the 8-byte default register data of address 16-23 is compared with the target register configuration data in the same manner as described above, data of addresses 19 and 22 are different from each other in FIG. Therefore, this means that the fourth and seventh bytes of the 8 bytes are different from the default register data, and are represented by " 0001 0010 ". If it is displayed in hexadecimal, it becomes "12". Therefore, the encoded data is recorded with address " 12 " at address 11 and the positional information of other data is recorded, and the target register configuration data at addresses 19 and 22 are written at addresses 12 and 13 as " 30 "

This process is repeated to encode (compress) the original target register configuration data and store it in the external nonvolatile memory.

Since the target register configuration data is encoded (compressed) in the external nonvolatile memory storing the target register configuration data and thus stored, the capacity of the external nonvolatile memory can be reduced, and the access to read the data from the external nonvolatile memory Time can be reduced.

On the other hand, the timing controller reads the target register configuration data encoded and stored as described above from the external nonvolatile memory, loads the register into the register, restores the original target register configuration data using the decoder sd, Timing control and option setting according to the data.

That is, the decoder reads the data stored in the first address in the one variable byte flag, converts the data into binary numbers, recognizes the number of data different from the default register data according to the number of " 1 " The data of the corresponding position in the default register data is replaced with data of the next address in accordance with the position of " 1 " from the binary number 8 bytes to restore the original target register configuration data.

8: Timing controller 8a: Timing controller
8b: external nonvolatile memory 8c: register
8d: decoder

Claims (7)

An external non-volatile memory for storing the encoded target register configuration data,
And a decoder for decoding the target register configuration data stored in the external nonvolatile memory, wherein the decoder is configured to decode the target register configuration data using the decoded target register configuration data, And a timing controller for controlling the data driver. The method according to claim 1,
Wherein the encoded target register configuration data stored in the external non-
The target register configuration data different from the default register data, and the location information of the other original target register configuration data. Comparing the default register data with the original target register configuration data in units of a predetermined number of bytes;
Storing location and number information of an original target register configuration data different from the default register data; And
And storing the target register configuration data different from the default register data in order. The method of claim 3,
The compressed target register configuration data format is divided into interface option data checksum and main data checksum,
The interface option data checksum records compression on / off options and compression method selection information,
Wherein the main data checksum records the location and number information of the original target register configuration data different from the default register data and the original target register configuration data different from the default register data. The method of claim 3,
If the default register data and the target register configuration data are the same, the default register data is compared with the default register data. If the default register data is identical to the target register configuration data, the default register data is expressed as " 0 & Wherein the target register configuration data is converted into a hexadecimal number and used as position and number information of other data. The method of claim 3,
And when the number of original target register configuration data other than the default register data is " n "," n + 1 " is a flag. Storing the position and number information of the target register configuration data different from the default register data by comparing default register data for timing control and option setting with target register configuration data in units of predetermined bytes, An external nonvolatile memory for storing target register configuration data in order to encode the target register configuration data and storing the encoded target register configuration data,
A register for storing the default register data value,
And a decoder for decoding the target register configuration data encoded and stored in the external nonvolatile memory,
And a timing controller for controlling the gate driver and the data driver using the decoded target register configuration data.

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