KR101972917B1 - A power saving method of a computer system by automatically controlling registry setting values according to the idle resource - Google Patents

Abstract

In the present invention, when the OS is booted and stabilized, the value of the Registry is optimized according to the system idle resources by checking the status of the current system during the operation of the computer system, dropping the CPU speed constantly, removing unnecessary processes, The present invention provides an energy saving method for automatically controlling a registry setting value in accordance with computer idle resources for saving energy by a management program. The ATX power connector is supplied with power from the SMPS through the ATX power connector, ) Is activated, the SIO 19 recognizes and propagates it; A chipset 14 informing the SIO 19 of a current power state (mode); A ROM BIOS 10b for programming through the chipset 14 to output the SIO 19 according to the current mode; A power switching component 140 for supplying a power source 5VSB_PWR supplied from the ATX power connector 60 to elements on the main board; (S3 mode) or idle state by notifying the OS 10c of the job and the process currently in process from the job DB 13 of the current job DB and the process DB, A window operation manager 130; And a registry management tool 150 for setting an environment variable 151 according to an instruction of the OS 10c so as to perform optimal power saving; And a control unit.

Description

[0001] The present invention relates to an energy saving method for automatically controlling a registry setting value according to a computer idle resource,

The present invention relates to a technique for reducing the power consumption of a power supply unit supplied to a main board and a peripheral device of a computer, and more particularly to a technique of automatically controlling a registry setting value according to a computer idle resource, The present invention relates to an energy saving method for automatically controlling a registry setting value in accordance with computer idle resources for saving energy by a management program that optimizes a memory capacity of a computer.

1, a power supply 20 such as an SMPS is connected to the SIO 12 of the main board 10 through 24 pins, one of which is connected to a standby Voltage (+ 5VSB).

When the user presses the power switch (not shown) of the PC case, the mechanically connected power button 13 is pressed, the power button 13 sends the first signal PWRBTN # to the SIO 12, The power supply 20 activates the power-on signal line PSON # with the power supply 20 and issues the second signal PWRBTN # _SB to the chipset 14. The power supply 20 is connected to the CPU 11 ) And the chipset 14 to inform it of the power supply signal, and then supply power to the main board.

Reference numeral 15 denotes a reset button of the chipset, 16 is a battery, 17 is a reset reset (17), and 18 is a LAN. In addition, AC, FWH, Super IO 19, AGP slot, PCI slot, IDE connected to the CPU and the chipset are connected.

Meanwhile, as described above, +5 V standby power is applied between the power supply 20 and the main board during non-operation, and standby power of about 1 W is required for recognizing the start button and recognizing the remote start do.

And this leads to a waste of energy, which is never high individually, and a huge amount of energy for a whole organization and even for a whole country.

In order to solve such a problem, there has been developed a socket having a switch which completely cuts off the power supply from the power socket itself to make the standby power zero (first prior art). On the other hand, Korean Patent Publication No. 2013-0043923 (Second conventional technique) for recognizing the on / off state of the power switch to completely shut off the power supply, such as the power supply device and the image forming apparatus including the power supply device.

However, in the case of the first prior art, in spite of the fact that it is practically possible for the user to sit in the outlet without turning off the power supply completely disconnected from the outlet, the second prior art is very complicated and expensive It is indispensable to mount such a device on a general PC.

Accordingly, the present inventor has proposed a computer power supply apparatus which is very simple but minimizes standby power automatically, and proposed Korean Patent No. 1328393 (name: computer power supply apparatus whose standby power is reduced) This will be described as a third prior art.

As shown in FIG. 2, the third prior art technology has a CPU 11, an SIO 12, a power button 13, a chipset 14, a reset button 15, a first battery 16, a LAN 18 ) And a super IO (19); An SMPS (20) for supplying power to the main board; A microcomputer 30 for controlling standby power supply of the SMPS; A power connector 60 for mediating signal and standby power connection between the main board and the SMPS; And a switching unit (40) for switching standby power on / off according to the control of the microcomputer. And the microcomputer 30 controls the standby power supplied to the main board by controlling the standby power (5VSB) of the power supply by the switching unit 40. [

2, the power supply apparatus of the third prior art includes an existing CPU 11, an SIO 12, a power button 13, a chipset 14, a reset button 15, A main board 10 having a power supply 16, a resetting reset 17, a LAN 18, a super IO 19, and the like, an SMPS 20 for supplying power to the main board, And a switching unit 40 for switching the standby power on / off according to the control of the microcomputer 30 and the microcomputer. The reference numeral 50 denotes a power switch of the PC case, and 60 denotes a power connector between the main board and the SMPS.

In the third prior art, the power connector 60 mediates signal and standby power connection between the main board 10 and the SMPS 20, and the SMPS 20 and the power connector are connected with 23 pins 1 is different from the conventional power supply of FIG. 1 in that a + 5V standby power line (+ 5VSB) which is one pin instead of a power connector is connected to the microcomputer 30 and the switching unit 40 instead of the power connector. The switching unit 40 may be a power switch IC or an FET circuit.

In addition, the microcomputer 30 receives the signal of either or both of the SMPS good signal (PS_ON #) and the power good signal (PWR_ON) from the SMPS 20 from the SMPS 20. The power good signal PWR_ON is also applied to the CPU 11 and the chipset 14.

Meanwhile, the microcomputer 30 also starts the standby power supply start operation by the switching signal CASE_PWR_BTN from the external case power switch 50, so that the standby power of +5 V (+ 5VSB) When the control signal 5VSB_SW of the microcomputer 30 is 'ON', the switching unit 40 applies the 5V standby signal P5V_STBY to the main board 10 through the switching unit 40, And the + 5V standby power (+ 5VSB) from the SMPS 20 is applied to the main board 10 as the 5V standby signal P5V_STBY.

From the SMPS (20) power connector to the mainboard (10) power connector, the PC's normal operating power goes to + 12V and -12V lines, + 5V standby power lines, + 3.3V power lines, and power hardening (PWR_ON) signals. However, the 5V standby power line (5VSB) goes to the switching device (40), and the standby power signal (P5V_STBY) goes from the switching device (40) back to the main board power connector.

Further, the standby power switch signal 5VSB_SW from the microcomputer 30 to the switching unit 40 and the power button signal MB_PWR_BTN to the main power button 12 go.

Conversely, the SMPS good (PS_ON #) signal goes from the mainboard 10 power connector to the SMPS 20 power connector.

First, the microcomputer 30 of the third prior art controls the standby power (5VSB) of the power supply by the switching unit 40 so as to control the power supplied to the main board When the power is off, the microcomputer senses the power cord PWR_ON and / or SMPS good signal (PS_ON #) between the connectors, and turns off the 5V standby power when the power is off. That is, in this case, since standby power is not supplied to the main board, the computer can not be turned on.

On the other hand, when the PC user presses the case power switch 50, the microcomputer 30 of the third prior art is activated by this signal, and the microcomputer controls the power good PWR_ON and / or the SMPS good PS_ON # And when the power is on, the control signal 5VSB_SW to the switching unit 40 is turned on so that the 5V standby power source 5VSB is applied to the main board. When the power button 13 of the main board is turned on, an input / output start command is issued to the SIO 12, and the SIO 12 transmits power supply completion signal PS_ON # to the SMPS 20 via the power connector 60. [ The SMPS transmits the PWR_ON signal to the main board 10 via the connector 60 and activates the main board operation power source (+12 V) when the situation is normal.

Therefore, according to the third prior art, standby power and computer start-up can be performed only by standby power of about 0.1 W corresponding to the standby power of the microcomputer without consuming standby power of 1 W corresponding to standby power of the computer activation system There are advantages.

Unlike conventional systems that only have the system power 'on' and 'off' states, modern PCs adopt the S1 to S5 mode, adopting various granular modes and thus the most efficient System operation. For reference, the S0 mode is a computer operation mode, the S1 mode is a state in which the processor is in an idle state and is in a low power supply state or a state in which power is still supplied to the RAM, and S2 mode is a deep sleep mode However, in the S3 mode (power saving / standby mode), the power is still supplied to the RAM. In this case, the + 5V SB should not be turned off as the data is stored in the memory and the minimum power is maintained. At this time, depending on the type of DDR memory, VDD power is maintained at 1.2 ~ 1.5V, but power is supplied only to some parts such as memory and RTC. On the other hand, in S4 mode (hibernate mode), the data is stored on the hard disk and all the system power is turned off. That is, it is almost the same as the power OFF state. At this time, VDD power of memory is output as 0 V as when power is OFF. In other words, the VDD signal is 0 V in the OFF state of the system standby power and in the case of the S4 mode, and the system operation which is the standby power ON condition (Power ON state) and S3 (power saving / standby mode), the VDD signal outputs 1.2 to 1.5V.

Therefore, in the case of the system having the recent S0 to S5 mode, in the case of the third prior art, it is necessary to check all the states of the power source in order to block such standby power. 2) Checking some signals such as 'power good', and checking them. 1) When checking the current, an expensive analog-to-digital converter (ADC) and a peripheral circuit are required There is no cost-effective value to reduce standby power of 1W. 2) Also, when checking through signals such as 'power good', all power can not be checked by one signal. Therefore, Structure, which leads to a problem of low production efficiency.

On the other hand, a conventional general power-on operation will be described with reference to Figs. 3 to 7. Fig.

3, the PS_ON circuit 19a in the super IO 19 recognizes the power ON state when the power button is turned on, as shown in FIG. 3, The PS_ON # terminal of the 20-pin connector of the SIO 12 of the main board 10 is activated while communicating with the south bridge of the chipset 14 so that power is applied to the main board 10.

An example of the block diagram of the PS_ON circuit 19a of FIG. 3 is shown in detail in FIG. 4, when the switch S1 corresponding to the power button is pressed, the PS_ON circuit 19a is activated while falling to a low level, so that various voltages are applied from the SMPS to the main board (See the timing chart of Fig.

On the other hand, FIG. 6 shows another example of a conventional power-on operation concept. When power-on switching (PWR) is performed, the chipset 14 transmits the P.ON signal to the SIO 12, And the SIO 12 outputs the PON signal to the PS_ON # terminal of the connector of the main board so that the power is applied from the SMPS to the main board.

FIG. 7 is a timing chart of the signals of FIG. 6, and when the VAC is activated (AC power is applied), the PS_ON # signal is activated while falling to a low level and various voltages are applied from the SMPS to the main board, It responds with a good signal.

6, the PS_ON # signal (SMPS power on) is also turned on first by turning on the + 5V SB signal and then by connecting the south bridge and the Super I / O chipset , The PS_ON # signal is generated in the SMPS, and the connection and remodeling workability of the cable is poor, resulting in low productivity.

In order to solve the above problems, the inventor of the present invention has proposed a computer power supply apparatus which is very simple and automatically minimizes standby power even in a computer system having various operation modes, And proposed a computer power supply device that reduces standby power and has been patented as a patent No. 1623756. [ This will be described with reference to FIG. 2 and FIGS. 8 to 10. FIG.

FIG. 8 is a block diagram of a computer power supply apparatus in which standby power is reduced according to a fourth conventional technique, FIG. 9 is a detailed circuit diagram of a computer power supply apparatus in which standby power is reduced according to a fourth conventional technique, 4 is a flowchart of the operation of the microcomputer of the computer power supply apparatus in which the standby power according to the related art is reduced.

First, the invention of the fourth related art will be described with reference to the block diagram of FIG. 8. First, it is detected whether the PC power source 50 is 'on', and the ATX power cable from the SMPS 20 to the main board Activate the PS_ON # signal to the 'low' level, causing the line except the 5V SB line to go to the mainboard. At this time, the 5V SB line does not go directly to the main board but provides Vcc to the microcomputer 30 and the first switching unit 40 and activates them, thereby activating the power control signal PWR_CTRL, The first switching unit 40 sends the power output signal PWR_OUT to the 5V SB terminal of the mainboard so that the main board is operated while all the power is supplied to the main board do.

At this time, the microcomputer 30 applies the PS_ON # signal to the SMPS 20 to turn on the SMPS, and the signal and the common ground signal interlocked therewith are transmitted from the SMPS to the main board 10 via the ATX cable, The microcomputer 30 may directly supply the PS_ON # signal to the main board through the second switching unit 41 without passing through the SMPS, as shown in FIG. 8, , But it is also possible to apply it to the PS_ON # terminal of the power connector 60 through the power button 13, the PS_ON circuit 19a, and the main board.

9, the on / off state of the PC power 'on' switch 50 is provided through the switching input (SW_IN) terminal (pin 16 of the chip) of the microcomputer 30 .

Thereafter, the microcomputer 30 activates the common ground terminal (turns from 'high' to 'low') so that all of the 5V, 3.3V, 12V, power cord (PWR_OK) So that various powers are applied from the SMPS to the main board. In addition, the PS_ON # signal may be output to the SMPS 20 through the PS_ON # terminal (pin 2 of the chip) and may be connected to the corresponding terminal of the power connector 60 of the main board 10 through the ATX power cable 9, the SW_OUT signal is output to the second switching unit 41 through the fifth terminal of the microcomputer, and the switching signal is output to the super IO 19 through the power button # 13 in the main board To the corresponding terminal of the power connector 60 by activating the PS_ON circuit 19a.

The power control signal PWR_CTRL is output through the 14th pin of the microcomputer 30 to activate the first and third transistors Q1 and Q3 of the switching unit 40 to output the power output PWR_OUT signal To the 5V standby signal terminal of the connector of the main board 10. This means that the main board (computer) including the function of the memory finally operates.

Lastly, the voltage supplied to the memory (for example, DDR3) of the main board 10 is sensed by the fourth transistor Q4 of the sensing unit 70, and the result is the power GD_PWR Pin 15 of the chip).

The operation of the microcomputer of the fourth conventional art will be described once again with reference to FIG.

First, the microcomputer 30 of the present invention is operated when the system standby power is in the off state (in a state in which the AC power is not inputted). (S1). In such a case, is the PC power switch "on"? The power control signal PWR_CTRL (PWR_CTRL) is set to the power control signal PWR_CTRL (step S2). If the power control signal PWR_CTRL The switching unit 40 sends the power output signal PWR_OUT to the 5V SB terminal of the mainboard so that all the power is supplied to the main board S3). At the same time, the power button # 13 is activated and the PS_ON # signal is activated to operate the main board (S4 ').

That is, the microcomputer 30 receives a signal that the PC power switch is 'on', activates the power control signal PWR_CTRL to the first switching unit 40, and outputs the power output signal PWR_OUT) to the 5V SB terminal of the main board to supply all the power to the main board (S3) and to output the switching-out signal (SW_OUT) to another second switching unit 41 The transistor Q2 of the second switching unit 41 is turned on and the PS_ON # signal is applied to the power button 13 of the main board so that the power button 13 and the super I / The PS_ON # terminal of the connector 60 is activated through the PS_ON circuit 19a of the controller 19 to operate the main board (S4 ').

Thereafter, the voltage V _DD supplied to the memory 10a of the main board is checked (S5), and it is determined whether it is less than a predetermined voltage (for example, 0.7 V) (S6). If the voltage is abnormal ), The 5V SB power 'on' state is maintained and power supply to the main board is continued. Otherwise, the memory is considered to have stopped operating, and the power control signal PWR_CTRL is deactivated, The switching unit 40 disables the power output signal PWR_OUT and turns off the system standby power in step S7.

That is, as described above in the related art, the + 5V SB should not be turned off in the S3 mode (power saving / standby mode), while in the S4 mode (the maximum power saving mode) Turn off all power. That is, in the S4 mode and the S5 mode in which the power is OFF, 0V is output. In other words, the VDD signal is 0 V in the OFF state of the system standby power and in the case of the S4 mode, and the system operation which is the standby power ON condition (Power ON state) and S3 (power saving / standby mode), the VDD signal outputs 1.2 to 1.5V. Therefore, in S5 and S6, the voltage V _DD supplied to the memory is checked (S5), and it is determined whether or not it is less than a predetermined voltage (Vr: 0.7 V, for example) The power 'on' state is maintained, and less than (V _DD ≪ Vr), the system standby power is turned off (S7).

The fourth prior art recognizes the S3 and S4 modes by a relatively simple method of checking the voltage (V _DD ) supplied to the memory and continues to supply the 5V standby power in the S3 mode, In the S4 mode, the standby power is cut off to save power in the dash mode. However, there is an advantage that it can be performed without additional cable construction.

However, in S3 (standby / power saving mode), there is no need to supply a standby power of 5 V, and only a standby power of about 3 V is sufficient. However, the fourth prior art does not provide such a standby power supply.

In addition, in the above-mentioned conventional techniques, since the mode recognition such as S3 and S4 is checked with a voltage in a secondary device such as a memory, a separate device for checking the mode is necessary. In addition, A wiring to the microcomputer and a separate cable are required. In addition, although the possibility is very low, there is a problem that the system can not accurately sense the inconsistency between the secondary device such as the current mode and the memory due to the error of the system.

In order to solve the above problems, the present inventor has proposed a power saving apparatus and method for a computer system using a GPIO port, and a computer system utilizing the same, in order to save energy in various operation modes, Korean Patent Application No. 2016-0087595 ) (Hereinafter referred to as "fifth prior art").

First, an embodiment of a method and an apparatus for measuring the operating state of the computer system of the fifth conventional technique will be described with reference to Figs. 11 to 13. Fig.

Fig. 11 is a system configuration diagram of a fifth prior art system, Fig. 12 is a system configuration diagram showing only related components among systems of a fifth prior art system, Fig. 13 is a system configuration diagram of a superconducting Fig.

11 and 12, the power saving apparatus of the fifth prior art computer system includes a first switching unit 40 between the super IO 19 and the ATX power connector 60 on the main board, And a second switching unit 41 is added between the super IO 19 and the chipset (PCH) 14.

As shown in FIG. 2, the power supply in the general computer system is performed through a power supply such as the SMPS 20 through the ATX power connector 60 to the main board 10, for example, through a 5VSB power line The power saving is performed through a device such as the microcomputer 30 that performs appropriate control.

11, the super-IO 19 receives power from a power supply such as the SMPS 20 through the ATX power connector 60. More specifically, the power button 13 The power state detector 19b in the super IO 19 recognizes it and outputs a power on signal PWRON # to the chipset 14. In response, the chipset 14 receives the power on signal from the super IO 19, The power state detector 19b in the super IO 19 responds to the current power state (mode) via the SLP_4 and SLP_3 signal line terminals via the first switching unit 40 and the ATX power connector 60 to start the super IO 19 operation.

On the other hand, in the case of the fifth conventional technique, when the power state detector 19b in the super IO 19 recognizes activation of the power button 13 and outputs a power on (PWRON #) signal to the chipset 14, In response to this, the point of grasping the current power state (mode) through the 'SLP_4' and the 'SLP_3' signal line terminals from the chipset 14 is the same as in the prior art. In the fifth conventional technology, And are programmed to perform different operations. For reference, generally, the Super IO chip has about 50 general purpose input output (GPIO) ports, which can be programmed to a specific purpose port by the BIOS, Technology will use the 'GPIO A' port and the 'GPIO B' port.

The power state detector 19b of the super IO 19 determines whether the current power state is the S4 mode (the maximum power saving mode) through the SLP_4 signal line terminal from the chipset 14, L 'signal to the control terminal of the third transistor Q3 of the first switching unit 40 through the port of the ATX power connector 60 and at the same time the super IO 19 activates the PSON # . The signal 5VSB_ATX of the output terminal OUT of the first switching unit 40 is turned on by the switching operation of the third transistor Q3 and the first transistor Q1 of the first switching unit 40, (5V) voltage is applied to the PMOS 10d and is therefore applied to the PMOS 10d and the LDO 10e, which are a kind of voltage regulators. The 5VSB, which is the output of the PMOS 10d, becomes the first operating power of the system, 2 switching unit 41 and the output 3VSB of the LDO 10e is applied to the operation power source of the super IO 19 as the second operation power. Therefore, by using the super IO chip 19 and the 'GPIO B' port, it is possible to save power when the computer system is started, without using any additional device as compared with the prior art.

Subsequently, the super IO 19 determines whether the current power state is proceeding to the S3 mode (power saving / standby mode). If the current power state is S3 through the 'SLP_3' signal line terminal from the chipset 14, L "signal to the input side of the second switching unit 41 through the 'GPIO A' port of the super IO 19 when the mode is determined to be a power saving / standby mode, The switching unit 41 applies the output of the second switching unit 41 to the power supply terminal (3VSB / 5VSB terminal) of the super IO and the chipset 14 and the 'PWRBTN #' terminal of the chipset with the low voltage (3VSB) do.

At this time, when the 'H' signal is input to the input side by the peripheral devices such as resistances R3 to R5 and the capacitors C2 to C3 and the voltage regulator 41a, the second switching unit 41 In this case (power saving / standby mode), if only the minimum power supply is maintained and high voltage of 5V is not needed, it is controlled by low voltage (3VSB) so that the high voltage (5VSB) The total power consumption can be saved.

Subsequently, the super I / O 19 determines whether the current power state proceeds to the S3 mode (power saving / standby mode) and then proceeds to the operation mode S2 or less (i.e., S0 (computer operation mode) (Hereinafter, referred to as an 'S2 mode or an operation mode'), the current power state is switched to the mode S2 or less through the 'SLP_3' signal line terminal from the chipset 14 H 'signal to the input side of the second switching unit 41 through the' GPIO A 'port of the super I / O 19 when it is determined that the first switching unit (operation mode) 41 is applied to the power supply terminal (3VSB / 5VSB terminal) of the super IO and chipset 14 and the 'PWRBTN #' terminal of the chipset with the output of the second switching unit 41 being a high voltage (5VSB).

On the other hand, if the current power state (mode) is determined through the SLP_4 and SLP_3 signal line terminals from the chipset 14 and the SLP_4 is 'L', the computer system is already in the hibernation mode H 'at the input side of the second switching unit 41 through the' GPIO A 'port. If the' SLP_3 'signal line is' H', the system is woken up. Signal to the power supply terminal (3VSB / 5VSB terminal) of the super IO and chipset 14 and the 'PWRBTN #' terminal of the chipset by setting the output of the second switching unit 41 to a high voltage (5VSB) do.

Of course, when the current power state (mode) is determined through the SLP_4 and SLP_3 signal line terminals from the chipset 14 and the SLP_4 is L and the SLP_3 is L, H 'signal to the input side of the second switching unit 41 through the' GPIO A 'port and outputs the output of the second switching unit 41 to the high voltage (5VSB) .

Finally, since the computer system is operating as described above, the 'H' signal is continuously output to the input side of the second switching unit 41 through the 'GPIO A' port to output the output of the second switching unit 41 to the high voltage The power state detector 19b of the super IO 19 controls the third transistor Q3 of the first switching unit 40 via the GPIO B port, The output terminal of the first switching unit 40 is turned on by the switching operation of the third transistor Q3 and the first transistor Q1 of the first switching unit 40, The zero voltage (0V) is applied to the signal 5VSB_ATX of the output terminal OUT and the output of the PMOS 10d and the LDO 10e also becomes 0 V. Eventually, the operation of the super IO 19 is turned off, By using the super IO chip 19 and the ' GPIO B ' port, It is possible to prevent the power consumption at an early stage in the end of the system, thereby enabling the overall power saving.

Now, a power saving method of a computer system using the GPIO port of the fifth prior art will be described with reference to FIGS. 11 to 13, particularly with reference to FIG.

13, when the computer system is started, the power state detector 19b in the super IO 19 checks whether a power on (PWRON #) signal is generated (S11), and a power on (PWRON # SLP_4 "and" SLP_3 "signal lines from the chipset 14 in response to the power on (PWRON #) signal, if the power on (PWRON #) signal has not been generated (for example, if the power button has not been turned on) The current power state (mode) is checked. First, it is checked whether the 'SLP_4' signal line from the chipset 14 is 'H' (S12).

The power state detector 19b of the super I / O 19 determines that the GPIO B port is connected to the GPIO B port because the current power state is determined to be the S4 mode (the maximum power saving mode) when the SLP_4 signal line is' A high voltage is applied to the signal 5VSB_ATX of the output terminal OUT of the first switching unit 40 by outputting an L signal to the first switching unit 40 through the first switching unit 40, At the same time, the super IO 19 activates the PSON # signal (S15) and outputs it to the ATX power connector 60 so that the super IO 19 is activated.

The super IO 19 checks whether the 'SLP_3' signal line from the chipset 14 is 'H' (S17) and determines whether the current power state goes to S3 mode (power save / standby mode) (SLP_3 = 'H') is determined to be the S3 mode (power save / standby mode) through the 'SLP_3' signal line terminal from the chipset 14, L 'signal to the input side of the second switching unit 41 through the' GPIO A 'port in step S18. The second switching unit 41 then outputs the output of the second switching unit 41 (3VSB / 5VSB) of the chipset 14 and the 'PWRBTN #' terminal of the chipset as the low voltage (3VSB).

Thereafter, the super IO 19 checks whether the SLP_3 signal line is 'L' (S19) after the current power supply state proceeds to the S3 mode (power saving / standby mode) GPIO A 'of the super IO 19 is determined to be in a mode (operation mode) under the current power state through the SLP_3 signal line terminal from the chipset 14, The second switching unit 41 outputs the output of the second switching unit 41 as a high voltage (5VSB) to the input side of the second switching unit 41 through the port To the power supply terminal (3VSB / 5VSB terminal) of the super IO and chipset 14 and the 'PWRBTN #' terminal of the chipset. This results in a successful boot.

On the other hand, if it is determined in step S17 that the 'SLP_3' signal line is not 'H', it is checked whether the PWR_OFF state is satisfied (S32) And if it is not (power off), it is determined to be a boot error (S33).

If the SLP_3 is not 'L' in step S19, it is determined that the booting process is out of the normal booting process. Therefore, the process proceeds to step S32. In step S32, If it is not power-off, the process proceeds to step S19 and repeats. If the power is off, it is determined as a boot error (S33).

On the other hand, if it is determined in step S12 that 'SLP_4' is 'L', it indicates that the boot has already been performed. In this case as well, it is determined whether the 'SLP_3' signal line is 'H' (Step S14). If the SLP_3 is 'L', it means that the mode is the mode S2 (operation mode). Accordingly, the process proceeds to step S20, and the 'GPIO A' H "signal to the input side of the second switching unit 41 through the port of the second switching unit 41 and the second switching unit 41 outputs the output of the second switching unit 41 as the high voltage (5VSB) To the power supply terminal (3VSB / 5VSB terminal) of the chipset 14 and the 'PWRBTN #' terminal of the chipset.

However, if it is determined in step S14 that 'SLP_3' = 'H', it indicates that the system is in the S3 mode (power save / standby mode) while booting after booting. , The process directly proceeds to step S20 and outputs 'H' signal to the input side of the second switching unit 41 through the 'GPIO A' port of the super IO 19. That is, in this case, since the S3 mode is the same as the step S18, the step S18 indicates a state of proceeding from the S2 mode or the S3 mode to the S3 mode, The process immediately goes to the step S20 and shifts to the operation mode.

Finally, when the booting has been successfully performed and the process proceeds to the sub-S2 mode (operation mode) (S11, S12, S1, S15, S17 to S20) (S21). If it is determined in step S21 that power-off is to be performed, GPIO = 'H', and output through the first switching unit 40 The system is terminated (S23). On the contrary, if the voltage is not turned off in the step S21, the process returns to the step S12 (S41) SLP_4 'and' SLP_3 'signal lines from the chipset 14 to determine whether to proceed with the next power state (mode).

As a result, according to the power saving method of the computer system using the GPIO port according to the fifth related art, the GPIO port of the super IO chip is programmed through the BIOS without any additional hardware or cable installation work, It is possible to easily detect the current operation state of the system by using only the software, and it is possible to save power at booting by using only the first switching unit 40. [

In addition, it is possible to save power by applying 3VSB operating voltage instead of 5VSB even in S3 mode during boot, and switch to 3VSB operating voltage immediately after S4 mode in operation, It is advantageous in that only the second switching unit 41 can have an effect without any additional sensing device or cable operation.

However, although the above fifth conventional technique also significantly reduces the number of new hardware additions compared to the prior art, nevertheless still requires a minimum amount of cable coupling to connect the first switching unit 40 and them , And the power saving is performed by being trapped in the existing frame of the existing main mode designers such as the S3 and S4 modes. Therefore, even when the standby power is unnecessary, the power saving can not be performed beyond the existing frame called the S0 to S5 mode Respectively.

In addition, there has been no attempt to realize optimal energy saving in each mode including the operation mode by controlling the set value of the registry according to the idle resources of the system during operation of the computer. In other words, although energy is saved in the idle mode or the long-term idle mode, for example, when some resources of the system are idle, an energy saving method of controlling the speed of the CPU or the brightness of the display language by 1 to 90% Was not attempted.

Korean Patent Publication No. 2013-0043923 (Patent Application No. 2011-0108115) Korea Patent No. 1328393 (name: computer power supply device for saving standby power) Korean Patent No. 1623756 (Title: Standby power cutoff method of standby power cutoff device using system memory power) Korean Patent Application No. 2016-0087595 (Title: Power Saving Device and Method of Computer System Using GPIO Port, and Computer System Utilizing the Same)

In the present invention, energy saving is implemented in each mode by checking the power off mode, the standby mode (S3), and the long-term idle mode during operation of the computer system. In the term idle mode, it detects the pixel change of the monitor, detects the current state of the system by keyboard or mouse input detection, drops the CPU speed to a fixed value (for example, 50% or more), removes unnecessary processes, When booted and stabilized, it provides an energy saving method that automatically controls registry settings according to computer idle resources, which helps to save energy by management programs that optimize the value of the registry based on system idle resources.

According to an aspect of the present invention, there is provided an energy saving method for automatically controlling a registry setting value according to computer idle resources, including a main board, an SMPS for supplying power to the main board, An energy saving device for a computer system, comprising: an SIO (19) receiving power from an SMPS via an ATX power connector (60) and recognizing and propagating power when the power button (13) is activated; A chipset 14 informing the SIO 19 of a current power state (mode); A ROM BIOS 10b for programming through the chipset 14 to output the SIO 19 according to the current mode; A power switching component 140 for supplying a power source 5VSB_PWR supplied from the ATX power connector 60 to elements on the main board; (S3 mode) or idle state by notifying the OS 10c of the job and the process currently in process from the job DB 13 of the current job DB and the process DB, A window operation manager 130; And a registry management tool 150 for setting an environment variable 151 according to an instruction of the OS 10c so as to perform optimal power saving; (B) a computer system is started and a main board is connected to the main board, and the main board is connected to the main board When activated, the OS 10c checks the CPU status registers and calls the window task manager 130 (S3); (c) after step (b), checking whether the current window is idle (S4); (d) If it is determined in the step (c) that the window is idle, the OS 10c calls the registry management tool 150 (S21) and saves energy (power consumption) Setting an environment variable to be optimal; (e) After the step (d), it is checked whether or not the environment variable value is returned from the registry management tool 150 (S22). If the value return is not made, A step of registering in the OS according to the value, and proceeding to the next step; (f) If the value returned from the registry management tool 150 in step (e) or the window is not idle as a result of the determination in step (c), the OS 10c sets a predetermined time (S5) of checking whether the CPU utilization rate has changed during the period T1); (g) If it is determined in step (f) that there is a change in the CPU utilization rate for a predetermined period of time, the process returns to step (b) (S6); (h) a step (P7) of checking again whether or not the change amount of the CPU utilization rate is less than X1% after the step (g); (j) , The 'registry optimization step 2' is performed (S8) to further restrict the performance of the CPU. (n) If it is determined in step (h) that the amount of change in the CPU utilization rate is X1% or more, it is regarded that wakeup has occurred and the registry is initialized (S10) ; (k) checking again (S9) whether or not the change amount of the CPU utilization rate is less than X2% after the step (n); (m) a step (S11) of performing the 'registry optimization step 3' if the change amount of the CPU utilization rate is less than X2% as a result of the determination in step (k); (n ') If it is determined that the amount of change in the CPU utilization rate is X2% or more as a result of the determination in step (k), the wakeup is considered to have occurred and the registry is initialized (S10) Starting; (v) the registry management tool 150 checks whether a registry management tool call is called from the OS 10c (S31); (w) checking if there is no call as a result of the determination in step (v), and (c) performing an environment variable call in the environment variable 151 if a call occurs; (y) setting (step S33) an environment variable to be optimal for saving energy (power consumption) after the step (w); (Z) After the step (y), the caller waits for an environment variable call back (S34). If the call back is made, the value return to the OS 10c (S35) ; And the registry management tool 150 may set the CPU performance and the display brightness value to 1% to 90% of the maximum value, respectively, in relation to the CPU performance and the display brightness setting In addition, The 'registry optimization step 1' sets the CPU performance to be limited to y1% of the maximum value as the 'POWER SCHEMES' registry optimization execution step, and the 'registry optimization step 2' , Where y1 is greater than y2 (90 > y1 > y2 > = 1) The 'registry optimization third step' is a step of setting the brightness parameter of the display language to be limited to z1% of the maximum value (90 ≥ z1 ≥ 1) .

Preferably, the registry management tool 150 can set a CPU performance and a display brightness value from 5% to 60% of a maximum value, respectively.

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Preferably, the method further comprises: (a) checking whether or not the power button 13 signal is input (S1) before the step (b), checking if the power button is not turned on, In response, the S1O 19 activates the system by applying a 'power ON' signal to the ATX power connector 60, with '5VSB_POWER' coming from the ATX power connector 60 through the power switching component 140 to the S1O 19, (S2) for supplying power to an element of the main board including the main board to activate the main board; And further comprising:
More preferably, (p) after step (m), the OS determines whether the system is in the idle mode (S12); (q) continuously checking if it is not the idle mode as a result of the determination in step (p), and if the mode is the idle mode, deactivating the PCIex_PD # signal to cause the peripheral device to transition to the deep sleep mode (S13); (r) After the step (q), it is checked whether the sleep mode is the S3 mode (S14). If it is not the sleep mode, it is continuously checked. If it is the sleep mode, Taking an action; And further comprising:
Most preferably, (s) the step (S15) of checking whether the power is turned off again after the step (r); And (t) if it is determined in step (s) that the power is not turned off, it is checked continuously. If the power is off, the SIO 19 issues a '5VSB_OFF' signal to shut off all the power sources and deactivate the main board Step S16; And further comprising:

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According to the energy saving method of automatically controlling the registry setting value according to the computer idle resource according to the present invention, the energy consumption is minimized by the management program that optimizes the value of the registry according to the system idle resource even during operation, It is possible to save power while using the application program, to perform the power saving function even in the short-term idle mode, and to provide the optimum energy saving environment in combination with the saving function in the existing OS, The program can be changed easily.

Other objects and advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the attached drawings.

1 is a conceptual diagram of a conventional computer power supply;
2 is a block diagram of a computer power supply in which standby power is reduced according to the third prior art.
3 is a view for explaining a concept of a conventional general power-on operation;
4 is a block diagram of the PS_ON circuit 19a of Fig.
5 is a timing chart of the signals of FIG. 3;
FIG. 6 is another example of a concept of a conventional general power-on operation; FIG.
FIG. 7 is a timing chart of the signals of FIG. 6; FIG.
FIG. 8 is a block diagram of a computer power supply in which standby power is reduced according to a fourth prior art; FIG.
FIG. 9 is a detailed circuit diagram of a computer power supply apparatus in which standby power is reduced according to a fourth prior art; FIG.
FIG. 10 is a flowchart illustrating an operation of a microcomputer of a computer power supply apparatus according to a fourth prior art in which standby power is reduced. FIG.
11 is a system configuration diagram of a fifth prior art.
12 is a system configuration diagram showing only related components among the systems of the fifth prior art;
Fig. 13 is a flow chart of the operation of the super IO of a computer system in which the power consumption of the fifth prior art is reduced. Fig.
FIG. 14 is a system configuration diagram showing only components directly related to the present invention among the systems according to the present invention; FIG.
15 is an operational flowchart of an OS among energy saving methods according to the present invention.
FIG. 16 is a flowchart illustrating an operation of a registry management tool among the energy saving methods according to the present invention. FIG.
17 is an example of CPU performance setting in the energy saving method according to the present invention.
18 is an example of the brightness setting of the displayer in the energy saving method according to the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, You will know.

(Example)

Hereinafter, an optimal embodiment of an energy saving method for automatically controlling a registry setting value according to the computer idle resources of the present invention will be described with reference to FIGS. 14 to 18. FIG.

FIG. 14 is a system configuration diagram showing only components directly related to the present invention among systems according to the present invention, FIG. 15 is an operation flowchart of an OS among energy saving methods according to the present invention, FIG. A flowchart of the operation of the registry management tool. FIG. 17 shows an example of CPU performance setting in the energy saving method according to the present invention, and FIG. 18 shows an example of brightness setting of the display in the energy saving method according to the present invention.

First, an energy saving apparatus for automatically controlling a registry setting value according to computer idle resources according to the present invention will be described with reference to FIG.

14, the computer system is started by receiving an on / off signal of the power button 13 and supplying a power-on switch (SIO) 19 to the SIO 19, The SIO 19 of the main board gives a 'power ON' signal to the ATPS power on connector 60 of the SMPS as a power supply, and the ATX power connector 60 of the main board, The power switching component 140 supplies 5VSB voltage (5VSB_POWER) to the system in response to the signal of the power button 13 so that the main board is booted up by supplying 5VSB voltage (5VSB_POWER) . Then, the main board is activated, and the 5VSB is applied to the SIO 19, the BIOS 10d, the PCH chipset 14, and the like.

On the other hand, the system off operation causes the SIO 19 to supply the " 5VSB_OFF " signal to the power switching component 140 to deactivate it.

In addition, the SIO 19 exchanges a CPU_Clock signal and a SYS_OFF signal with the OS 10c (at this time, the OS 10c provides a CPU_Clock_drop signal to the CPU 11). On the other hand, the ROM BIOS 10b and the PCH chipset (14) sends and receives signals through the SPI port and gives processor performance control signals (C0 to C7) to the CPU (11).

Meanwhile, the SIO 19 may apply a 'PCIex_PD #' signal to the PCI device 151 to shut off the power supply to the idle peripheral device.

On the other hand, the window operation manager 130 notifies the OS 10c of the current work and process from the job DB of the current operation DB and the process DB of the process DB, ) Or idle state to determine the registry environment for power saving.

The OS 10c reads the current task DB and the like through the window task manager 130 and determines the power saving policy through the administrator, According to the instruction of the OS 10c, the registry management tool 150 sets an environment variable 151 so that optimal power saving is performed.

Examples of the environment variables may include the CPU performance as shown in FIG. 17, and the brightness setting of the display of FIG. 18. That is, as shown in FIG. 17, the registry management tool 150 can set the CPU performance (speed) from 1% to 100%. In the first case of FIG. 17, the processor state minimum is set to 100% , The hexa code '00000064', the second case with the processor state minimum set to 70%, and the third case with the processor state minimum set to 1% As an example, it may be set to the hex code '00000001' (see the red underlined portion in FIG. 17).

In the case of FIG. 18, the display brightness is set to '50' as an example of the display brightness setting. In addition, 'dward: 00000001' is set as the brightness adjustable option, which indicates that brightness adjustment is possible, and 'dward: 00000000' in the last row indicates that brightness adjustment is not possible (See underlined red underneath).

In addition, there are various environment variables, and an example of the setting of environment variables is shown in the following [Table 1].

Example 1 Example 2 Example 3 Normal mode 100 100 100 Power Save Step 1 50 30 60 Power saving phase 2 5 10 15 CPUUSAGE 10 10 10 HDDUSAGE 300 300 300 DEFAULT_TIME (wait time) 60 60 60 Power Saver Entry Time 60 60 60

Now, an energy saving method for automatically controlling registry settings according to the computer idle resources of the present invention will be described with reference to FIGS. 14 to 16, particularly with reference mainly to FIG. 15 and FIG.

15, a computer system is started to check whether or not a power button 13 signal is input (S1). If the power button is not turned on, it is continuously checked. If a power button signal is generated, In response, the S1O 19 activates the system by applying a 'power ON' signal to the ATX power connector 60, with '5VSB_POWER' passing from the ATX power connector 60 through the power switching component 140 to the S1O 19 The main board is activated by supplying standby power to elements of the main board including the main board (S2).

Now, the OS 10c checks the CPU status registers and calls the window operation manager 130 (S3) to check whether the current window is idle (S4).

For example, the OS 10c may be configured such that the hard drive (HDD) and the processor (CPU) are idle for 90% or more during a given time period (1 minute) without user interaction with the mouse or keyboard (That is, if the standby processor is zero and the current CPU utilization is within 10%), then Windows is considered to be idle.

As a result of the determination in step S4, if it is determined that the window is idle, the OS 10c calls the registry management tool 150 (S21) and optimizes the environment variable to save energy (power consumption) .

Thereafter, an optimal environment variable 151 is set, and it is checked whether or not an optimum environment variable value is returned from the registry management tool 150 (S22). If a value return is not made, The process proceeds to the next step S5 while allowing registry binding in the OS according to the value.

If it is determined that the value returned from the registry management tool 150 or the window is not in the idle state as a result of the determination in step S4, it is checked whether or not the window is changed for a predetermined time T1 (for example, for 60 seconds) (S5). If there is no change for a predetermined period of time, the 'registry optimization step 1' is executed (S6). In this embodiment, the 'POWER SCHEMES' registry optimization is performed. As shown in FIG. 17, the performance of the CPU is limited to 1% to 90% (C0 to C7 mode). For example, the CPU performance is limited to 50%, 30%, or 60% as in the power saving phase 1 in Table 1.

If the amount of change is less than X1% (for example, 10%), it is checked whether the amount of change is less than X1% (for example, 10%) after step S6 (S8), the performance supplied from the CPU is further restricted. For example, as in the power saving step 2 in Table 1, the CPU performance is limited to 5%, 10%, or 15%.

Thereafter, it is again checked whether the change amount is less than X2% (for example, 10%) (S9). If the change amount is less than X2% (for example, 10% (S11). For example, as shown in FIG. 18, the brightness parameter of the display brightness is limited (for example, the brightness is limited to 50% of the maximum brightness).

On the other hand, if it is determined in step S5 that there is a change in the time T1, the process returns to step S3 and starts again from the beginning. If it is determined in step S7 and step S9 that the amount of change is equal to or greater than a predetermined value, The registry is initialized (S10), and the process returns to step S3 and starts again from the beginning.

The OS then determines whether the system is in the idle mode (S12). If it is not the idle mode, it continues to check. In the idle mode, the OS deactivates the signal 'PCIex_PD #' so that the peripheral device enters the deep sleep mode And further performs power saving (S13).

Subsequently, it is checked whether it is the sleep mode (S3 mode) (S14). If it is not the sleep mode, it is checked continuously. If it is the sleep mode, the operation necessary for the sleep mode including 'Suspended RAM' If the power is turned off, the SIO 19 issues a '5VSB_OFF' signal to turn off all the power sources and deactivate the main board (S16).

Finally, the environment variable setting operation of the registry management tool 150 will be described with reference to FIG.

If it is determined in step S4 that the window is idle, the OS 10c calls the registry management tool 150 in step S21, and the registry management tool 150 ) Should be set to optimize environmental variables to save energy (power consumption).

First, the registry management tool 150 checks whether there is a registry management tool call from the OS 10c (S31). If there is no call, the registry management tool 150 continuously checks. If the call is generated, (Step S32).

Thereafter, the environment variable is set to be optimal for saving energy (power consumption) (S33), the environment variable callback is waited for (S34), and when the callback is made, a value return is performed to the OS 10c S35), so that the registry in the OS 10c is mapped.

Therefore, according to the energy saving method of automatically controlling the registry setting value according to the computer idle resource according to the present invention, the energy consumption is minimized by the management program that optimizes the value of the registry according to the system idle resource even during operation, By setting the limits of resources automatically by the defined program, it is possible to save power while using the application program, save power even in short-term idle mode, And the program can be easily changed for an additional power saving function.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Of course.

(Prior art)
10: main board 10a: memory
10b: ROM BIOS 10c: OS
10d: PMOS (P-type MOS) 10e: LDO (Low Dropout Voltage Regulator)
11: CPU 12: SIO (System IO)
13: Power button 14: Chipset
15: reset button 16: first battery
17: RESET RESET 18: LAN
19: Super IO (Super IO) 19a: PS_ON circuit
19c: Power state detector
20: Power supply (SMPS) 30: Microcomputer
40: first switching unit 41: second switching unit
50: Case power switch 60: Power connector
70: V _DD sensing unit
(Invention)
130: Windows Task Manager 131: Task and Process DB
140: Power Switching Component
150: Registry Management Tool 151: Environment Variables

Claims (7)

An energy saving device for a computer system including a main board, an SMPS and a peripheral device for supplying power to the main board, wherein power is supplied from the SMPS via the ATX power connector (60) The SIO 19 recognizing and propagating; A chipset 14 informing the SIO 19 of a current power state (mode); A ROM BIOS 10b for programming through the chipset 14 to output the SIO 19 according to the current mode; A power switching component 140 for supplying a power (5VSB_PWR) supplied from the ATX power connector 60 to elements on the main board; (S3 mode) or idle state by notifying the OS 10c of the job and the process currently in process from the job DB 13 of the current job DB and the process DB, A window operation manager 130; And a registry management tool 150 for setting an environment variable 151 according to an instruction of the OS 10c so as to perform optimal power saving; And automatically controlling a registry setting value according to a computer idle resource using an energy saving device that automatically controls a registry setting value according to computer idle resources,
(b) When the computer system is started and the main board is activated, the OS 10c checks the CPU status registers and calls the window task manager 130 (S3);
(c) after step (b), checking whether the current window is idle (S4);
(d) If it is determined in the step (c) that the window is idle, the OS 10c calls the registry management tool 150 (S21) and saves energy (power consumption) Setting an environment variable to be optimal;
(e) After the step (d), it is checked whether or not the environment variable value is returned from the registry management tool 150 (S22). If the value return is not made, A step of registering in the OS according to the value, and proceeding to the next step;
(f) If the value returned from the registry management tool 150 in step (e) or the window is not idle as a result of the determination in step (c), the OS 10c sets a predetermined time (S5) of checking whether the CPU utilization rate has changed during the period T1);
(g) If it is determined in step (f) that there is a change in the CPU utilization rate for a predetermined period of time, the process returns to step (b) (S6);
(h) a step (P7) of checking again whether or not the change amount of the CPU utilization rate is less than X1% after the step (g)
(j) if the change in the CPU utilization rate is less than X1% as a result of the determination in step (h), performing the 'registry optimization step 2' (S8) to further restrict the performance of the CPU;
(n) If it is determined in step (h) that the amount of change in the CPU utilization rate is X1% or more, it is regarded that wakeup has occurred and the registry is initialized (S10) ;
(k) checking again (S9) whether or not the change amount of the CPU utilization rate is less than X2% after the step (n);
(m) a step (S11) of performing the 'registry optimization step 3' if the change amount of the CPU utilization rate is less than X2% as a result of the determination in step (k);
(n ') If it is determined that the amount of change in the CPU utilization rate is X2% or more as a result of the determination in step (k), the wakeup is considered to have occurred and the registry is initialized (S10) Starting;
(v) the registry management tool 150 checks whether a registry management tool call is called from the OS 10c (S31);
(w) checking if there is no call as a result of the determination in step (v), and (c) performing an environment variable call in the environment variable 151 if a call occurs;
(y) setting (step S33) an environment variable to be optimal for saving energy (power consumption) after the step (w); And
(z) After the step (y), the environment variable call back is waited (S34). When the call back is made, a value return is performed to the OS 10c (S35) ;
/ RTI >
The environment variable includes the CPU performance and the brightness of the display. The registry management tool 150 can set the CPU performance and the display brightness to 1% to 90% of the maximum value, respectively.
The 'registry optimization step 1' sets the CPU performance to be limited to y1% of the maximum value as the 'POWER SCHEMES' registry optimization execution step, and the 'registry optimization step 2' , Where y1 is greater than y2 (90 > y1 > y2 > = 1)
The 'registry optimization third step' is a step of setting the brightness parameter of the display language to be limited to z1% of the maximum value (90 ≥ z1 ≥ 1) And automatically controlling registry settings according to computer idle resources. The method according to claim 1,
Wherein the registry management tool (150) is capable of setting a CPU performance and a display brightness value from 5% to 60% of a maximum value, respectively, wherein the registry setting value is automatically controlled according to computer idle resources. delete The method according to claim 1,
(a) Before the step (b), it is checked whether or not the power button 13 signal is input (S1). If the power button is not turned on, the power button signal is continuously checked. 19 activates the system by applying a power ON signal to the ATX power connector 60 so that the 5VSB_POWER is transmitted from the ATX power connector 60 via the power switching component 140 to the main board Allowing the main board to be activated by supplying power to the device (S2);
And automatically controlling a registry setting value according to computer idle resources. 5. The method of claim 4,
(p) after the step (m), the OS determines whether the system is in the idle mode (S12);
(q) continuously checking if it is not the idle mode as a result of the determination in step (p), and if the mode is the idle mode, deactivating the PCIex_PD # signal to cause the peripheral device to transition to the deep sleep mode (S13);
(r) After the step (q), it is checked whether the sleep mode is the S3 mode (S14). If it is not the sleep mode, it is continuously checked. If it is the sleep mode, Taking an action;
And automatically controlling a registry setting value according to computer idle resources. 6. The method of claim 5,
(s) a step (S15) of checking whether the power is turned off again after the step (r); And
(t) If it is determined in step (s) that the power is not turned off, it is checked continuously. If the power is off, the SIO 19 issues a '5VSB_OFF' signal to turn off all the power sources and deactivate the main board (S16);
And automatically controlling a registry setting value according to computer idle resources. delete

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