KR101964897B1 - Memory apparatus based on low power circuit and operating method thereof - Google Patents

Abstract

There is provided a memory device in which a clock signal is allocated only in an actual operation period based on a logic circuit capable of low power programming. The apparatus includes: a clock processor for generating clock information based on at least one of a reference clock signal, a write operation signal, and a read operation signal; and a clock processor for performing at least one of the write operation signal and the read operation signal, And a core memory unit for performing at least one of a write operation and a read operation based on the activated clock information and outputting result data corresponding to the execution. At this time, the core memory unit is implemented with at least one logic circuit that is programmable associated with the write operation and the read operation.

Description

TECHNICAL FIELD [0001] The present invention relates to a memory device implemented as a low-power programmable logic circuit and a method of operating the memory device.

And more particularly, to a memory device in which a clock signal is allocated only in an actual operation period based on a logic circuit capable of low-power programming such as an ASIC (Application Specific Integrated Circuit) and its operation ≪ / RTI >

Low-power programmable logic circuits, such as application specific integrated circuits (ASICs), are being used in a variety of applications in that they allow easy circuit design as intended by the designer. Generally, a memory is essential when designing a circuit. When a memory is implemented using a logic circuit, a power and a clock signal are fixedly allocated. In this case, the power may be consumed while maintaining the clock even in the idle period where the memory does not actually operate, thereby causing unnecessary power consumption.

According to one aspect, a memory device is provided in which a clock signal is assigned only in an actual operation period based on a logic circuit capable of low power programming. The apparatus includes: a clock processor for generating clock information based on at least one of a reference clock signal, a write operation signal, and a read operation signal; and a clock processor for performing at least one of the write operation signal and the read operation signal, And a core memory unit for performing at least one of a write operation and a read operation based on the activated clock information and outputting result data corresponding to the execution. At this time, the core memory unit is implemented with at least one logic circuit that is programmable associated with the write operation and the read operation.

According to one embodiment, the clock processing unit includes: a first D flip-flop for outputting a first output signal corresponding to the input of the write operation signal based on the reference clock signal; and a second D flip- And a second D flip-flop for outputting a second output signal corresponding to the input of the read operation signal based on the read operation signal.

The clock processing unit receives 1 as a data signal when at least one of the write operation signal, the read operation signal, the first output signal, and the second output signal is 1, And a third D flip-flop that receives the data signal and generates the clock information in synchronization with a negative edge of the reference clock signal. In this case, the delay processing unit inputs the clock information to the core memory unit in a period in which the output signal of the third D flip-flop is 1.

According to one embodiment, the delay processing unit may delay the clock signal by one clock unit with respect to a period in which at least one of the write operation signal and the read operation signal occurs, and transmit the clock information to the core memory unit.

Here, the delay processing unit outputs to the core memory unit a third output signal that is a result of ANDing the reference clock signal and the clock information generated from the clock processing unit.

According to one embodiment, the logic circuit includes at least one of a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a Complex Programmable Logic Device (CPLD), and a Field Programmable Analog Array (FPAA).

According to another aspect, a method of operating a memory device is provided in which a clock signal is assigned only in an actual operation period based on a logic circuit capable of low-power programming. The method includes the steps of: generating clock information based on at least one of a clock signal, a write operation signal and a read operation signal, and a delay processing unit performing at least one of the write operation signal and the read operation signal Controlling the clock information to be activated in a period, and performing a write operation and a read operation on a core memory based on the activated clock information, and outputting result data corresponding to the execution .

According to an embodiment, the step of generating the clock information may include: outputting a first output signal corresponding to the input of the write operation signal based on the reference clock signal; Outputting a second output signal corresponding to an input of an operation signal, and generating the clock information based on at least one of the write operation signal, the read operation signal, the first output signal, and the second output signal Step < / RTI >

At this time, the step of generating the clock information may include: receiving 1 as a data signal if at least one of the write operation signal, the read operation signal, the first output signal, and the second output signal is 1, 0 is input as a data signal and the clock information is generated in synchronization with a negative edge of the reference clock signal. The step of controlling to activate the clock information may include the steps of: when the at least one of the write operation signal, the read operation signal, the first output signal, and the second output signal is 1, can do.

According to one embodiment, the step of controlling to activate the clock information may include: delaying the clock signal by one clock unit with respect to a period in which at least one of the write operation signal and the read operation signal occurs, Can be delivered to the department.

The step of controlling to activate the clock information may include: outputting a third output signal obtained as a result of ANDing the reference clock signal and the clock information generated from the clock processor to the core memory unit.

1 is a diagram showing a circuit configuration of a general memory device.
2 is a graph showing the operation of a memory device having a general structure.
3 is a block diagram illustrating a memory device in which a clock signal is assigned only in an actual operating period according to an embodiment.
4 is a diagram showing a circuit configuration of a memory device to which a clock signal is allocated only in an actual operation period according to an embodiment.
5 is a circuit diagram illustrating a detailed configuration of a clock processing unit of a memory device according to an embodiment.
6 is a graph illustrating an operation of a memory device to which a clock signal is allocated only in an actual operation period according to an exemplary embodiment of the present invention.
7 is a flow chart illustrating a method of operation of a memory device according to one embodiment.

It is to be understood that the specific structural or functional descriptions of embodiments of the present invention disclosed herein are presented for the purpose of describing embodiments only in accordance with the concepts of the present invention, May be embodied in various forms and are not limited to the embodiments described herein.

Embodiments in accordance with the concepts of the present invention are capable of various modifications and may take various forms, so that the embodiments are illustrated in the drawings and described in detail herein. However, it is not intended to limit the embodiments according to the concepts of the present invention to the specific disclosure forms, but includes changes, equivalents, or alternatives falling within the spirit and scope of the present invention.

The terms first, second, or the like may be used to describe various elements, but the elements should not be limited by the terms. The terms may be named for the purpose of distinguishing one element from another, for example without departing from the scope of the right according to the concept of the present invention, the first element being referred to as the second element, Similarly, the second component may also be referred to as the first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Expressions that describe the relationship between components, for example, "between" and "immediately" or "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, the terms "comprises ", or" having ", and the like, are used to specify one or more of the features, numbers, steps, operations, elements, But do not preclude the presence or addition of steps, operations, elements, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the meaning of the context in the relevant art and, unless explicitly defined herein, are to be interpreted as ideal or overly formal Do not.

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. However, the scope of the patent application is not limited or limited by these embodiments. Like reference symbols in the drawings denote like elements.

1 is a diagram showing a circuit configuration of a general memory device 100, which is a conventional memory implemented using a programmable logic circuit.

Referring to FIG. 1, a memory device 100 may be implemented using a standardized core library. The memory device 100 implemented in this manner includes a NOR gate 110 and a core memory 120.

The memory device 100 stores data in response to at least one operation command signal and outputs stored data. In this process, the memory device 100 receives the read operation command signal or the write operation command signal based on the input clock information, and processes the received operation command signal.

In FIG. 1, clock information having a predetermined period is input to the memory device 100, which is transferred to the core memory 120 as it is. For convenience, the clock information transmitted to the core memory 120 is denoted by clk_core.

The NOR gate 110 determines the value of the enable signal cen-core of the core memory 120 according to the NOR operation of the enable signal rden for the read operation and the enable signal wren for the write operation do. For example, when the memory device 100 receives either the enable signal rden for the read operation or the enable signal wren for the write operation, the NOR gate 110 may control the core memory 120 And outputs a signal (cen-core) for enabling. At the same time, the memory device 100 receives the address information (addr) for processing a read operation or a write operation, and transfers the address information (addr) to the core memory 120. The address information transmitted to the core memory 120 may be represented by a_core.

In addition, when the memory device 100 receives the data (wdata) for a write operation, the data is transferred to the core memory 120 for a write operation process, which may be represented by d_core. The core memory 120 may output a result signal q_core in response to an input signal. The q_core may include a value indicating a result of processing an operation signal or data stored and output corresponding to a processing result have. The signal or data output from the memory device 100 in response to the operation signal processing of the core memory 120 is represented by rdata.

The operation of the memory device 100 may be illustrated in the graph of FIG. 2, clk_core, cen_core, wen_core, a_core, d_core, and q_core at the bottom are signals input to or output from the memory device 100 and clock, wren, rden, addr, wdata and rdata from the top, Respectively. 2, a clock signal having a predetermined period is input to the memory device 100, and an enable signal (wren) for a write operation based on the clock information (clock) An enable signal rden, address information addr for a read / write operation, and data (wdata) for a write operation.

Addresses A0 and A1 for the write operation process are allocated to the memory device 100 when a command for a write operation is input in a period 210 of a clock signal applied to the memory device 100, D0 and D1 corresponding to the write operation data wdata are stored, respectively. Similarly, when a command for a read operation is inputted in a section 220 of the clock information applied to the memory device 100, data D0 and D1 are output from the addresses A0 and A1 corresponding to the read operation . Corresponding to the operation of the memory device 100, the core memory 120 processes signals of cen_core, wen_core, a_core, d_core, and q_core. In this process, the inter-gate delay t (212, 222) May occur.

Referring to FIG. 2, the core memory 120 receives a clock signal clk_core identical to the clock signal applied to the memory device 100. Therefore, a clock signal is continuously generated irrespective of the write or read operation of the actual memory, and the clock is continuously maintained even in a section in which the memory is not used, thereby unnecessarily consuming power. In order to prevent unnecessary power consumption, it is necessary to design the memory so that the clock is allocated only in the actual operation period based on the logic circuit that can be programmed.

FIG. 3 is a block diagram illustrating a memory device 300 in which a clock signal is assigned only in an actual operating period according to one embodiment.

The memory device 300 is implemented to enable low-power operation using a programmable logic circuit. The memory device 300 generates a clock signal only during a period in which actual operation is performed, thereby greatly reducing power consumption of the memory. The memory device 300 may include a clock processor 310, a delay processor 320, and a core memory 330.

First, the clock processor 310 may generate clock information based on at least one of the input reference clock signal, the write operation signal, and the read operation signal. The clock processing unit 310 includes three D flip-flops constituted by a first D flip-flop, a second D flip-flop, and a third D flip-flop. The first D flip flop outputs a first output signal corresponding to the input of the write operation signal based on the reference clock signal and the second D flip flop outputs a first output signal corresponding to the input of the read operation signal based on the reference clock signal And outputs a corresponding second output signal. The third D flip-flop generates the clock information based on at least one of the write operation signal, the read operation signal, the first output signal, and the second output signal. For example, if at least one of the write operation signal, the read operation signal, the first output signal, and the second output signal is '1', the third D flip flop receives '1' as a data signal, When the signal is '0', '0' is input as a data signal, and the clock information is generated in synchronization with a negative edge of the reference clock signal.

The delay processing unit 320 may control the clock information to be activated in an interval in which at least one of the write operation signal and the read operation signal is performed. The delay processing unit 320 inputs the clock information to the core memory unit 330 during a period in which the output signal of the third D flip-flop is '1' (330). In addition, the delay processing unit 320 may include a delay unit for delaying at least one of the write operation signal and the read operation signal in consideration of a delay between gates in the circuit, And transfers the clock information to the core memory unit 330. The clock signal generator 320 generates a clock signal by using the clock signal. Here, the delay processing unit 320 may be regarded as an AND gate, and outputs a third output signal obtained as a result of ANDing the reference clock signal and the clock information generated from the clock processing unit 310 to the core memory unit 330 .

The core memory unit 330 performs at least one of a write operation and a read operation based on the activated clock information, and outputs result data corresponding to the execution. Here, the core memory unit 330 is implemented by at least one logic circuit that is programmable in association with the write operation and the read operation, and the logic circuit includes an FPGA (Field Programmable Gate Array), an ASIC ), A Complex Programmable Logic Device (CPLD), and a Field Programmable Analog Array (FPAA).

The memory device 300 can control the clock information to be applied to the core memory unit only in an actual operation period based on a programmable logic circuit, thereby greatly reducing power consumption of the memory device and improving power efficiency.

4 is a circuit diagram showing a circuit configuration of a memory device 400 to which a clock signal is assigned only in an actual operation period according to an embodiment. FIG. 4 is a circuit diagram showing a memory device 300 of FIG. .

4, memory device 400 includes clock processing block A 410, AND gate 420, NOR gate 430, and core memory 440. The signals (clock, rden, wren, addr, wdata) input to the memory device 400 are the same as the input signals of the memory device 100 in FIG.

The clock processing block 410 and the AND gate 420 process and control the clock information provided to the core memory 440. The clock processing block 410 will be described in detail with reference to FIG.

5 is a circuit diagram showing a detailed configuration of the clock processing unit 410 of the memory device 400 implemented according to an embodiment. The clock processor 410 generates the clock information en_clk_neg based on the reference clock signal, the read operation signal rden, and the write operation signal wren input to the memory device 400. The clock processing unit 410 may be implemented by three D flip-flops 510, 520, and 560 and three OR gates 530, 540, and 550. The first D flip flop 510 receives the write operation signal wren based on a periodically applied reference clock signal and outputs a signal of wren_1d in response to the input. (520) receives the read operation signal (rden) based on a periodically applied reference clock signal (clock), and outputs a signal of rden_1d in response to the input. The first OR gate 530 receives the wren_1d output signal of the first D flip flop 510 and the output signal rden_1d of the second D flip flop 520 and outputs a result of the OR operation, The OR gate 540 receives the read operation signal rden and the write operation signal wren and outputs an OR operation result. The third OR gate 550 receives the output signal of the first OR gate 530 and the output signal of the second OR gate 540 and outputs a result (en_clk) obtained by performing an OR operation. The third D flip-flop 560 receives the output signal en_clk of the third OR gate 550 based on the periodically input reference clock signal and receives the clock signal (en_clk_neg). The third D flip-flop 560 outputs the clock information (en_clk_neg) in synchronization with a falling edge of the reference clock signal with a negative edge D flip-flop.

4, the AND gate 420 receives the reference clock signal periodically applied to the memory device 400 and the clock information (en_clk_neg) generated by the clock processing block 410 as AND And provides the calculated result to the core memory 440 as the final clock information clk_core. Although the clock processing block 410 and the AND gate 420 are shown separately in FIG. 4, in some embodiments, an AND gate 420 may be implemented to be included in the clock processing block 410, The present invention is not limited to the embodiments of Figs.

The NOR gate 430 and the core memory 440 operate in the same manner as the configuration shown in FIG. The NOR gate 430 provides a result of the NOR operation of the read operation signal rden and the write operation signal wren as the operation signal cen-core of the core memory 440. The core memory 440 receives the address information addr for processing the operation signal received by the memory device 400 and the data wdata for the write operation as an input signal Data are represented by a_core and d_core, respectively), and a result signal (q_core) is output in response to the input signal. The q_core may include a value indicating a result of the operation signal processing or data to be stored and output in accordance with the processing result. The q_core may include a signal output from the memory device 400 in response to the processing result of the core memory 440 Or data is represented by rdata.

FIG. 6 is a graph illustrating an operation of a memory device to which a clock signal is allocated only in an actual operation period according to an exemplary embodiment, and it can be understood as an operation process of the memory device 400. Referring to FIG.

6, clock, wren, rden, addr, wdata and rdata from the top are signals input to or outputted from the memory device 400, and wren_1d, rden_1d, en_clk and en_clk_neg of the interruption are processed in the clock processing block 410 And the lower clk_core, cen_core, wen_core, a_core, d_core, and q_core represent the input / output signals of the core memory 440, respectively. 2, a reference clock signal having a predetermined period is input to the memory device 400, and based on the reference clock signal, a write operation signal wren, a read operation signal rden, Address information (addr) for write operation and data (wdata) for write operation are input. When a command for a write operation is inputted in a period 610 of a reference clock signal (clock) applied to the memory device 400, addresses A0 and A1 for the write operation process are allocated, D0 and D1 corresponding to the input write operation data (wdata) are respectively stored. When a command for a read operation is inputted in a period 620 of a reference clock signal (clock) applied to the memory device 400, data D0 and D1 are output from addresses A0 and A1 corresponding to the read operation do.

Unlike FIG. 2, in FIG. 6, signals transmitted to the core memory 440 are controlled by the signal processing of the clock processing block 410. The core memory 440 receives the final clock information clk_core only in a period in which the output of the clock processing block 410 en_clk_neg is '1', so that only the clock signal of the core memory 440 It is possible to prevent unnecessary power consumption in a section in which the memory is not used. In addition, the clock processing block 410 generates a clock signal in synchronization with the falling edge of the reference clock signal (clock) in preparation for a case where the inter-gate delay t (612, 622) Information (en_clk_neg) and adds the extra 1-clock period (M) to transfer the final clock information (clk_core) to the core memory 440.

7 is a flow chart illustrating a method of operation of a memory device according to one embodiment.

The memory device according to one embodiment is implemented to be capable of low power operation using a programmable logic circuit, and provides a method of greatly reducing power consumption of a memory by causing a clock signal to be generated only during an actual operation.

In operation 710, the clock processor of the memory device may generate clock information based on at least one of the reference clock signal, the write operation signal, and the read operation signal. Here, the clock processing unit includes three D flip-flops. In step 710, the first D flip-flop generates a first output signal corresponding to the input of the write operation signal based on the reference clock signal And the second D flip flop outputs a second output signal corresponding to the input of the read operation signal based on the reference clock signal. The third D flip flop generates the clock information based on at least one of the write operation signal, the read operation signal, the first output signal, and the second output signal. For example, if at least one of the write operation signal, the read operation signal, the first output signal, and the second output signal is '1', the third D flip flop receives '1' as a data signal, When the signal is '0', '0' is input as a data signal, and the clock information is generated in synchronization with a negative edge of the reference clock signal.

In step 720, the delay information of the memory device may be controlled such that the clock information is activated during a period in which the delay processing unit performs at least one of the write operation signal and the read operation signal. The delay processing unit inputs the clock information to the core memory unit in a period in which the output signal of the third D flip-flop is '1', so that the clock information is transferred to the core memory unit only during an actual operation period.

In step 720, the delay processing unit considers a delay between gates in the circuit, which may occur in the operation signal processing process, to generate a delayed signal in response to at least one of the write operation signal and the read operation signal, And transfers the clock information to the core memory unit with a delay of a clock unit. Here, the delay processing unit may be understood as an AND gate, and outputs a third output signal, which is a result of ANDing the reference clock signal and the clock information generated from the clock processing unit, to the core memory unit.

In operation 730, the core memory unit of the memory device may perform at least one of a write operation and a read operation based on the activated clock information, and output result data corresponding to the execution.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (13)

A clock processor for generating clock information based on at least one of a reference clock signal, a write operation signal, and a read operation signal;
A delay processing unit for controlling the clock information to be activated in a section for performing at least one of the write operation signal and the read operation signal; And
A core memory unit for performing at least one of a write operation and a read operation based on the activated clock information and outputting result data corresponding to the execution,
/ RTI >
Wherein the core memory unit is implemented with at least one logic circuit that is programmable associated with the write operation and the read operation,
The clock processing unit,
A first D flip-flop for outputting a first output signal corresponding to an input of the write operation signal based on the reference clock signal; And
A second D flip-flop for outputting a second output signal corresponding to the input of the read operation signal based on the reference clock signal,
≪ / RTI >
delete The method according to claim 1,
The clock processing unit,
1 is input as a data signal when at least one of the write operation signal, the read operation signal, the first output signal, and the second output signal is 1, and when all the signals are 0, 0 is input as a data signal, A third D flip-flop for generating the clock information in synchronization with a negative edge of the clock signal;
≪ / RTI >
The method of claim 3,
The delay processing unit,
And the clock information is input to the core memory unit in a period in which the output signal of the third D flip-flop is 1.
The method according to claim 1,
The delay processing unit,
And transfers the clock information to the core memory unit by a delay of one clock unit for a period in which at least one of the write operation signal and the read operation signal occurs.
6. The method of claim 5,
The delay processing unit,
And outputs a third output signal as a result of ANDing the reference clock signal and the clock information generated from the clock processor to the core memory unit.
The method according to claim 1,
The logic circuit comprises:
A field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a complex programmable logic device (CPLD), and a field programmable analog array (FPAA).
Generating a clock signal based on at least one of a clock signal, a write operation signal, and a read operation signal;
Controlling to activate the clock information in a period in which the delay processing unit performs at least one of the write operation signal and the read operation signal; And
The core memory unit performing at least one of a write operation and a read operation based on the activated clock information, and outputting result data corresponding to the execution
/ RTI >
Wherein the core memory unit is implemented with at least one logic circuit that is programmable associated with the write operation and the read operation,
Wherein the generating the clock information comprises:
Outputting a first output signal corresponding to an input of the write operation signal based on the reference clock signal;
Outputting a second output signal corresponding to an input of the read operation signal based on the reference clock signal; And
Generating the clock information based on at least one of the write operation signal, the read operation signal, the first output signal, and the second output signal
≪ / RTI >
delete 9. The method of claim 8,
Wherein the generating the clock information comprises:
1 is input as a data signal when at least one of the write operation signal, the read operation signal, the first output signal, and the second output signal is 1, and when all the signals are 0, 0 is input as a data signal, And generating the clock information in synchronization with a negative edge of the clock signal.
11. The method of claim 10,
Wherein the step of controlling to activate the clock information comprises:
Wherein the clock signal is input to the core memory unit when at least one of the write operation signal, the read operation signal, the first output signal, and the second output signal is 1.
9. The method of claim 8,
Wherein the step of controlling to activate the clock information comprises:
And transfers the clock information to the core memory unit with a delay of one clock unit for a period in which at least one of the write operation signal and the read operation signal occurs.
13. The method of claim 12,
Wherein the step of controlling to activate the clock information comprises:
And outputting a third output signal as a result of ANDing the reference clock signal and the clock information generated from the clock processor to the core memory unit.

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