KR101964456B1 - Organic light emitting diode display device - Google Patents

Abstract

The present invention relates to an organic light emitting diode display device capable of compensating a threshold voltage of a driving TFT. An organic light emitting diode display device according to an embodiment of the present invention includes a display panel in which a plurality of pixels formed of a matrix are formed, in which data lines, first to third scan lines, light emitting lines, and control lines are formed Wherein the pixel includes: a driver TFT having a gate electrode connected to a first node and a source electrode connected to a second node; An organic light emitting diode including an anode electrode connected to a drain electrode of the driving TFT, and a cathode electrode connected to a low potential voltage source for supplying a low potential voltage; A first capacitor having one electrode connected to the third node and the other electrode connected to the high potential voltage source; A second capacitor having one electrode connected to the first node and the other electrode connected between the third node; And first to fifth TFTs controlled by signals supplied from the first to third scan lines, the light emission lines, and the control lines, respectively.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode display device capable of compensating a threshold voltage of a driving TFT.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. In recent years, various flat panel display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting diode (OLED) have been used . Among these flat panel display devices, organic light emitting diode display devices are capable of low voltage driving, are thin, have excellent viewing angles, and have a high response speed. An active matrix type organic light emitting diode display device in which a plurality of pixels are arranged in a matrix form to display an image is widely used in organic light emitting diode display devices.

A display panel of an active matrix type organic light emitting diode display device includes a plurality of pixels arranged in a matrix form. Each of the pixels includes a scan TFT (Thin Film Transistor) for supplying a data voltage of the data line in response to a scan signal of the scan line, and a current And a driving TFT for adjusting the amount of the driving TFT. At this time, the drain-source current Ids of the driving TFT supplied to the organic light emitting diode can be expressed by Equation (1).

In Equation 1, k 'is a proportional coefficient determined by the structure and physical characteristics of the driving TFT, Vgs is the gate-source voltage of the driving TFT, and Vth is the threshold voltage of the driving TFT.

On the other hand, the threshold voltage (Vth) of each of the driving TFTs of the pixels has a different value due to the threshold voltage shift due to deterioration of the driving TFT. Since the drain-source current Ids of the driving TFT depends on the threshold voltage Vth of the driving TFT, even if the same data voltage is supplied to each of the pixels, the current Ids supplied to the organic light emitting diode differs from pixel to pixel. Therefore, even if the same data voltage is supplied to each of the pixels, the luminance of the light emitted by each of the organic light emitting diodes of the pixels varies. To solve this problem, various types of pixel structures for compensating a threshold voltage of a driving TFT have been proposed.

However, in recent years, an organic light emitting diode display device has been manufactured to realize a stereoscopic image realization or a high-speed driving with a frame frequency of 240 Hz or more in order to improve image quality. In this case, since the threshold voltage sensing period is shortened, the accuracy of the threshold voltage sensing of the driving TFT is lowered. In addition, recently, organic light emitting diode display devices have been manufactured in a large-area high resolution according to a demand of a consumer. In this case, since the length of the wiring becomes long, the wiring resistance becomes high and an RC delay may occur. As a result, the threshold voltage sensing signal is delayed and the threshold voltage sensing period is shortened. The problem of lowering occurs.

The present invention provides an organic light emitting diode display device capable of increasing the accuracy of threshold voltage sensing of a driving TFT.

An organic light emitting diode display device according to an embodiment of the present invention includes a display panel in which a plurality of pixels formed of a matrix are formed, in which data lines, first to third scan lines, light emitting lines, and control lines are formed Wherein the pixel includes: a driver TFT having a gate electrode connected to a first node and a source electrode connected to a second node; An organic light emitting diode including an anode electrode connected to a drain electrode of the driving TFT, and a cathode electrode connected to a low potential voltage source for supplying a low potential voltage; A first TFT connecting a third node and a data line supplying a data voltage in response to a first scan signal supplied from the first scan line; A second TFT for connecting the data line to the first node in response to a second scan signal supplied from the second scan line; A third TFT for connecting the first node with a reference voltage source for supplying a reference voltage in response to a third scan signal supplied from the third scan line; A fourth TFT for connecting the second node to a high potential voltage source for supplying a high-potential voltage in response to the light-emitting signal supplied from the light-emitting line; A fifth TFT for connecting the second node and the third node in response to a control signal supplied from the control line; A first capacitor having one electrode connected to the third node and the other electrode connected to the high potential voltage source; And a second capacitor having one side electrode connected to the first node and the other side electrode connected between the third node.

The present invention senses the threshold voltage of the driving TFT for a period longer than two horizontal periods. As a result, the present invention can accurately sense the threshold voltage of the driving TFT even when the large-area, high-resolution organic light emitting display device is driven at a high frame frequency of 240 Hz or higher.

Further, the present invention connects the fourth TFT between the high potential source and the driving TFT, and controls on / off of the fourth TFT by using the light emitting signal. As a result, the present invention can compensate the voltage drop of the high-potential voltage by compensating the threshold voltage using the voltage reflecting the voltage drop of the high-potential voltage.

Further, the present invention can sense the drain-source current of the driving TFT by using the data line. As a result, since the present invention can externally compensate using the external compensation method, it is possible to compensate not only the threshold voltage of the driving TFT but also the mobility of the driving TFT.

1 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention;
FIG. 2 is a waveform diagram showing signals input to a pixel in the case of internal compensation. FIG.
3 is a table showing voltage changes of nodes.
4 is a waveform diagram showing signals input to a pixel in the case of external compensation;
5 is a current flow diagram of a pixel in the case of external compensation;
6 is a block diagram schematically illustrating an organic light emitting diode display device according to an embodiment of the present invention.
7 is a block diagram showing an external compensation section of the timing controller;
8 is a flow chart illustrating an external compensation method in accordance with an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

The pixel of the organic light emitting diode display according to the embodiment of the present invention not only internally compensates the threshold voltage of the driving TFT but also compensates the threshold voltage and mobility of the driving TFT (Thin Film Transistor) have. The internal compensation means that the threshold voltage of the driving TFT is sensed and compensated in real time in the pixel. The external compensation senses the drain-source current of the driving TFT and compensates the digital video data to be input to the pixel by using the sensed current, and then supplies the compensated digital video data to the pixel.

1 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. Referring to FIG. 1, a pixel P according to an embodiment of the present invention includes a driving TFT DT, an organic light emitting diode (OLED), a control circuit, capacitors, and the like.

The driving TFT DT adjusts the amount of the drain-source current Ids differently depending on the amount of voltage applied to the gate electrode. The gate electrode of the driving TFT DT is connected to the first node N1, the source electrode is connected to the second node N2, and the drain electrode is connected to the anode electrode of the organic light emitting diode OLED.

The anode electrode of the organic light emitting diode OLED is connected to the drain electrode of the driving TFT DT and the cathode electrode is connected to the low potential voltage source VSS_S for supplying the low potential voltage VSS. The organic light emitting diode OLED emits light in accordance with the drain-source current Ids of the driving TFT DT.

The control circuit includes the first to fifth TFTs T1, T2, T3, T4, and T5. The first TFT T1 connects the third node N3 and the data line DL to which the data voltage DATA is supplied in response to the first scan signal SCAN1 supplied from the first scan line SL1 . The gate electrode of the first TFT T1 is connected to the first scan line SL1, the source electrode thereof is connected to the data line DL, and the drain electrode thereof is connected to the third node N3.

The second TFT T2 connects the first node N1 and the data line DL in response to the second scan signal SCAN2 supplied from the second scan line SL2. The gate electrode of the second TFT T2 is connected to the second scan line SL2, the source electrode thereof is connected to the data line DL, and the drain electrode thereof is connected to the first node N1.

The third TFT T3 connects the first node N1 with the reference voltage source REF_S that supplies the reference voltage REF in response to the third scan signal SCAN3 supplied from the third scan line SL3 . The gate electrode of the third TFT T3 is connected to the third scan line SL3, the source electrode thereof is connected to the first node N1, and the drain electrode thereof is connected to the reference voltage source REF_S.

The fourth TFT T4 connects the high potential voltage source VDD_S which supplies the high potential voltage VDD to the second node N2 in response to the light emission signal EM supplied from the light emission line EML. The gate electrode of the fourth TFT T4 is connected to the light emitting line EML, the source electrode thereof is connected to the high potential voltage source VDD_S, and the drain electrode thereof is connected to the second node N2.

The fifth TFT T5 connects the second node N2 and the third node N3 in response to the control signal MG supplied from the control line MGL. The gate electrode of the fifth TFT T5 is connected to the control line MGL, the source electrode thereof is connected to the second node N2, and the drain electrode thereof is connected to the third node N3.

One electrode of the first capacitor C1 is connected to the third node N3, and the other electrode thereof is connected between the high potential voltage source VDD_S. One electrode of the second capacitor C2 is connected to the first node N1 and the other electrode is connected to the third node N3.

The first node N1 is a contact point between the gate electrode of the driving TFT DT, the drain electrode of the second TFT T2, the source electrode of the third TFT T3, and one electrode of the second capacitor C2. The second node N2 is a contact point between the source electrode of the driving TFT DT, the drain electrode of the fourth TFT T4, and the source electrode of the fifth TFT T5. The third node N3 is a contact point between the drain electrode of the first TFT T1, the drain electrode of the fifth TFT T5, one electrode of the first capacitor C1, and the other electrode of the second capacitor C2 .

The semiconductor layers of the first to fifth TFTs T1, T2, T3, T4, and T5 and the driver TFT DT may be formed of any one of a-Si, Poly-Si, and oxides. In the embodiment of the present invention, the first to fifth TFTs T1, T2, T3, T4, and T5 and the driving TFT DT are formed of a P-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) However, the present invention is not limited to this, and it may be implemented as an N-type MOSFET.

The high potential voltage source VDD_S is set to supply the direct current high potential voltage VDD in consideration of the characteristics of the driving TFT DT and the characteristics of the organic light emitting diode OLED and the low potential power source VSS_S is set to the direct current low potential May be set to supply the voltage VSS. The reference voltage source REF_S is set to supply the reference voltage REF to initialize the first node N1. The differential voltage VDD-REF between the high-potential voltage VDD and the reference voltage REF is higher than the threshold voltage Vth of the driving TFT DT in order to sense the threshold voltage Vth of the driving TFT DT Voltage can be set.

The display panel 10 of the organic light emitting diode display device of the present invention may be used to externally compensate the threshold voltage Vth and mobility of the driving TFT DT and the threshold voltage Vth of the organic light emitting diode OLED And a data voltage switching circuit (DATA_SW). The data voltage switching circuit DATA_SW includes first and second switches S1 and S2, an inverter Inv, and a current sensing circuit ADC. Although the first and second switches S1 and S2 are formed of a P-type MOSFET, the present invention is not limited to this, and may also be realized as an N-type MOSFET. The data voltage switching circuit DATA_SW connects the data line DL to the source drive IC S-IC when internal compensation is performed and connects the data line DL to the current sensing circuit ADC .

The first switch S1 connects the data line DL to the source driver IC (S-IC) which supplies the data voltage DATA in response to the switching control signal SC supplied from the switching control line SCL . The gate electrode of the first switch S1 is connected to the switching control line SCL, the source electrode thereof is connected to the source drive IC, and the drain electrode thereof is connected to the data line DL.

The second switch S2 connects the data line DL to the current sensing circuit ADC in response to the switching control signal SC inverted by the inverter supplied from the switching control line SCL. The gate electrode of the second switch S2 is connected to the inverter Inv, the source electrode thereof is connected to the current sensing circuit ADC and the drain electrode thereof is connected to the data line DL.

The inverter Inv inverts the switching control signal SC supplied from the switching control line SCL. The inverter Inv is connected between the switching control line SCL and the gate electrode of the second switch S2.

The current sensing circuit ADC is connected to the data line DL and senses the current flowing through the data line DL. The current sensing circuit ADC converts the sensed current into digital data and outputs the converted digital data to the timing controller 40. [ A detailed description of the external compensation method of the timing controller 40 will be given later with reference to FIGS. 7 and 8. FIG.

2 is a waveform diagram showing signals input to a pixel in the case of internal compensation. In FIG. 2, the first to third scan signals SCAN1 and SCAN2, which are input to one pixel P of the display panel 10 during the first to fourth periods t1, t2, t3 and t4, SCAN3, a control signal MG, a light emission signal EM, and a switching control signal SC are shown. The first period t1 is a period for initializing the first node N1, the second period t2 is a period for sensing the threshold voltage of the driving TFT DT, and the third period t3 is a period for initializing the pixels P And the fourth period t4 is a period during which the organic light emitting diode OLED emits light.

2, the first to third scan signals SCAN1, SCAN2 and SCAN3, the emission signal EM and the control signal MG are applied to the first to fifth TFTs T1 and T2 of the pixel P, , T3, T4, T5). The switching control signal SC is a signal for controlling the first and second switches S1 and S2 of the data voltage switching circuit DATA_SW of the display panel 10. [ The first to third scan signals SCAN1, SCAN2 and SCAN3, the emission signal EM and the control signal MG are generated in a period of one frame period. The data voltage DATA is generated in a period of one horizontal period (1H). One horizontal period (1H) denotes a one-line scanning time at which data is written to the pixels (P) of one horizontal line in the display panel (10).

The first scan signal SCAN1 is generated at the gate high voltage VGH during the first to fourth periods t1, t2, t3 and t4. The second scan signal SCAN2 is generated at the gate high voltage VGH during the first, second and fourth periods t1, t2 and t4 and during the third period t3 at the gate low voltage VGL Occurs. The third scan signal SCAN3 is generated at the gate high voltage VGH during the third and fourth periods t3 and t4 and is generated at the gate low voltage VGL during the first and second periods t1 and t2 do. The control signal MG is generated with the gate high voltage VGH during the third period t3 and with the gate low voltage VGL during the first, second and fourth periods t1, t2 and t4 . The emission signal EM is generated at the gate high voltage VGH during the second and third periods t2 and t3 and at the gate low voltage VGL during the first and fourth periods t1 and t4. The switching control signal SC is generated as a gate low voltage VGL during the first to fourth periods t1, t2, t3 and t4. The gate high voltage VGH may be set between about 14V and 20V, and the gate low voltage VGL may be set between about -12V and -5V.

3 is a table showing voltage changes of the nodes of the pixel. Hereinafter, the operation of the pixel P during the first to fourth periods t1, t2, t3 and t4 will be described in detail with reference to Figs.

The first period t1 is a period for initializing the first node N1, the second period t2 is a period for sensing the threshold voltage of the driving TFT DT, and the third period t3 is a period for initializing the pixels P And the fourth period t4 is a period during which the organic light emitting diode OLED emits light. The second period t2 continues in the first period t1 and the third period t3 continues in the second period t2 and the fourth period t4 continues in the third period t3 .

The switching control signal SC of the gate low voltage VGL is supplied through the switching control line SCL during the first to fourth periods t1 to t4. The first switch S1 is turned on by the switch control signal SC of the gate low voltage VGL. Due to the turn-on of the first switch S1, the source drive IC (S-IC) and the data line DL are connected to each other. The second switch S2 is turned off by the inversion signal of the switch control signal SC.

First, the first scan signal SCAN1 of the gate high voltage VGH is supplied through the first scan line SL1 during the first period t1 and the second scan signal SCAN1 of the gate high voltage VGH is supplied through the first scan line SL1. SCAN2 are supplied through the second scan line SL2 and the third scan signal SCAN3 of the gate low voltage VGL is supplied through the third scan line SL3. During the first period t1 the emission signal EM of the gate low voltage VGL is supplied through the emission line EML and the control signal MG of the gate low voltage VGL is supplied to the control line MGL, Lt; / RTI >

The first TFT T1 is turned off by the first scan signal SCAN1 of the gate high voltage VGH. And the second TFT T2 is turned off by the second scan signal SCAN2 of the gate high voltage VGH. The third TFT T3 is turned on by the third scan signal SCAN3 of the gate low voltage VGL. Due to the turn-on of the third TFT T3, the first node N1 and the reference voltage source REF_S are connected to each other. The fourth TFT T4 is turned on by the emission signal EM of the gate-low voltage VGL. Due to the turn-on of the fourth TFT (T4), the second node (N2) and the high potential voltage source (VDD_S) are connected to each other. The fifth TFT T5 is turned on by the control signal MG of the gate low voltage VGL. Due to the turn-on of the fifth TFT (T5), the second node (N2) and the third node (N3) are connected to each other.

Since the first node N1 is connected to the reference voltage source REF_S due to the turn-off of the second TFT T2 and the turn-on of the third TFT T3, the first node N1 is supplied with the reference voltage REF) is supplied. Due to the turn-on of the fourth TFT T4, the second node N2 is connected to the high potential voltage source VDD_S, so that the high potential voltage VDD is supplied to the second node N2. The third node N3 is connected to the second node N2 due to the turn-off of the first TFT T1 and the turn-on of the fifth TFT T5, The voltage VDD is supplied.

Second, during the second period t2, the first scan signal SCAN1 of the gate high voltage VGH is supplied through the first scan line SL1 and the second scan signal SCAN1 of the gate high voltage VGH SCAN2 are supplied through the second scan line SL2 and the third scan signal SCAN3 of the gate low voltage VGL is supplied through the third scan line SL3. The light emission signal EM of the gate high voltage VGH is supplied through the light emission line EML and the control signal MG of the gate low voltage VGL is supplied to the control line MGL during the second period t2. Lt; / RTI >

The first TFT T1 is turned off by the first scan signal SCAN1 of the gate high voltage VGH. And the second TFT T2 is turned off by the second scan signal SCAN2 of the gate high voltage VGH. The third TFT T3 is turned on by the third scan signal SCAN3 of the gate low voltage VGL. Due to the turn-on of the third TFT T3, the first node N1 and the reference voltage source REF_S are connected to each other. The fourth TFT T4 is turned off by the emission signal EM of the gate high voltage VGH. The fifth TFT T5 is turned on by the control signal MG of the gate low voltage VGL. Due to the turn-on of the fifth TFT (T5), the second node (N2) and the third node (N3) are connected to each other.

Since the first node N1 is connected to the reference voltage source REF_S due to the turn-off of the second TFT T2 and the turn-on of the third TFT T3, the first node N1 is supplied with the reference voltage REF) is supplied. Due to the turn-off of the fourth TFT T4, the second node N2 is floating. The third node N3 is connected to the second node N2 because of the turn-off of the first TFT T1 and the turn-on of the fifth TFT T5, And is plotted with a potential substantially equal to the node N2.

The threshold voltage Vth of the driving TFT DT is set to the second node N2 and the third node N3 due to the floating of the second node N2 and the third node N3 during the second period t2, . The voltage difference Vgs between the first node N1 connected to the gate electrode of the driving TFT DT and the second node N2 connected to the source electrode is greater than the threshold voltage Vth, Forms a current path until the voltage difference (Vgs) between the gate electrode and the source electrode reaches the threshold voltage (Vth). Therefore, the voltage of the second node N2 is lowered to the difference voltage REF-Vth between the reference voltage REF and the threshold voltage Vth of the driving TFT DT. The third node N3 is also floated to a potential substantially equal to the second node N2 due to the turn-on of the fifth TFT T5, so that the voltage of the third node N3 also becomes equal to the reference voltage REF1, (REF-Vth) of the threshold voltage (Vth) of the driving TFT (DT).

During the second period t2, the second node N2 and the third node N3 sense the threshold voltage Vth of the driving TFT DT. In particular, the second period t2 may be appropriately set to a period longer than two horizontal periods through a preliminary experiment. As a result, according to the present invention, the threshold voltage (Vth) of the driving TFT (DT) can be sensed for a period longer than two horizontal periods. Therefore, even when the organic light emitting display device with a large area and high resolution is driven at a high- The accuracy of the threshold voltage sensing of the signal DT can be improved.

Third, during the third period t3, the first scan signal SCAN1 of the gate high voltage VGH is supplied through the first scan line SL1 and the second scan signal SCAN1 of the gate low voltage VGL SCAN2 are supplied through the second scan line SL2 and the third scan signal SCAN3 of the gate high voltage VGH is supplied through the third scan line SL3. During the third period t3, the emission signal EM of the gate high voltage VGH is supplied through the emission line EML and the control signal MG of the gate high voltage VGH is supplied to the control line MGL. Lt; / RTI >

The first TFT T1 is turned off by the first scan signal SCAN1 of the gate high voltage VGH. And the second TFT T2 is turned on by the second scan signal SCAN2 of the gate low voltage VGL. Due to the turn-on of the second TFT T2, the first node N1 and the data line DL are connected to each other. The third TFT T3 is turned off by the third scan signal SCAN3 of the gate high voltage VGH. The fourth TFT T4 is turned off by the emission signal EM of the gate high voltage VGH. The fifth TFT T5 is turned off by the control signal MG of the gate high voltage VGH.

The first node N1 is connected to the data line DL due to the turn-on of the second TFT T2 and the turn-off of the third TFT T3, DATA) is supplied. Due to the turn-off of the fourth TFT (T4), the second node (N2) floats. Due to the turn-off of the first TFT (T1) and the fifth TFT (T5), the connection between the second node (N2) and the third node (N3) is cut off, so that the third node (N3) floats.

Since the third node N3 is floated during the third period t3, the voltage variation of the first node N1 is reflected to the third node N3 by the second capacitor C2. That is, 'REF-DATA', which is the voltage change amount of the first node N1, is reflected to the third node N3. However, since the third node N3 is connected between the first and second capacitors C1 and C2 connected in series, the voltage change amount is reflected at the ratio of C 'as in Equation (2).

In Equation (2), CA1 denotes the capacitance of the first capacitor (C1) and CA2 denotes the capacitance of the second capacitor (C2). As a result, 'C' (REF-DATA) 'is reflected in the third node N3, so that the voltage of the third node N3 changes to' REF-Vth-C '(REF-DATA).

Fourth, during the fourth period t4, the first scan signal SCAN1 of the gate high voltage VGH is supplied through the first scan line SL1 and the second scan signal SCAN1 of the gate high voltage VGH SCAN2 are supplied through the second scan line SL2 and the third scan signal SCAN3 of the gate high voltage VGH is supplied through the third scan line SL3. During the fourth period t4, the emission signal EM of the gate low voltage VGL is supplied through the emission line EML and the control signal MG of the gate low voltage VGL is supplied to the control line MGL. Lt; / RTI >

The first TFT T1 is turned off by the first scan signal SCAN1 of the gate high voltage VGH. And the second TFT T2 is turned off by the second scan signal SCAN2 of the gate high voltage VGH. The third TFT T3 is turned off by the third scan signal SCAN3 of the gate high voltage VGH. The fourth TFT T4 is turned on by the emission signal EM of the gate-low voltage VGL. Due to the turn-on of the fourth TFT (T4), the second node (N2) and the high potential voltage source (VDD_S) are connected to each other. The fifth TFT T5 is turned on by the control signal MG of the gate low voltage VGL. Due to the turn-on of the fifth TFT (T5), the second node (N2) and the third node (N3) are connected to each other.

Due to the turn-off of the second TFT T2 and the third TFT T3, the first node N1 floats. Due to the turn-on of the fourth TFT T4, the second node N2 is connected to the high potential voltage source VDD_S, and thus the high potential voltage VDD is supplied to the second node N2. Since the second node N2 and the third node N3 are connected due to the turn-off of the first TFT T1 and the turn-on of the fifth TFT T5, the third node N3 is supplied with a high potential The voltage VDD is supplied.

Since the first node N1 is floated during the fourth period t4, the voltage variation of the third node N3 is reflected to the first node N1 by the second capacitor C2. That is, 'REF-Vth-C' (REF-DATA) -VDD ', which is the voltage change amount of the third node N3, is reflected in the first node N1. Accordingly, the voltage of the first node N1 changes to 'DATA- {REF-Vth-C' (REF-DATA) -VDD} '.

Meanwhile, the drain-source current Ids of the driving TFT DT supplied to the organic light emitting diode (OLED) is expressed by Equation (3).

In Equation 3, k 'is a proportional coefficient determined by the structure and physical characteristics of the driver TFT DT, and is determined by the mobility, the channel width, and the channel length of the driver TFT DT. Vgs denotes a difference between the gate voltage Vg and the source voltage Vs of the driving TFT DT and Vth denotes a threshold voltage of the driving TFT DT. During the fourth period (t4), 'Vgs-Vth' is expressed by Equation (4).

Summarizing the expression (4), the drain-source current Ids of the driving TFT DT is derived as shown in expression (5).

As a result, the drain-source current Ids of the driving TFT DT supplied to the organic light emitting diode OLED during the fourth period t4 is equal to the threshold voltage Vth of the driving TFT DT It does not depend on it. That is, the present invention can compensate the threshold voltage (Vth) of the driving TFT (DT).

On the other hand, the high potential voltage source VDD_S supplies the high potential voltage VDD to the plurality of pixels P. When the fourth TFT T4 is turned on by the light emission pulse EM of the gate low voltage VGL during the fourth period t4, the current between the high potential VDD and the low potential VSS The high potential voltage VDD supplied from the high potential voltage source VDD_S is lowered due to the parasitic resistance of the driving TFT DT and the organic light emitting diode OLED existing along the path. Referring to Equation (4), in the prior art, 'VDD' of the gate voltage Vg is a high potential voltage before the voltage is lowered, and 'VDD' of the source voltage Vs is a voltage lowered high potential voltage. In this case, 'VDD' is not deleted in Equation (4) because 'VDD' of the gate voltage Vg and 'VDD' of the source voltage Vs are different. Therefore, the drain-source current Ids of the driving TFT DT, Has a problem that it becomes dependent on the high-potential voltage (VDD). However, in the pixel P according to the embodiment of the present invention, 'VDD' sampled at the gate voltage Vg at 'Vgs-Vth' in Equation 4 and 'VDD', which is the source voltage Vs, Since the voltage is reflected, 'VDD' is deleted in Equation (4), so that the drain-source current Ids of the driving TFT DT is not dependent on the high-potential voltage VDD. That is, the present invention can compensate the voltage drop of the high-potential voltage (VDD).

4 is a waveform diagram showing signals input to a pixel in the case of external compensation. 4 shows the first to third scan signals SCAN1, SCAN2 and SCAN3, the control signal MG, the emission signal EM, and the first and second scan signals SC1 to SCn3 inputted to one pixel P of the display panel 10 in the case of external compensation. The switching control signal SC is shown. The fifth and seventh periods t5 and t7 are idle periods and the sixth period t6 is a period for sensing the drain-source current Ids of the driving TFT DT for external compensation. The sixth period t6 may be set to an appropriate period through experiment so that the drain-source current Ids of the driving TFT DT can be accurately sensed.

4, the first to third scan signals SCAN1, SCAN2 and SCAN3, the emission signal EM and the control signal MG are applied to the first to fifth TFTs T1 and T2 of the pixel P, , T3, T4, T5). The switching control signal SC is a signal for controlling the first and second switches S1 and S2 of the data voltage switching circuit DATA_SW of the display panel 10. [

The first scan signal SCAN1, the third scan signal SCAN3 and the control signal MG are generated at the gate high voltage VGH during the fifth and seventh periods t5 and t7 and during the sixth period t6 ≪ / RTI > (VGL). The second scan signal SCAN2, the emission signal EM and the switching control signal SC are generated at the gate high voltage VGH during the fifth to tenth periods t5, t6 and t7.

5 is a current flow diagram of a pixel in the case of external compensation. Hereinafter, the operation of the pixel P during the first to fourth periods t1, t2, t3 and t4 will be described in detail with reference to Figs. 4 and 5. Fig. The fifth and seventh periods t5 and t7 are idle periods and the sixth period t6 is a period for sensing the drain-source current Ids of the driving TFT DT for external compensation. The sixth period t6 continues in the fifth period t5 and the seventh period t7 continues in the sixth period t6.

The switching control signal SC of the gate high voltage VGH is supplied through the switching control line SCL during the fifth to seventh periods t5 to t7. The first switch S1 is turned off by the switch control signal SC of the gate high voltage VGH. The second switch S2 is turned on by the inversion signal of the switch control signal SC. Due to the turn-on of the second switch S2, the current sensing circuit ADC and the data line DL are connected to each other.

First, during the fifth period t5, the first scan signal SCAN1 of the gate high voltage VGH is supplied through the first scan line SL1 and the second scan signal SCAN1 of the gate high voltage VGH SCAN2 are supplied through the second scan line SL2 and the third scan signal SCAN3 of the gate high voltage VGH is supplied through the third scan line SL3. During the fifth period t5, the control signal MG of the gate high voltage VGH is supplied through the control line MGL and the emission signal EM of the gate high voltage VGH is supplied to the emission line EML. Lt; / RTI >

The first TFT T1 is turned off by the first scan signal SCAN1 of the gate high voltage VGH. And the second TFT T2 is turned off by the second scan signal SCAN2 of the gate high voltage VGH. The third TFT T3 is turned off by the third scan signal SCAN3 of the gate high voltage VGH. The fourth TFT T4 is turned off by the emission signal EM of the gate high voltage VGH. The fifth TFT T5 is turned off by the control signal MG of the gate high voltage VGH.

Secondly, during the sixth period t6, the first scan signal SCAN1 of the gate low voltage VGL is supplied through the first scan line SL1, and the second scan signal of the gate high voltage VGH SCAN2 are supplied through the second scan line SL2 and the third scan signal SCAN3 of the gate low voltage VGL is supplied through the third scan line SL3. During the sixth period t6 the control signal MG of the gate low voltage VGL is supplied through the control line MGL and the emission signal EM of the gate high voltage VGH is supplied to the emission line EML, Lt; / RTI >

The first TFT (T1) is turned on by the first scan signal (SCAN1) of the gate low voltage (VGL). Due to the turn-on of the first TFT (T1), the third node (N3) and the data line (DL) are connected to each other. And the second TFT T2 is turned off by the second scan signal SCAN2 of the gate high voltage VGH. The third TFT T3 is turned on by the third scan signal SCAN3 of the gate low voltage VGL. Due to the turn-on of the third TFT T3, the first node N1 and the reference voltage source REF_S are connected to each other. The fourth TFT T4 is turned off by the emission signal EM of the gate high voltage VGH. The fifth TFT T5 is turned on by the control signal MG of the gate low voltage VGL. Due to the turn-on of the fifth TFT (T5), the second node (N2) and the third node (N3) are connected to each other.

Due to the turn-on of the first TFT (T1), the third node (N3) is connected to the data line (DL). Since the first node N1 is connected to the reference voltage source REF_S due to the turn-off of the second TFT T2 and the turn-on of the third TFT T3, the first node N1 is supplied with the reference voltage REF) is supplied. Due to the turn-off of the fourth TFT (T4) and the turn-on of the fifth TFT (T5), the second node (N2) is connected to the third node (N3).

Since the voltage difference Vgs between the reference voltage REF applied to the gate electrode of the driving TFT DT and the voltage of the source electrode during the sixth period t6 is larger than the threshold voltage Vth of the driving TFT DT, The driving TFT DT is turned on. Further, since the first and fifth TFTs T1 and T5 are turned on, the drain-source current Ids of the driving TFT DT is higher than the second node N2, the third node N3, And is sensed by a current sensing circuit ADC via a line DL. The current sensing circuit ADC converts the sensed current into digital data and outputs the converted digital data to the external compensation section 41 of the timing controller 40. [ A detailed description of the external compensation method of the external compensation unit 41 will be given later with reference to FIGS. 7 and 8. FIG.

Third, during the seventh period t7, the first scan signal SCAN1 of the gate high voltage VGH is supplied through the first scan line SL1 and the second scan signal SCAN1 of the gate high voltage VGH SCAN2 are supplied through the second scan line SL2 and the third scan signal SCAN3 of the gate high voltage VGH is supplied through the third scan line SL3. The control signal MG of the gate high voltage VGH is supplied through the control line MGL and the emission signal EM of the gate high voltage VGH is supplied to the emission line EML during the seventh period t7, Lt; / RTI >

The first TFT T1 is turned off by the first scan signal SCAN1 of the gate high voltage VGH. And the second TFT T2 is turned off by the second scan signal SCAN2 of the gate high voltage VGH. The third TFT T3 is turned off by the third scan signal SCAN3 of the gate high voltage VGH. The fourth TFT T4 is turned off by the emission signal EM of the gate high voltage VGH. The fifth TFT T5 is turned off by the control signal MG of the gate high voltage VGH.

6 is a block diagram schematically showing an organic light emitting diode display device according to an embodiment of the present invention. 6, the organic light emitting diode display according to the exemplary embodiment of the present invention includes a display panel 10, a data driver 20, a scan driver 30, a timing controller 40, a host system 50, Respectively.

The display panel 10 is formed such that the data lines DL and the first scan lines SL1 intersect with each other. The display panel 10 includes a second scan line SL2, a third scan line SL3, a control line MG, and a light emission line EML in parallel with the first scan lines SL1. Are formed. In addition, switching control lines SCL may be formed on the display panel 10 in parallel with the first scan lines SL1. In addition, in the display panel 10, pixels P arranged in a matrix form are formed. Each of the pixels P of the display panel 10 is as described with reference to FIG.

The data driver 20 includes a plurality of source drive ICs. The source drive ICs receive the digital video data RGB 'compensated from the timing controller 40 for the threshold voltage Vth of the driving TFT DT and the mobility, the threshold voltage Vth of the organic light emitting diode OLED, . The source drive ICs generate a data voltage by converting the compensated digital video data RGB 'into a gamma compensation voltage in response to a source timing control signal DCS from the timing controller 40, (DL) of the display panel 10 so as to be synchronized with the scan line SCAN1.

The scan driver 30 includes a first scan signal output unit, a second scan signal output unit, a third scan signal output unit, a control signal output unit, an emission signal output unit, and a switching control signal output unit. The first scan signal output unit sequentially outputs the first scan signal SCAN1 to the first scan lines SL1 of the display panel 10. [ The second scan signal output unit sequentially outputs a second scan signal (SCAN2) to the second scan lines (SL2) of the display panel (10). The third scan signal output unit sequentially outputs a third scan signal (SCAN3) to the third scan lines (SL3) of the display panel (10). The control signal output unit sequentially outputs the control signal MG to the control lines MGL of the display panel 10. The light emitting signal output unit sequentially outputs the light emitting signal EM to the light emitting lines (EML) of the display panel 10. The switching control signal output unit sequentially outputs the switching control signal SC to the switching control lines SCL of the display panel 10. The details of the first to third scan signals SCAN1, SCAN2 and SCAN3, the control signal MG, the light emission signal EM and the switching control signal SC are described in detail with reference to FIG. 2 and FIG. Respectively.

The timing controller 40 receives digital video data RGB from the host system 50 via an interface such as a low voltage differential signaling (LVDS) interface and a transition minimized differential signaling (TMDS) interface. The timing controller 40 may include an external compensation section 41 for externally compensating the threshold voltage Vth of the driving TFT DT and mobility and the like. The external compensation unit 41 of the timing controller 40 reflects the compensation data calculated by using the external compensation method on the digital video data RGB input from the host system 50 and outputs the compensated digital video data RGB ' And outputs it to the data driver 20.

The timing controller 40 receives timing signals such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal (Data Enable), and a dot clock (Dot Clock). The timing controller 50 generates timing control signals for controlling the operation timing of the data driver 20 and the scan driver 30 based on the timing signal from the host system. The timing control signals include a scan timing control signal for controlling the operation timing of the scan driver 30 and a data timing control signal for controlling the operation timing of the data driver 20. [ The timing controller 40 outputs a scan timing control signal to the scan driver 30 and a data timing control signal to the data driver 20.

The display panel may further include a power supply unit (not shown). The power supply unit supplies a high potential voltage (VDD), a low potential voltage (VSS), and a reference voltage (REF) to the display panel (10). The power supply unit supplies a gate high voltage VGH and a gate low voltage VGL to the scan driver 30.

7 is a block diagram showing an external compensation unit of the timing controller. 8 is a flowchart illustrating an external compensation method according to an embodiment of the present invention. 7, the external compensation unit 41 of the timing controller 40 includes a compensation data calculation unit 41a and a compensated digital video data output unit 41b. Hereinafter, an external compensation method of the external compensation unit 41 according to the embodiment of the present invention will be schematically described with reference to FIGS. 7 and 8. FIG.

First, a current-sensing circuit (ADC) connected to the data line DL of each of the pixels P of the display panel 10 is used to drive the drain-source of the driving TFT DT of each of the pixels P And senses the inter-state current Ids. The method of sensing the drain-source current (Ids) of the driver TFT (DT) of the current sensing circuit (ADC) has been described in detail with reference to FIGS. 4 and 5. FIG. The current sensing circuit ADC converts the sensed current into digital data and outputs the converted digital data to the compensation data calculation section 41a of the external compensation section 41. [ (S1)

Secondly, the compensation data calculation section 41a calculates the external compensation data using the digital data inputted from the current sensing circuit ADC. The compensation data calculator 41a can calculate external compensation data compensating for the threshold voltage Vth of the driving TFT DT and mobility and the like from the digital data inputted using known external compensation calculation methods. (S2)

Thirdly, the compensated digital video data output section 41b receives digital video data (RGB) from the host system 50 and receives external compensation data from the compensation data calculation section 41a. The compensated digital video data output section 41b generates compensated digital video data RGB 'by reflecting external compensation data to the input digital video data RGB. The compensated digital video data output section 41b outputs the compensated digital video data RGB 'to the data driver 20. (S3)

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

OLED: organic light emitting diode DT: driving TFT
T1: first TFT T2: second TFT
T3: third TFT T4: fourth TFT
T5: fifth TFT S1: first switch
S2: second switch Inv: inverter
ADC: current sensing circuit C1: first capacitor
C2: second capacitor N1: first node
N2: second node N3: third node
SCAN1: first scan signal SCAN2: second scan signal
SCAN3: Third scan signal MG: Control signal
EM: Emission signal SC: Switching control signal
10: display panel 20: data driver
30: scan driver 40: timing controller
41: external compensation unit 41a: external compensation data calculation unit
41b: Compensated digital video data output section
50: Host system

Claims (14)

And a display panel in which a plurality of data lines, first to third scan lines, light emitting lines, and control lines are formed and a plurality of pixels formed in a matrix form are formed,
The pixel includes:
A driver TFT having a gate electrode connected to the first node and a source electrode connected to the second node;
An organic light emitting diode including an anode electrode connected to a drain electrode of the driving TFT, and a cathode electrode connected to a low potential voltage source for supplying a low potential voltage;
A first TFT connecting a third node and a data line supplying a data voltage in response to a first scan signal supplied from the first scan line;
A second TFT for connecting the data line to the first node in response to a second scan signal supplied from the second scan line;
A third TFT for connecting the first node with a reference voltage source for supplying a reference voltage in response to a third scan signal supplied from the third scan line;
A fourth TFT for connecting the second node to a high potential voltage source for supplying a high-potential voltage in response to the light-emitting signal supplied from the light-emitting line;
A fifth TFT for connecting the second node and the third node in response to a control signal supplied from the control line;
A first capacitor having one electrode connected to the third node and the other electrode connected to the high potential voltage source; And
And a second capacitor having one electrode connected to the first node and the other electrode connected between the third node. The method according to claim 1,
During a first period of initializing the first node to the reference voltage,
The first and second scan signals are generated at a gate high voltage,
Wherein the third scan signal, the control signal, and the emission signal are generated at a gate low voltage lower than the gate high voltage. 3. The method of claim 2,
During a second period following the first period and sensing a threshold voltage of the driving TFT,
The first and second scan signals and the emission signal are generated at the gate high voltage,
And the third scan signal and the control signal are generated at the gate low voltage. The method of claim 3,
During a third period in which the data voltage is supplied to the data line,
The first and third scan signals, the control signal, and the emission signal are generated at the gate high voltage,
And the second scan signal is generated at the gate-low voltage. 5. The method of claim 4,
During the fourth period in which the organic light emitting diode emits light,
The first to third scan signals are generated at the gate high voltage,
Wherein the control signal and the emission signal are generated at the gate low voltage. The method according to claim 1,
And the difference voltage between the reference voltage and the high-potential voltage is greater than a threshold voltage of the driving TFT. The method according to claim 1,
A gate electrode of the first TFT is connected to the first scan line, a source electrode is connected to the data line, a drain electrode is connected to the third node,
A gate electrode of the second TFT is connected to the second scan line, a source electrode is connected to the data line, a drain electrode is connected to the first node,
A gate electrode of the third TFT is connected to the third scan line, a source electrode is connected to the first node, a drain electrode is connected to the reference voltage source,
A gate electrode of the fourth TFT is connected to the light emitting line, a source electrode is connected to the high potential voltage source, a drain electrode is connected to the second node,
The gate electrode of the fifth TFT is connected to the control line, the source electrode is connected to the second node, and the drain electrode is connected to the third node. 6. The method of claim 5,
The display panel further includes a switching control line,
In the display panel,
A first switch for connecting the data line with a source drive IC for supplying the data voltage in response to a switching control signal of the switching control line;
An inverter for inverting the switching control signal; And
And a second switch for connecting the current sensing circuit and the data line in response to the switching control signal inverted by the inverter. 9. The method of claim 8,
Wherein the switching control signal is generated as a gate-low voltage during the first to fourth periods. The method according to claim 1,
During the fifth period of rest period,
Wherein the first to third scan signals, the control signal, and the emission signal are generated at a gate high voltage. 11. The method of claim 10,
During a sixth period subsequent to the fifth period and sensing the drain-source current of the driving TFT,
The first scan signal and the emission signal are generated at the gate high voltage,
And the third scan signal and the control signal are generated at a gate low voltage lower than the gate high voltage. 12. The method of claim 11,
During the seventh period which is continuous to the sixth period and which is the rest period,
Wherein the first to third scan signals, the control signal, and the emission signal are generated at a gate high voltage. 13. The method of claim 12,
The display panel further includes a switching control line,
In the display panel,
A first switch for connecting the data line with a source drive IC for supplying the data voltage in response to a switching control signal of the switching control line;
An inverter for inverting the switching control signal; And
And a second switch for connecting the current sensing circuit and the data line in response to the switching control signal inverted by the inverter. 14. The method of claim 13,
Wherein the switching control signal is generated at a gate high voltage during the first to fourth periods.

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