KR101931345B1 - Method and circuit for converting infra-red analog signal into digital signal - Google Patents

Abstract

1. A circuit for converting an infrared analog signal to a digital signal, comprising: a ramp generator for generating a ramp-up ramp signal; A counter code which is configured by setting the bits output by the multiphase counter to less significant bits, setting the bits output by the gray code counter to more significant bits, A counter for outputting a counter value; And at least one column circuit for comparing the infrared analog signal and the ramp signal and storing the bit values corresponding to the infrared analog signal among the bit values of the counter code as a digital signal based on the comparison result .

Description

[0001] The present invention relates to a method and a circuit for converting an infrared analog signal into a digital signal,

This disclosure relates to methods and circuits for converting infrared analog signals to digital signals.

Infrared image systems are used in various fields such as CCTV, automobile assistant vision system, as well as military equipment by utilizing the fact that they can detect objects without light. As the application fields of the infrared image system have diversified, studies are being conducted to improve the resolution, resolution and portability of the infrared image system.

Infrared imaging systems include an analog-to-digital converter (ADC) that converts analog signals to digital signals. In order for an infrared imaging system to have a high resolution, it is required that a high frequency clock signal be applied to the analog-to-digital converter. As the frequency of the clock signal applied to the analog-to-digital converter increases, the infrared image system becomes vulnerable to digital noise, and the power consumption of the infrared image system becomes excessive, resulting in low portability.

There is a need for a technique for reducing the power consumption of an infrared image system and for increasing immunity against digital noise so as to solve the above-mentioned problems and to improve the performance of an infrared image system.

Various embodiments are directed to a method and circuit for converting an infrared analog signal to a digital signal. The technical problem to be solved by the present invention is not limited to the above-mentioned technical problems, and other technical problems can be deduced from the following embodiments.

According to one aspect of the present invention, there is provided a circuit for converting an infrared analog signal into a digital signal, comprising: a ramp generator for generating a linearly increasing ramp signal; The method comprising: setting the bits output by the multiphase counter to less significant bits, setting the bits output by the gray code counter to more significant bits, and setting the lower bits and the upper bits A counter for outputting a counter code; And at least one column circuit for comparing the infrared analog signal and the ramp signal and storing bit values corresponding to the infrared analog signal among the bit values of the counter code based on the comparison result, .

According to another aspect of the present disclosure, a method of converting an infrared analog signal to a digital signal includes generating a linearly increasing ramp signal; Setting the bits output by the multiphase counter to the lower bits; Setting the bits output by the gray code counter to upper bits; Outputting a counter code composed of the lower bits and the upper bits; Comparing the infrared analog signal and the ramp signal; And storing the bit values corresponding to the infrared analog signal among the bit values of the counter code as the digital signal based on the comparison result.

The counter included in the circuit for converting the infrared analog signal to the digital signal according to the present disclosure can set the bits output from the multi-phase counter to the lower bits of the counter code. As the lower bits of the counter code are provided from the multiphase counter, the frequency of the clock signal applied to the circuit for converting the infrared analog signal into a digital signal may be lowered.

As the frequency of a clock signal applied to a circuit for converting an infrared analog signal into a digital signal is lowered, the power consumed by the circuit can be reduced, and the resistance to the digital noise of the circuit can be increased.

The counter included in the circuit for converting the infrared analog signal into the digital signal according to the present disclosure can set the bits output by the gray code counter to the upper bits of the counter code. As the upper bits of the counter code are composed of gray code, the error due to the noise of the digital signal outputted by the circuit can be reduced.

1 is a block diagram showing the configuration of a conventional analog-to-digital converter and a graph for explaining a process of detecting an infrared analog signal.
2 is a block diagram showing a configuration of a circuit for converting an infrared analog signal into a digital signal according to some embodiments.
3 is a circuit diagram of a multi-phase counter according to some embodiments.
4 is a circuit diagram of a gray code counter according to some embodiments.
FIG. 5 is a graph for explaining the operation of a counter for outputting a plurality of bits in a conventional manner. FIG.
6 is a graph illustrating an operation in which a multi-phase counter according to some embodiments outputs a plurality of bits.
7 is a table showing a difference between a general binary code and a gray code.
8 is a diagram illustrating a circuit for converting an infrared analog signal into a digital signal and a graph for explaining a process of converting an infrared analog signal to a digital signal according to some embodiments.
9 is a flowchart illustrating a method of converting an infrared analog signal into a digital signal according to some embodiments.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. It is to be understood that the following description is intended to illustrate the embodiments and not to limit or limit the scope of the invention. Those skilled in the art can easily deduce from the detailed description and examples that the scope of the present invention falls within the scope of the right.

As used herein, the terms " comprising " or " comprising " and the like should not be construed as necessarily including the various elements or steps described in the specification, May not be included, or may be interpreted to include additional components or steps.

The present embodiments relate to a method and a circuit for converting an infrared analog signal into a digital signal, and a detailed description thereof will be omitted with respect to matters widely known to those skilled in the art.

1 is a block diagram showing the configuration of a conventional analog-to-digital converter and a graph for explaining a process of detecting an infrared analog signal.

Referring to FIG. 1, a conventional column-level single slope analog-to-digital converter may include a global circuit and a plurality of column circuits. A conventional analog-to-digital converter can receive an infrared analog signal (Vin1, Vin2) and convert the received signal through each of the column circuits into an N-bit digital signal corresponding to the received signal.

The global circuit can generate a linearly increasing ramp signal and output a counter code composed of a plurality of bits. Each of the plurality of column circuits can compare an infrared analog signal with a ramp signal, and can store a counter code corresponding to an infrared analog signal.

1, a bit value D2 corresponding to the infrared analog signal Vin1 and a bit value D2 corresponding to the infrared analog signal Vin2 among the bit values of the counter code outputted by the global circuit, The process of determining the value D1 is shown.

As the number of bits N of the counter code output by the global circuit increases, the resolution of the infrared image system including the analog-to-digital converter can be improved, but the frequency of the clock signal applied to the analog-to-digital converter can be increased.

The resolution and the frame rate of the infrared image system are increased and the power consumption of the infrared image system may increase as the frequency of the clock signal increases to provide a higher resolution. Also, as the frequency of the clock signal increases, the infrared image system may become vulnerable to digital noise such as jitter. Therefore, a technique for lowering the frequency of the clock signal applied to the analog-to-digital converter is required.

2 is a block diagram showing a configuration of a circuit for converting an infrared analog signal into a digital signal according to some embodiments.

2, the circuit 1 for converting an infrared analog signal into a digital signal according to the present disclosure includes a lamp generator 30, a counter 15, at least one column circuit 45 and a serial converter 60 . Although only the components related to the present embodiment are shown in the circuit 1 shown in Fig. 2, it is to be understood that other general components other than the components shown in Fig. 2 may be further included in the circuit 1, It will be understood by those of ordinary skill in the art to which the examples relate.

The ramp generator 30 employs a capacitive transimpedance amplifier (CTIA) architecture and can generate linearly increasing ramp signals. The ramp signal can be applied to each of the at least one column circuits 45.

The counter 15 can output a counter code composed of a plurality of bits. The counter 15 may include a multi-phase counter 10 and a gray code counter 20. The plurality of bits constituting the counter code may be composed of the bits output from the multi-phase counter 10 and the bits output from the gray code counter 20. [ The counter code may be applied to each of at least one column circuit 45.

The counter 15 may set the bits output by the multiphase counter 10 to lower bits and set the bits output by the gray code counter 20 to upper bits. For example, the multiphase counter 10 may output 1100 ₍₂₎ , and the gray code counter 20 may output 1110011100 ₍₂₎ . The counter 15 may output a counter code having the bit values of 11100111001100 ₍₂₎ by setting 1100 ₍₂₎ to the lower bits and 1110011100 ₍₂₎ to the upper bits.

Although the multiphase counter 10 according to the present disclosure outputs 4 bits, the gray code counter 20 outputs 10 bits, and the counter code is configured to be composed of 14 bits, the present invention is not limited thereto, The gray code counter 20 can output any natural number n bits and the counter code can output any natural number m bits and the counter code can output n bits of n + m Bit. ≪ / RTI >

The bit values of the counter code output by the counter 15 may change over time. For example, when the counter code is composed of 14 bits, the counter 15 can sequentially output 2 ¹⁴ values corresponding to ¹⁴ bit values in accordance with time.

The at least one column circuit 45 can compare the infrared analog signal and the ramp signal and store the bit values corresponding to the infrared analog signal among the bit values of the counter code as a digital signal based on the comparison result. Each of the at least one column circuits 45 may comprise a comparator 40 and a memory 50. On the other hand, the at least one column circuit 45 may further include a control unit (not shown) for controlling the comparison operation of the comparator 40 and the storing operation of the memory 50.

The comparator 40 receives the infrared analog signal and the ramp signal through the terminals of the amplifier, and can determine when the infrared analog signal and the ramp signal match. Since the ramp signal increases linearly with time, the point of time when both signals match can be changed according to the size of the received infrared analog signal.

The memory 50 may store bit values at a time point when the infrared analog signal and the ramp signal match among the bit values of the counter code. The control part included in at least one column circuit 45 can control the memory 50 to store the bit values at the time when the memory 50 matches both signals. The bit values and the ramp signal of the counter code change with time and the comparator 40 can determine when the infrared analog signal and the ramp signal coincide with each other so that from the bit values stored in the memory 50, The size of the infrared analog signal received by the receiver 40 can be derived.

At least one column circuit 45 may simultaneously perform comparison of the infrared analog signal and the ramp signal, and concurrently store the bit values corresponding to the infrared analog signal. Therefore, the operations of the at least one column circuit 45 can be performed in parallel.

The serializer 60 may sequentially output the bit values stored in at least one column circuit 45. The serializer 60 may sequentially output the bit values stored in parallel by the at least one column circuit 45 and sequentially output the bit values.

3 is a circuit diagram of a multi-phase counter according to some embodiments.

Referring to FIG. 3, the multi-phase counter 10 includes a plurality of D-flip-flops. Each of the plurality of D-flip flops outputs a pulse, and the pulses output by the plurality of D-flip flops have the same frequency and have different phases from each other. As illustrated in FIG. 3, the multi-phase counter 10 may include eight D-flip flops. A specific example of the pulses output by the plurality of D-flip-flops is shown in Fig.

6 is a graph illustrating an operation in which a multi-phase counter according to some embodiments outputs a plurality of bits.

Referring to FIG. 6, eight pulses M0 to M7 output by the eight D-flip flops included in the multiphase counter 10 are shown. As each D-flip-flop passes the phase of the pulse output by each D-flip-flop, the eight pulses M0 to M7 may have the same frequency and different phases from each other. The value of each of the eight pulses M0 to M7 may correspond to 0 or 1 and the values of the eight pulses M0 to M7 may have 16 different values depending on the time of measurement . The 16 values may correspond to 4 bits, so that the multiphase counter 10 including 8 D-flip flops can output 4 bits.

3 and 6 illustrate that the multiphase counter 10 includes eight D-flip-flops for outputting four bits, but it is not limited thereto, and a different number of D-flip flops, including a different number of D- Can be output. For example, the multiphase counter 10 may output six bits, including 32 D-flip flops.

The multi-phase counter 10 according to the present disclosure can lower the frequency of the clock signal compared to the case of employing a conventional binary counter. The binary counter can be implemented in such a manner that, unlike the multiphase counter 10, the output of the D-flip-flop of the previous stage is applied to the clock terminal of the D-flip-flop of the next stage. A specific example of the pulses output by the binary counter is shown in FIG.

FIG. 5 is a graph for explaining the operation of a counter for outputting a plurality of bits in a conventional manner. FIG.

Referring to FIG. 5, four pulses output by the binary counter and corresponding to four bits are shown. The value of each of the four pulses B0 to B3 may correspond to 0 or 1 and the values of the four pulses B0 to B3 may correspond to 16 different Values.

Referring to Figures 5 and 6, two different schemes for outputting 4 bits can be compared. In the operation of the binary counter shown in FIG. 5, the period of the pulse B0 corresponding to the least significant bit (LSB) among the four bits may be T. FIG. In contrast, in the operation of the multiphase counter 10 shown in FIG. 6, the period of the pulses M0 to M7 may be 8T. Therefore, although the 1 / T clock frequency is required for the binary counter shown in FIG. 5 to operate, a lower 1 / (8T) clock frequency is required for the multi-phase counter 10 shown in FIG. . Consequently, the multiphase counter 10 can operate at a lower pulse frequency than the binary counter when outputting the same number of bits.

As the circuit 1 according to the present disclosure employs the multi-phase counter 10, the clock frequency applied to the circuit 1 can be reduced. As the clock frequency applied to the circuit 1 decreases, the power consumption of the infrared image system employing the circuit 1 can be reduced, and the portability can be improved as the power consumption is reduced.

In view of the fact that the higher the operating frequency of the circuit 1 is, the more susceptible to the digital noise such as jitter, the circuit 1 according to the present disclosure adopts the multiphase counter 10 so that at least one column circuit The resistance to noise of the lower bits constituting the counter code applied to the counter 45 can be improved.

4 is a circuit diagram of a gray code counter according to some embodiments.

Referring to Fig. 4, the gray code counter 20 includes a plurality of stages. Each of the plurality of stages outputs pulses, and the pulses output by the plurality of stages have different frequencies from each other and have different phases from each other. Each of the plurality of stages may comprise two consecutive D-flip flops. As illustrated in FIG. 4, the gray code counter 20 may include 10 stages and may output 10 bits.

The bits output by the gray code counter 20 may constitute a gray code. The bits constituting the gray code may correspond to the binary values in such a manner that only one bit is changed when the value of the binary number is changed by one. Advantages of the gray code counter 20 outputting the bits constituting the gray code instead of the general binary code can be explained with reference to Fig.

7 is a table showing a difference between a general binary code and a gray code.

Referring to FIG. 7, a binary code composed of 4 bits and a gray code composed of 4 bits can be compared. When the most significant bit (MSB) is changed from 0 to 1 due to digital noise or the like, a binary code may be different by 8, whereas a gray code may be different by 1.

The circuit 1 according to the present disclosure is applied to at least one column circuit 45 as it adopts the gray code counter 20 in view of the fact that even when the most significant bits are damaged by noise, The immunity to the noise of the upper bits constituting the applied counter code can be improved.

2, the gray code counter 20 is capable of receiving a signal output from the multiphase counter 10 and receiving the counter code output from the multiphase counter 10 and output by the counter 15, Lt; RTI ID = 0.0 > bits, < / RTI > The bits to be synchronized can be set to the upper bits constituting the counter code output by the counter 15. [ Therefore, the bits output by the multiphase counter 10 and the bits output by the gray code counter 20 can be synchronized to constitute a counter code output by the counter 15. [

8 is a diagram illustrating a circuit for converting an infrared analog signal into a digital signal and a graph for explaining a process of converting an infrared analog signal to a digital signal according to some embodiments.

Referring to Fig. 8, a circuit 1 for converting an infrared analog signal according to the present disclosure into a digital signal is shown, and a graph showing the operation waveform of the circuit 1 according to the present disclosure is shown. The circuit 1 may include a counter 15 including a ramp generator 30, a multiphase counter 10 and a gray code counter 20, at least one column circuit 45 and a serializer 60 have.

The ramp signal generated by the ramp generator 30 increases linearly with time, and the infrared analog signal Vin received by the comparator 40 included in at least one column circuit 45 at a certain time point Can be matched. The output signal Vcomp of the comparator 40 can be changed from 0 to 1 at the moment when both signals coincide.

The bits corresponding to the pulses M0 to M7 output by the multiphase counter 10 and the bits corresponding to the pulses G0 to G9 output by the gray code counter 20 are also changed . The bits corresponding to the pulses M0 to M7 are set to the lower 4 bits of the counter code outputted by the counter 15 at the time when the output signal Vcomp of the comparator 40 is changed from 0 to 1, (G0 to G9) may be set to the upper 10 bits of the counter code. The memory 50 can store a counter code composed of 14 bits in 14 terminals (B0 to B13).

Meanwhile, the ramp generator 30 may include a DC current source and a capacitor, and may output a ramp signal based on a voltage across a capacitor that is integrated when a DC current from the DC current source flows through the capacitor. Specifically, the amplifier included in the ramp generator 30 allows all the current of the DC current source to flow to the capacitor, and the voltage across the capacitor increases linearly with the relationship between voltage and current across the capacitor, Can be generated.

The operation of the components included in the circuit 1 according to the present disclosure can be synchronized by a reset signal Reset. 8, when the reset signal Reset is applied, the ramp generator 30 is initialized to regenerate the ramp signal, the output Vcomp of the comparator 40 is initialized from 1 to 0, The counter 10 and the gray code counter 20 can be synchronized with the operations performed by the ramp generator 30, the counter 15 and the at least one column circuit 45, such as outputting the counter code again.

9 is a flowchart illustrating a method of converting an infrared analog signal into a digital signal according to some embodiments. Referring to FIG. 9, a method of converting an infrared analog signal into a digital signal is comprised of steps that are processed in a time-series manner in the circuit 1 shown in FIGS. 2 to 8. Therefore, the contents described above with respect to the circuit 1 of FIG. 2 to FIG. 8 can be applied to the method of converting the infrared analog signal of FIG. 9 into a digital signal even if omitted from the following description.

In step s910, the circuit 1 may generate a ramp signal that increases linearly through the ramp generator 30.

In step s920, the circuit 1 is constituted by the bits output by the multiphase counter 10 set to the lower bits through the counter 15 and the bits output by the gray code counter 20 set to the upper bits Can be output.

In step s930, the circuit 1 compares the infrared analog signal and the ramp signal through at least one column circuit 45 and stores the bit values corresponding to the infrared analog signal among the bit values of the counter code as a digital signal have.

On the other hand, a method for converting an infrared analog signal to a digital signal may be recorded in a computer-readable recording medium having recorded thereon one or more programs including instructions for executing the method. Examples of the computer-readable recording medium include magnetic media such as a hard disk, a floppy disk and a magnetic tape, optical media such as CD-ROM and DVD, a floptical disk, Magneto-optical media, and hardware devices specifically configured to store and execute program instructions such as ROM, RAM, flash memory, and the like. Examples of program instructions include machine language code such as those generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter or the like.

While the present invention has been particularly shown and described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, .

1: circuit that converts infrared analog signal to digital signal
10: Multiphase Counter
15: Counter
20: Gray code counter
30: Lamp generator
40: comparator
45: at least one column circuit
50: Memory
60: serializer

Claims (12)

1. A circuit for converting an infrared analog signal into a digital signal,
A ramp generator for generating a linearly increasing ramp signal;
The method comprising: setting the bits output by the multiphase counter to less significant bits, setting the bits output by the gray code counter to more significant bits, and setting the lower bits and the upper bits A counter for outputting a counter code; And
And at least one column circuit for comparing the infrared analog signal and the ramp signal and for storing bit values corresponding to the infrared analog signal among the bit values of the counter code based on the comparison result, Circuit. The method according to claim 1,
Wherein each of the at least one column circuits comprises:
A comparator for determining when the infrared analog signal and the ramp signal match, and a memory for storing bit values at the time among the bit values of the counter code. The method according to claim 1,
The multi-
A plurality of D-flip-flops for outputting a plurality of pulses having the same frequency and different phases from each other,
And outputs the bits set to the lower bits based on the values of the plurality of pulses. The method according to claim 1,
The gray code counter includes:
A plurality of stages outputting a plurality of pulses having different frequencies and different phases from each other,
Outputting the bits set to the upper bits based on the values of the plurality of pulses,
Outputs bits set to upper bits constituting a gray code in which only one bit is changed when the value of the binary number is changed by 1,
Wherein each of the plurality of stages comprises two consecutive D-flip flops. The method according to claim 1,
The gray code counter includes:
Receiving a signal output from the multi-phase counter,
And outputs the bits set to the upper bits that are synchronized with the bits set to the lower bits. The method according to claim 1,
The multi-
4 bits are output,
The gray code counter includes:
10 bits are output,
The above-
And outputs the counter code composed of 14 bits. The method according to claim 1,
Further comprising a serializer that sorts and sequentially outputs bit values stored in the at least one column circuit. The method according to claim 1,
Wherein the lamp generator comprises:
A DC current source and a capacitor,
And outputs the ramp signal based on a voltage across the capacitor that is integrated when the direct current from the direct current source flows into the capacitor. The method according to claim 1,
Said at least one column circuit comprising:
Perform simultaneous comparisons of the signals, and concurrently store the bit values. The method according to claim 1,
Wherein the ramp generator, the counter and the operations performed by the at least one column circuit are synchronized by a reset signal applied to the circuit. A method for converting an infrared analog signal to a digital signal,
Generating a linearly increasing ramp signal;
Outputting a counter code consisting of bits outputted by a multiphase counter set to lower bits and bits output from a gray code counter set to upper bits;
And comparing the infrared analog signal and the ramp signal to store bit values corresponding to the infrared analog signal among the bit values of the counter code as the digital signal. 12. A computer-readable recording medium on which a program for implementing the method according to claim 11 is recorded.

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