KR101922177B1 - Organic light emitting display apparatus and method of manufacturing organic light emitting display apparatus - Google Patents

Abstract

One embodiment of the present invention provides a light emitting device comprising a substrate, a plurality of light emitting devices formed on the substrate, and a plurality of capacitors located on at least one side of the light emitting device, the capacitors being formed in a trench An organic light emitting display, and a method of manufacturing the organic light emitting display.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting diode (OLED) display,

An embodiment of the present invention relates to an organic light emitting display and a method of manufacturing the organic light emitting display.

In recent years, the display device has been replaced by a thin portable flat display device. Among the flat panel display devices, the organic light emitting display device is a self-luminous display device, and has a wide viewing angle, excellent contrast, and fast response speed, and is attracting attention as a next generation display device.

The organic light emitting display includes an intermediate layer, a first electrode, and a second electrode. The intermediate layer includes an organic light emitting layer. When a voltage is applied to the first electrode and the second electrode, visible light is generated in the organic light emitting layer.

SUMMARY OF THE INVENTION It is a primary object of the present invention to provide an organic light emitting display, an organic light emitting display, and a method of manufacturing an organic light emitting display in which the light emitting area is increased and the light extraction efficiency is improved.

An organic light emitting display according to an embodiment of the present invention includes a substrate, a plurality of light emitting devices formed on the substrate, and a plurality of capacitors located on at least one side of the light emitting device, May be formed in the trenches formed in the substrate.

The capacitors may be spaced apart from the light emitting device.

The capacitor may be disposed on both sides of the light emitting element with the light emitting element interposed therebetween.

The capacitor comprising a first capacitor disposed in a first trench formed on the substrate and spaced apart from a first side of the light emitting device and a second capacitor disposed on a second side of the substrate opposite to the first side of the light emitting device, And a second capacitor disposed in a second trench formed in the second trench.

The first capacitor may be formed longer than the length of the first side.

The second capacitor may be formed longer than the length of the second side.

One embodiment of the present invention is a semiconductor device including at least one transistor having a semiconductor layer, a gate electrode, and source and drain electrodes, and a gate insulating layer disposed between the semiconductor layer and the gate electrode, A pixel electrode formed on the gate insulating layer and electrically connected to the transistor, an intermediate layer disposed on the pixel electrode, the intermediate layer having a common layer and a light emitting layer, and an intermediate layer disposed opposite to the pixel electrode with the intermediate layer interposed therebetween An opposite electrode may be provided.

Wherein the first capacitor comprises a first capacitor lower electrode and a first capacitor upper electrode disposed in the first trench and the second capacitor comprises a second capacitor lower electrode disposed in the second trench and a second capacitor lower electrode disposed in the second trench, An upper electrode may be provided.

The gate insulating layer may be interposed between the first capacitor lower electrode and the first capacitor upper electrode, and between the second capacitor lower electrode and the second capacitor upper electrode.

The first capacitor lower electrode and the second capacitor lower electrode may be made of the same material as the semiconductor layer.

The first capacitor upper electrode and the second capacitor upper electrode may be made of the same material as the pixel electrode.

The pixel electrode may be made of a transparent conductive material.

Wherein the common layer comprises a hole injecting layer, a hole transporting layer, an electron transporting layer, and an electron injecting layer, wherein the hole injecting layer, the hole transporting layer, the light emitting layer, the electron transporting layer, .

Wherein the counter electrode is disposed on the first capacitor upper electrode and the second capacitor upper electrode and between the counter electrode and the first capacitor upper electrode or between the counter electrode and the second capacitor lower electrode, Layer, the hole transporting layer, the electron transporting layer, or the electron injecting layer may be interposed.

The semiconductor layer may be amorphous silicon or crystalline silicon.

The counter electrode may be a reflective electrode that reflects light emitted from the light emitting layer.

A method of manufacturing an organic light emitting display according to an embodiment of the present invention includes the steps of preparing a partition substrate using a plurality of light emitting device regions, a plurality of capacitor regions, and a plurality of transistor regions, forming a trench in the capacitor region A first mask process step of forming an active layer in the transistor region on the substrate and a capacitor lower electrode in the trench; a first mask process step of forming a pixel electrode on the light emitting device region, A second electrode unit for forming a capacitor upper electrode formed on the lower electrode of the capacitor in the first electrode unit, a contact hole exposing both edges of the active layer, A third mask process step of forming an interlayer insulating film in which openings for exposing the second electrode unit are formed; And a source electrode and a drain electrode which are in contact with the active layer through the contact hole are formed on the first electrode unit and the pixel electrode is formed from the first electrode unit, A fifth mask process step of forming a pixel defining layer exposing at least a part of the pixel electrode; forming an intermediate layer including a common layer and a light emitting layer on the pixel electrode, Forming the common layer, and forming a counter electrode on the intermediate layer and the common layer.

The capacitor region may include a first capacitor region and a second capacitor region disposed on both sides of the light emitting region with the light emitting region interposed therebetween.

Wherein the trench comprises a first trench formed in the first capacitor region spaced apart from a first side of the light emitting region and a second trench formed in the second capacitor region spaced apart from a second side opposite the first side of the light emitting region. 2 trenches.

A first capacitor made up of the first capacitor lower electrode and the first capacitor upper electrode formed in the first trench and a second capacitor lower electrode formed in the second trench and the second capacitor upper electrode formed in the second trench, 2 < / RTI > capacitors.

Wherein the second mask processing step comprises: Forming a gate insulating layer on the result of the first mask process; and forming a first conductive layer and a second conductive layer on the gate insulating layer in order and patterning the gate electrode, the pixel electrode, And forming a second electrode unit for forming the first capacitor upper electrode and a third electrode unit for forming the second capacitor lower electrode.

Wherein the third mask processing step comprises: A contact hole for exposing source and drain regions of the semiconductor layer in the first insulating layer, and a contact hole for exposing the source and drain regions of the semiconductor layer in the first insulating layer, And an opening for exposing the third electrode unit may be formed to form an interlayer insulating layer.

Wherein the fourth mask processing step comprises: Forming a third conductive layer on the interlayer insulating layer; patterning the third conductive layer to form the source electrode and the drain electrode; forming a second conductive layer Forming the pixel electrode of the first conductive layer and removing the second conductive layer constituting the second electrode unit to form the first capacitor upper electrode of the first conductive layer And forming the second capacitor upper electrode made of the first conductive layer by removing the second conductive layer constituting the third electrode unit.

The fifth mask process step may form a pixel defining layer by forming a second insulating layer on the result of the fourth mask process and patterning the second insulating layer to expose the transparent conductive material of the pixel electrode .

The counter electrode may be formed on the common layer in the trench.

Wherein the common layer comprises a hole injecting layer, a hole transporting layer, an electron transporting layer, and an electron injecting layer, wherein the hole injecting layer, the hole transporting layer, the light emitting layer, the electron transporting layer, .

Wherein the common layer comprises a first common layer and a second common layer, the common layer is formed on the first substrate other than the pixel electrode, and the first common layer, the light emitting layer, The second common layer can be stacked in a line-by-line manner.

The counter electrode may be a reflective electrode that reflects light emitted from the light emitting layer.

The semiconductor layer may be formed of amorphous silicon or crystalline silicon.

According to an embodiment of the present invention, the light emitting area of the organic light emitting display device can be increased and the light extraction efficiency can be improved.

1 is a plan view schematically showing a structure of an organic light emitting display according to an embodiment of the present invention.
2 is a cross-sectional view taken along the line II in Fig.
3 to 10 are cross-sectional views schematically showing a manufacturing process of the organic light emitting display shown in FIG.
11 is a cross-sectional view of an organic light emitting display device showing a path of light generated in a light emitting layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view schematically showing the structure of an organic light emitting diode display 1 according to an embodiment of the present invention.

Referring to FIG. 1, the organic light emitting diode display 1 includes a first substrate 10 including a plurality of light emitting devices, and a second substrate 70 bonded to the first substrate 10 through a sealing process.

A thin film transistor (TFT), a light emitting device EL, capacitors Cst1 and Cst2, and the like may be formed on the first substrate 10. The first substrate 10 may be a crystalline silicon (LTPS) substrate, a glass substrate, a plastic substrate, or the like.

The second substrate 70 may be an encapsulating substrate disposed on the first substrate 10 to block TFTs and light emitting devices provided on the first substrate 10 from external moisture, air, and the like. The second substrate 70 is positioned to face the first substrate 10 and the first substrate 10 and the second substrate 70 are bonded together by a sealing member 90 disposed along the edge thereof. The second substrate 70 may be a glass substrate, a plastic substrate, or a stainless steel (SUS) substrate.

The first substrate 10 includes a light emitting region DA through which light is emitted and a non-light emitting region NDA located outside the light emitting region DA. According to the embodiments of the present invention, the sealing member 90 is disposed in the non-emission region NDA outside the light emitting region DA to bond the first substrate 10 and the second substrate 70 together.

As described above, the organic light emitting device EL, the thin film transistor (TFT) driving the organic light emitting device EL, and the wiring electrically connected thereto are formed in the light emitting area DA of the first substrate 10. The non-emission region NDA may include a pad region 5 in which the pad electrode PAD extending from the wiring of the emission region DA is located.

Referring to FIG. 1, a part of the light emitting area DA is enlarged. A first capacitor Cst1 and a second capacitor Cst2 may be disposed with the organic light emitting element EL therebetween. Each of the first capacitor Cst1 and the second capacitor Cst2 may be disposed apart from both sides of the organic light emitting device EL. This will be described later.

2 is a cross-sectional view taken along the line I-I in Fig.

2, an OLED display 1 according to an embodiment of the present invention includes a transistor region 2, a first capacitor region 3a, a second capacitor region 3b, and a light emitting element region 4).

The transistor region 2 is provided with a thin film transistor (TFT) as a driving element. The thin film transistor TFT may be composed of the active layer 21, the gate electrode 20, and the source / drain electrodes 26 and 27.

The gate electrode 20 may be composed of a gate lower electrode 23 and a gate upper electrode 25 located above the gate lower electrode 23. The gate lower electrode 23 may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin oxide And may contain at least one selected from the group consisting of indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). The gate upper electrode 25 may be formed of a single layer of a metal such as Mo, MoW, Al-based alloy, or an alloy of a metal, or a plurality of layers of two or more layers, but is not limited thereto. A gate insulating layer 12 is interposed between the gate electrode 20 and the active layer 21 for insulation therebetween. In addition, the active layer 21 may include a channel region 21c and source / drain regions 21s / 21d. Source / drain regions 21s / 21d doped with a high concentration of impurities are formed at both edges of the channel region 21c, and they can be connected to the source / drain electrodes 26/27, respectively.

A first trench 10a and a second trench 10b are formed in the first capacitor region 3a and the second capacitor region 3b on the first substrate 10 and the first trench 10a and the second trench 10b are formed in the first trench 10a, The capacitor Cst1 may be formed and the second capacitor Cst2 may be formed in the second trench 10b.

The first trench 10a and the second trench 10b are intaglio patterns formed on the first substrate 10. That is, the first trench 10a and the second trench 10b may be a depressed pattern formed on one surface of the first substrate 10 on which the pixel electrode 43 is formed toward the other surface facing the other surface. The first trench 10a and the second trench 10b may be formed with the light emitting element region 4 therebetween. The first trench 10a may be spaced apart from one side of the light emitting element region 4 and the second trench 10b may be spaced apart from the other side of the light emitting element region 4, The lengths of the first trench 10a and the second trench 10b may be longer than the length of the pixel electrode 43.

A first capacitor Cst1 may be formed in the first trench 10a and a second capacitor Cst2 may be formed in the second trench 10b. The first capacitor Cst1 includes a first capacitor lower electrode 31a and a capacitor upper electrode 33a with a gate insulating layer 12 interposed therebetween and the second capacitor Cst2 is connected to the second capacitor sub- An electrode 31b and a capacitor upper electrode 33b, and a gate insulating layer 12 may be interposed therebetween. Here, the first and second capacitor lower electrodes 31a and 31b may be formed of the same material as the active layer 21 of the thin film transistor TFT. The first and second capacitor lower electrodes 31a and 31b are made of a semiconductor material and doped with impurities, thereby improving electrical conductivity. On the other hand, each of the first and second capacitor upper electrodes 33a and 33b may be formed on the gate insulating layer 12 in the first and second trenches 10a and 10b.

Since the capacitors Cst1 and Cst2 are formed in the trenches 10a and 10b as described above, the area occupied by the capacitors Cst1 and Cst2 is reduced compared with the case where the capacitors Cst1 and Cst2 are formed on the plane of the first substrate 10, The area of the light emitting layer can be made larger, thereby improving the light emitting efficiency.

The light emitting element region 4 is provided with an organic light emitting element EL. The organic light emitting element EL includes a pixel electrode 43 connected to one of the source / drain electrodes 26/27 of the thin film transistor TFT, an opposite electrode 45 formed to face the pixel electrode 43, And an intermediate layer 44 interposed in the intermediate layer 44. The pixel electrode 43 is formed of a transparent conductive material and may be formed of the same material in the same layer as the gate lower electrode 23 of the thin film transistor TFT. The organic light emitting element EL will be described later.

3 to 10 are sectional views schematically showing a manufacturing process of the organic light emitting diode display 1 shown in FIG. Hereinafter, a manufacturing process of the OLED display 1 shown in FIG. 2 will be schematically described.

First, as shown in FIG. 3, first and second trenches 10a and 10b are formed on a first substrate 10. In detail, the first substrate 10 may be formed of a transparent glass material having SiO ₂ as a main component. The first substrate 10 is not limited thereto, and various substrates such as a transparent plastic material or a metal material can be used. The first and second trenches 10a and 10b are engraved patterns formed on the first substrate 10 in the other direction. The first and second trenches 10a and 10b may be formed on both sides of the light emitting element region 4 with the light emitting element region 4 therebetween.

Next, an auxiliary layer 11 is formed on the first substrate 10, as shown in FIG. An auxiliary layer 11 such as a barrier layer, a blocking layer, and / or a buffer layer for preventing impurity ions from diffusing on the upper surface of the first substrate 10, preventing penetration of moisture or outside air, and planarizing the surface . Secondary layer 11 is formed by various deposition methods such as SiO ₂ and / or by using a SiN _x and so on, PECVD (plasma enhanced chemical vapor deposition) method, APCVD (atmospheric pressure CVD) method, LPCVD (low pressure CVD) method .

Next, the active layer 21 of the thin film transistor (TFT), the first capacitor lower electrode 31a and the second capacitor lower electrode 31b may be formed on the auxiliary layer 11. In detail, a polycrystalline silicon layer (not shown) is formed by first depositing an amorphous silicon layer (not shown) on the auxiliary layer 11 and then crystallizing the amorphous silicon layer (not shown). The amorphous silicon may be formed by rapid thermal annealing (RTA), solid phase crystallization (SPC), excimer laser annealing (ELA), metal induced crystallization (MIC), metal induced lateral crystallization (MILC) And can be crystallized by various methods. The polycrystalline silicon layer is formed on the active layer 21 and the first capacitor lower electrode 31a and the second capacitor lower electrode 31b of the thin film transistor TFT by a mask process using a first mask (not shown) As shown in FIG. The first capacitor lower electrode 31a is formed on the auxiliary layer 11 in the first trench 10a and the second capacitor lower electrode 31b is formed on the auxiliary layer 11 in the second trench 10b .

As another embodiment, the first and second trenches 10a and 10b on the first substrate 10 may be formed simultaneously with the formation of the active layer 21. [ More specifically, after the auxiliary layer 11 is formed on the first substrate 10, an amorphous silicon layer (not shown) is deposited on the auxiliary layer 11 and crystallized to form a polycrystalline silicon layer. Then, the first and second trenches 10a and 10b and the active layer 21 can be patterned using a halftone mask.

5, on the entire surface of the first substrate 10 having the active layer 21 and the first and second capacitor lower electrodes 31a and 31b formed thereon, a gate insulating layer 12, a first conductive layer The first conductive layer 23a and the second conductive layer 25a are sequentially formed.

The gate insulating layer 12 may be formed by depositing an inorganic insulating film such as SiN _x or SiO _x by a method such as a PECVD method, an APCVD method, or an LPCVD method. The gate insulating layer 12 is interposed between the active layer 21 of the thin film transistor TFT and the gate electrode 20 to serve as an insulating film of the thin film transistor TFT and includes a first capacitor upper electrode 33a, The second capacitor Cst2 is interposed between the capacitor lower electrode 31a and serves as a dielectric layer of the first capacitor Cst1 and is interposed between the second capacitor upper electrode 33b and the second capacitor lower electrode 31b, And serves as a dielectric layer.

The first conductive layer 23a may include one or more materials selected from transparent materials such as ITO, IZO, ZnO, or In ₂ O ₃ . The first conductive layer 23a may be patterned into the pixel electrode 43, the gate lower electrode 23, and the first and second capacitor upper electrodes 33a and 33b.

The second conductive layer 25a may include at least one selected from Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, W, MoW and Cu. can do. Preferably, the second conductive layer 25a may have a three-layer structure of Mo - Al - Mo. The second conductive layer 25a may later be patterned into the gate upper electrode 25.

However, the present invention is not limited to this, and the first conductive layer 23a may include a material having better corrosion resistance than the second conductive layer 25a, and the second conductive layer 25a may have a resistance higher than that of the first conductive layer 23a If the current comprises a well-flowing material, satisfies one embodiment of the present invention.

6, a gate electrode 20, a first electrode unit 43, 43a, a second electrode unit 33a, 35a, and a third electrode unit 34a are formed on the first substrate 10, (33b, 35b), respectively.

In detail, the first conductive layer 23a and the second conductive layer 25a, which are sequentially stacked on the entire surface of the first substrate 10, are patterned by a mask process using a second mask (not shown).

The gate electrode 20 is formed on the active layer 21 in the transistor region 2. The gate electrode 20 is formed on the gate lower electrode 23 formed as a part of the first conductive layer 23a, And a gate upper electrode 25 formed as a part of the gate electrode 15.

The gate electrode 20 is formed so as to correspond to the center of the active layer 21 and the n-type or p-type impurity is doped into the active layer 21 using the gate electrode 20 as a self- Source / drain regions 21s / 21d and a channel region 21c therebetween are formed at the edges of the active layer 21 corresponding to both sides of the gate electrode 20. [ Here, the impurity may be a boron (B) ion or a phosphorus (P) ion.

Second electrode units 33a and 35a for forming a first capacitor upper electrode 33a are formed on the first capacitor lower electrode 31a in the first capacitor region 3a and a second capacitor unit 3b The third electrode units 33b and 35b for forming the second capacitor upper electrode 33b are formed on the second capacitor lower electrode 31b and the pixel electrode 43 The first electrode units 43 and 43a are formed.

7, a first insulating layer (not shown) is formed on the entire surface of the first substrate 10 on which the gate electrode 20 is formed, and then a first insulating layer (not shown) is patterned The openings H1, H2 and H3 for exposing the pixel electrode 43, the first capacitor upper electrode 33a and the second capacitor upper electrode 33b and the source / drain regions 21s / 21d The contact holes H4 and H5 exposing a part of the interlayer insulating layer 14 are formed.

The interlayer insulating layer 14 is formed by a method such as spin coating with at least one organic insulating material selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin. The interlayer insulating layer 14 is formed to have a sufficient thickness and is formed thicker than the gate insulating layer 12 described above so that the distance between the gate electrode 20 of the thin film transistor TFT and the source / And serves as an insulating film. The interlayer insulating layer 14 may be formed of an inorganic insulating material such as the above-described gate insulating layer 12 as well as the above organic insulating material. Alternatively, the interlayer insulating layer 14 may be formed by alternately forming an organic insulating material and an inorganic insulating material have.

In detail, the first insulating layer is patterned by a mask process using a third mask (not shown) to form an interlayer insulating layer 14 having openings H1, H2 and H3 and contact holes H4 and H5 . Here, the contact holes H4 and H5 expose portions of the source / drain regions 21s / 21d, respectively,

The first opening H1 exposes the first electrode unit 43, 43a. The second opening H2 exposes the second electrode units 33a and 35a and the third opening H3 exposes the third electrode units 33b and 35b.

Next, as shown in FIG. 8, a third conductive layer (not shown) is formed on the entire surface of the first substrate 10 so as to cover the interlayer insulating layer 14, and then the third conductive layer is patterned, The drain electrode 26/27, the pixel electrode 43, the first capacitor upper electrode 33a, and the second capacitor upper electrode 33b, respectively.

The third conductive layer may be selected from the same conductive materials as the first or second conductive layer, but may be formed of various conductive materials. In addition, the conductive material is deposited to a sufficient thickness to fill between the contact holes H4 and H5 and the openings H1, H2, and H3 described above.

The third conductive layer is patterned by a mask process using a fourth mask (not shown) to form source / drain electrodes 26/27.

The pixel electrode 43, the first capacitor upper electrode 33a, and the second capacitor upper electrode 33b are formed while forming the source / drain electrodes 26/27. However, the present invention is not limited to this, and the pixel electrode 43, the first capacitor upper electrode 33a, and the second capacitor upper electrode 33b may be formed by further etching after the source / drain electrodes 26/27 are formed. Respectively.

The gate lower electrode 23, the first and second capacitor upper electrodes 33a and 33b, and the pixel electrode 43 are formed of the same material in the same layer.

Here, n-type or p-type impurities may be injected through the second and third openings H2 and H3 to dope the first and second capacitor lower electrodes 31a and 31b. The impurities injected during the doping may be the same as or different from those used for doping the active layer 21.

9, a pixel defining layer (PDL) 16 is formed on the first substrate 10, and a common layer 442 and an intermediate layer 44 are formed.

In detail, a second insulating layer (not shown) is formed on the entire surface of the first substrate 10 on which the pixel electrode 43, the source / drain electrodes 26/27, and the first and second capacitor upper electrodes 33a and 33b are formed do. At this time, the second insulating layer (not shown) may be formed by spin coating or the like with one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin. On the other hand, the second insulating layer as well as the organic insulating material as described above, SiO _2, SiNx, Al ₂ O _3, CuOx, Tb ₄ O _7, Y ₂ O _3, Nb ₂ O _5, Pr ₂ O ₃ selected from It may be formed of an inorganic insulating material. The second insulating layer may have a multi-layer structure in which an organic insulating material and an inorganic insulating material are alternated.

The second insulating layer is patterned by a mask process using a fifth mask (not shown) to form an opening to expose a central portion of the pixel electrode 43, thereby forming a pixel defining layer 16 defining a pixel.

A common layer 442 is formed on the first substrate 10 on which the pixel defining layer 16 is formed and an intermediate layer 44 including a light emitting layer is formed in an opening exposing the pixel electrode 43. [

In detail, the intermediate layer 44 is composed of a common layer 442 and a light emitting layer 441, and the common layer 442 is composed of the first common layers 442a and 442b and the second common layers 442c and 442d And the intermediate layer 44 may be disposed between the first common layers 442a and 442b and the second common layers 442c and 442d.

The first common layers 442a and 442b may be formed by sequentially stacking a hole transport layer (HTL) 442a and a hole injection layer (HIL) 442b, and the second common layer 442c and 442d may be formed by sequentially stacking an electron transport layer (ETL) 442c and an electron injection layer (EIL) 442d.

The common layer 442 is formed in a region other than the light emitting element region 4. [ That is, on the first capacitor region 3a, the second capacitor region 3b, and the pixel defining film 16 on the transistor region 2 and the first and second capacitor upper electrodes 33a and 33b, The first common layers 442a and 442b and the second common layers 442c and 442d may be sequentially stacked.

In the light emitting element region 4, the first common layers 442a and 442b are formed on the pixel electrode 43, the light emitting layer 441 is formed on the first common layers 442a and 442b, The second common layer 442c, 442d may be formed on the second common layer 442c.

The light emitting layer 441 may be an emissive layer (EML). The organic light emitting layer may be a low molecular weight or a high molecular organic material.

The intermediate layer 44 is formed by laminating the hole transport layer 442a and the hole injection layer 442b and the like in the direction of the pixel electrode 43 with the center of the organic light emitting layer as the center and the counter electrode 45, The electron transport layer 442c, the electron injection layer 442d, and the like may be stacked. In addition, various layers can be stacked as needed. At this time, usable organic materials may also be selected from copper phthalocyanine (CuPc), N, N-di (naphthalen-1-yl) -N, N'- (NPB), tris-8-hydroxyquinoline aluminum (Alq3), and the like.

In the case where the organic light emitting layer is formed of a polymer organic material, the intermediate layer 44 may include only the hole transporting layer 442a in the direction of the pixel electrode 43 with the organic light emitting layer as a center. The hole transport layer 442a may be formed by inkjet printing or spin coating using polyethylene dihydroxy thiophene (PEDOT), polyaniline (PANI), or the like. The electrode 43 can be formed. In this case, a polymer organic material such as poly-phenylenevinylene (PPV) or polyfluorene may be used as the organic material. In addition, a color pattern may be formed by a conventional method such as inkjet printing, spin coating, Can be formed.

The counter electrode 45 may be deposited on the entire surface of the first substrate 10 to form a common electrode. The counter electrode 45 may also be formed in the first trench 10a of the first capacitor region 3a and the second trench 10b of the second capacitor region 3b as shown in Fig.

In the organic light emitting diode display 1 according to the present embodiment, the pixel electrode 43 is used as an anode electrode, and the counter electrode 45 is used as a cathode electrode. Needless to say, the polarity of the electrode can of course be reversed.

In the case of a bottom emission type in which an image is formed in the direction of the first substrate 10 of the organic light emitting display device 1, the pixel electrode 43 becomes a transparent electrode, . The reflective electrode may be formed of a metal having a low work function, for example, Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Can be formed by depositing a thin film.

As described above, since the counter electrode 45 is also formed on the first and second trenches 10a and 10b formed on both sides of the organic light emitting element EL with the organic EL element therebetween, The light P1 and P2 generated in the organic light emitting element EL are not totally reflected in the first substrate 10 but are reflected by the counter electrode 45 in the first and second trenches 10a and 10b So that the light extraction efficiency is improved.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

1: organic light emitting display device 26/27: source / drain electrode
2: transistor region 3a: first capacitor region
3b: second capacitor region 4: light emitting region
10: first substrate 11: auxiliary layer
12: gate insulating layer 23a: first conductive layer
14: interlayer insulating layer 25a: second conductive layer
16: pixel defining film 20: gate electrode
21: active layer 23: gate lower electrode
25: gate upper electrode 31a: first capacitor lower electrode
31b: second capacitor lower electrode 33a: first capacitor upper electrode
33b: second capacitor upper electrode 43: pixel electrode
44: intermediate layer 45: counter electrode
70: second substrate 90: sealing member

Claims (34)

Board;
A light emitting element disposed on the substrate, the light emitting element comprising: a pixel electrode; an intermediate layer positioned on the pixel electrode and having a common layer and a light emitting layer; and a counter electrode positioned on the intermediate layer; And
Capacitors located in one side and the other side of the light emitting device so as not to overlap with the portion of the pixel electrode that contacts the intermediate layer when viewed in a direction perpendicular to the substrate; And the organic light emitting display device. The method according to claim 1,
Wherein the capacitors are spaced apart from the light emitting device. delete The method according to claim 1,
Wherein the capacitors comprise a first capacitor disposed in a first trench formed on the substrate and spaced apart from a first side of the light emitting device and a second capacitor disposed on a second side of the substrate opposite to the first side of the light emitting device, And a second capacitor disposed in a second trench formed in the first trench. 5. The method of claim 4,
Wherein the first capacitor is formed to be longer than the length of the first side portion. 5. The method of claim 4,
And the second capacitor is formed to be longer than the length of the second side portion. 5. The method of claim 4,
At least one transistor including a semiconductor layer, a gate electrode, and source and drain electrodes; And
And a gate insulating layer disposed between the semiconductor layer and the gate electrode,
Wherein the pixel electrode of the light emitting element is located on the gate insulating layer and is electrically connected to the transistor. 8. The method of claim 7,
The first capacitor having a first capacitor lower electrode and a first capacitor upper electrode disposed in the first trench,
Wherein the second capacitor comprises a second capacitor lower electrode and a second capacitor upper electrode disposed in the second trench. 9. The method of claim 8,
Wherein the gate insulating layer is interposed between the first capacitor lower electrode and the first capacitor upper electrode, and between the second capacitor lower electrode and the second capacitor upper electrode. 9. The method of claim 8,
Wherein the first capacitor lower electrode and the second capacitor lower electrode are made of the same material as the semiconductor layer. 9. The method of claim 8,
Wherein the first capacitor upper electrode and the second capacitor upper electrode are made of the same material as the pixel electrode. 12. The method of claim 11,
Wherein the pixel electrode is made of a transparent conductive material. 8. The method of claim 7,
Wherein the common layer comprises a hole injecting layer, a hole transporting layer, an electron transporting layer, and an electron injecting layer, wherein the hole injecting layer, the hole transporting layer, the light emitting layer, the electron transporting layer, The organic light emitting display device comprising: 14. The method of claim 13,
Wherein the counter electrode is disposed on the first capacitor upper electrode and the second capacitor upper electrode,
Wherein the hole injection layer, the hole transport layer, the electron transport layer, or the electron injection layer are interposed between the counter electrode and the first capacitor upper electrode, or between the counter electrode and the second capacitor lower electrode. Organic light emitting display. 8. The method of claim 7,
Wherein the semiconductor layer is amorphous silicon or crystalline silicon. 8. The method of claim 7,
Wherein the counter electrode is a reflective electrode that reflects light emitted from the light emitting layer. delete delete delete delete delete delete delete delete delete delete delete delete delete The method according to claim 1,
Wherein portions of the counter electrode are located in the trenches, and light emitted from the light emitting device is reflected by portions of the counter electrode in the trenches and is emitted to the outside. A substrate including a light emitting element region, a transistor region, and a trench-shaped first capacitor region and a second capacitor region arranged on one side and the other side of the light emitting element region so as not to overlap the light emitting element region;
A first capacitor lower electrode disposed in a trench in the first capacitor region and a second capacitor lower electrode disposed in a trench in the second capacitor region and a second capacitor lower electrode disposed in the trench of the first capacitor region, A second capacitor upper electrode disposed opposite the first capacitor lower electrode in a trench of the second capacitor region;
An active layer disposed in the transistor region and located on the same layer as the first capacitor lower electrode and the second capacitor lower electrode; a gate lower electrode positioned in the same layer as the first capacitor upper electrode and the second capacitor upper electrode; And
A pixel electrode disposed on the same layer as the gate lower electrode, the pixel electrode being disposed in the light emitting element region;
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The first capacitor upper electrode, the second capacitor lower electrode, the first capacitor lower electrode, and the second capacitor lower electrode are formed so as not to overlap with the pixel electrode portion when viewed from a direction perpendicular to the substrate , An organic light emitting display device. 32. The method of claim 31,
Wherein a length of a trench of the first capacitor region and a length of a trench of the second capacitor region are longer than a length of the pixel electrode. 32. The method of claim 31,
A first common layer, a light emitting layer, and a second common layer disposed on the pixel electrode of the light emitting element region, wherein the first common layer and the second common layer are located in regions other than the light emitting element region , An organic light emitting display device. 34. The method of claim 33,
Further comprising a counter electrode disposed on a front surface of the substrate,
The portion of the counter electrode located in the light emitting device region reflects the light emitted from the light emitting layer, and the light is reflected from portions of the counter electrode located in the first capacitor region and the second capacitor region and is emitted to the outside , An organic light emitting display device.

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