KR101906310B1 - Timing controller for liquid crystal display device and method of driving thereof - Google Patents

Abstract

The present invention discloses a liquid crystal display device. More particularly, the present invention relates to a timing controller for a liquid crystal display, which improves the problem that data stored in a line memory provided in a timing controller to which a digital gamma algorithm (DGA) is applied is changed due to external factors, Driving method.
A timing controller according to an exemplary embodiment of the present invention includes a control signal generator for receiving a timing control signal from an external system to generate a control signal of a liquid crystal display driver and a control signal generator for reading and decoding the compensation data stored in the external memory, ) To compensate the image data on a line-by-line basis, generate a checksum before and after the decoding to judge whether the temporarily stored data is erroneous, and correct the image data by compensating the image data through the compensated data Part.
Accordingly, the present invention generates a first checksum code upon reading the compensation data stored in the EEPROM, decodes the encoded compensation data for each vertical blank interval of each frame, generates and compares a second checksum code, The compensation data is re-received from the EEPROM upon the change, so that the image data can be compensated through the error power data, thereby improving the image quality degradation problem.

Description

TECHNICAL FIELD [0001] The present invention relates to a timing controller for a liquid crystal display device and a driving method thereof.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display (LCD), and more particularly, to a liquid crystal display device having a timing controller for a liquid crystal display Controller and a driving method thereof.

2. Description of the Related Art [0002] With the development of information devices such as potable devices such as mobile phones and notebook computers and high-resolution and high-quality images such as HDTVs, flat panel displays Display Device) is increasing. As such flat panel display devices, a liquid crystal display (LCD), a plasma display panel (PDP), a field emission display (FED), and an organic light emitting diode (OLED) have been actively studied. However, And realization of a large area screen, a liquid crystal display (LCD) is in the spotlight at present.

In particular, an active matrix liquid crystal display device using a thin film transistor as a switching element is suitable for displaying dynamic images.

Fig. 1 is a block diagram showing a basic configuration of a conventional liquid crystal display device, and includes a liquid crystal panel 10 and a drive circuit portion 20. Fig.

1, the liquid crystal panel 10 includes a plurality of data lines DL1 to DLm and a plurality of gate lines GL1 to GLn crossing each other in a matrix form on a glass substrate, And a thin film transistor T and a liquid crystal LC are formed in each pixel region to display a screen.

The driving circuit unit 20 includes an interface 21, a timing controller 22, a gate driving unit 25, and a data driving unit 26.

The interface 21 receives image data RGB Data input from an external system such as a personal computer or the like to the drive circuit unit 20 and a clock signal CLK, a horizontal synchronization signal Hsync, a vertical synchronization signal Vsync, And supplies the timing control signals including the enable signal DE to the timing controller 22. As the interface 21, a low voltage differential signal (LVDS) interface and a TTL interface are used. In addition, such an interface may be configured such that its functions are integrated in the timing controller 22 and integrated into a single chip.

The timing controller 22 includes a gate driver 25 configured by a plurality of integrated circuits and a control unit 26 for driving a data driver 26 including a plurality of integrated circuits using a timing control signal input through the interface 21 Signal. Related data (RGB DATA) input through the interface unit 21 and supplies the image-related data to the data driver 26 as image conversion data (RGB DATA ').

The gate driver 25 performs on / off control of the thin film transistors T arranged on the liquid crystal panel 10 in response to a gate control signal GCS input from the timing controller 22 And the gate signals GL1 to GLn on the liquid crystal panel 10 are sequentially enabled for one horizontal synchronization time period by outputting a gate signal so that the thin film transistor T on the liquid crystal panel 10 So that a data voltage of an analog waveform corresponding to the image data (RGB DATA ') supplied from the data driver 18 is applied to the pixels connected to the thin film transistors T.

The data driver 26 modulates the image data (RGB DATA ') of the digital waveform input in response to the data control signal DCS input from the timing controller 22 into analog waveforms and then outputs the data lines DL1 to DLn To the liquid crystal panel 10 by one horizontal line to control the rotation angle of the liquid crystal molecules.

In order to improve the image quality of such a liquid crystal display device, various methods have been proposed. As one of such methods, there is a method of compensating luminance and color temperature deviation of each gray level by applying a digital gamma algorithm (DGA). In the DGA method, compensation data of all gradations is stored in a non-volatile memory such as EEPROM (electrically erasable and programmable read only memory), and the input image data is supplied to the data driver 26 in correspondence with the compensation data stored in the memory to be.

In the DGA method described above, compensation data having a size of 2048 bytes X 3 is required for 10 bit resolution. However, in order to reduce waste of memory capacity, only the difference value of each gradation is stored in the EEPROM, And stores the decoded difference value, and then compensates the image data and provides it to the data driver.

However, a phenomenon that the value stored in the line memory fluctuates due to the frequency change of the clock signal CLK input from the external system, the glitch component, or the static electricity (ESD) introduced from the outside often occurs.

As a result, the image data is converted through the compensated compensation data and the quality of the image is deteriorated, which causes the reliability of the liquid crystal display device to deteriorate.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to improve the image quality degradation caused by fluctuation of data stored in a line memory of a timing controller to which a DGA is applied by changing a frequency of a clock signal or an external environment have.

According to an aspect of the present invention, there is provided a timing controller for a liquid crystal display, comprising: a control signal generator for receiving a timing control signal from an external system and generating a control signal of a liquid crystal display driver; And reading and decoding the compensation data stored in the external memory and temporarily storing the compensated data stored in the external memory to compensate the image data on a line basis, generating a checksum before and after decoding to determine whether the temporarily stored data is erroneous, And an image data modulator for compensating the image data through updated compensation data when an error occurs.

The image data modulator includes an I2C master for reading compensation data from an external memory; A checksum generator for generating a first checksum corresponding to the compensation data; A decoding unit decoding the compensation data; A line memory for temporarily storing the decoded compensation data in units of horizontal lines; A comparison unit for generating a second checksum corresponding to the compensation data stored in the line memory and for comparing the data stored in the line memory with the first checksum; And a data compensator for compensating and outputting the image data corresponding to any one of the data stored in the line memory or the updated data according to the determination result of the comparator.

And the second checksum is data obtained by encoding the compensation data stored in the line memory in a manner stored in the external memory.

And the decoding unit decodes the compensation data read by the I2C master again when the data stored in the line memory fluctuates.

And the image data modulator further includes a register for storing the compensation data read by the I2C master.

And the decoding unit decodes the compensation data stored in the register again when the data stored in the line memory fluctuates.

The image data modulator may further include a vertical blank sensing unit for providing a timing for determining whether a data variation occurs to the comparing unit in synchronization with any one of the timing control signals.

In order to accomplish the above object, a driving method of a timing controller according to a preferred embodiment of the present invention includes: reading compensation data from an external memory; Generating a first checksum corresponding to the compensation data; Decoding the compensation data; Temporarily storing the decoded compensation data in a line memory in units of horizontal lines; Generating a second checksum corresponding to the temporarily stored compensation data, comparing the first checksum with the first checksum, and determining whether the data stored in the line memory fluctuates; And compensating and outputting the image data corresponding to one of the data previously stored in the line memory or the updated data according to the determination result of the comparison unit.

Wherein the decoding of the compensation data comprises decoding the compensation data read back from the external memory when the data stored in the line memory fluctuates.

The step of generating the second checksum may include encoding the compensation data stored in the line memory in a manner stored in the external memory.

Further comprising the step of storing the compensation data read from the external memory in a register after reading the compensation data from the external memory, wherein when the data stored in the line memory fluctuates, the compensation data stored in the register is decoded again The method comprising the steps of:

The timing controller according to the preferred embodiment of the present invention generates a first checksum code when the compensation data stored in the EEPROM is READ, decodes the compensation data encoded for each vertical blank interval of each frame again, It is possible to compensate the image data through the error power data by operating the compensation data from the EEPROM upon receiving the compensation data. It is effective.

1 is a block diagram showing a basic configuration of a conventional liquid crystal display device.
2 is a diagram showing a configuration of a liquid crystal display device including a timing controller of the present invention.
3 is a diagram showing a structure of a timing controller for a liquid crystal display according to an embodiment of the present invention.
FIG. 4A is a diagram illustrating a structure of an image data modulator of a timing controller according to a first embodiment of the present invention, and FIG. 4B is a diagram illustrating a method of driving the timing controller of FIG. 4A.
FIG. 5A is a diagram illustrating a structure of an image data modulator of a timing controller according to a second embodiment of the present invention, and FIG. 5B is a diagram illustrating a method of driving the timing controller of FIG. 5A.

Hereinafter, a timing controller for a liquid crystal display according to a preferred embodiment of the present invention and a driving method thereof will be described with reference to the drawings.

2 is a diagram showing a configuration of a liquid crystal display device including a timing controller of the present invention.

As shown in the figure, the liquid crystal display device of the present invention includes a liquid crystal panel 100 for displaying an image and a driving circuit portion 200 for driving the liquid crystal panel 100.

In the liquid crystal panel 100, a plurality of data lines (DL1 to DLm, m is a natural number) and a plurality of gate lines (GL1 to GLn, n are natural numbers) are crossed in a matrix form on a substrate using a glass, And a thin film transistor T and a liquid crystal LC are formed in each pixel region to display a screen.

The driving circuit unit 200 includes a timing controller 220 connected to an external system through an interface 210, an EEPROM 230, a gate driving unit 250, and a data driving unit 260.

The interface 210 serves to provide a video related signal and various timing control signals output from an external system (not shown) to the timing controller 220 at a high speed without any error. The interface 210 provides a low voltage differential signal (LVDS) Transistor-Transistor Logic) interface method is used. The interface 210 may be configured to be embedded in the timing controller 220 as a single chip.

The timing controller 220 includes image data RGB Data and a clock signal DCLK, a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, and a data enable signal, which are mounted on another PCB substrate and input through the interface 210, And a signal DE to generate control signals for the gate driver 250 and the data driver 260, which will be described later.

Here, the horizontal synchronization signal Hsync represents the time taken to display one line of the screen, and the vertical synchronization signal Vsync represents the time taken to display the screen of one frame. The data enable signal DE indicates a period of supplying the image data actually converted to the pixel defined in the liquid crystal panel 100.

The timing controller 220 generates a control signal for driving the gate driver 250 and the data driver 260, which are composed of a plurality of integrated circuits, in synchronization with the input timing control signal, The gate control signal GCS of the gate driving unit 250 may be a gate start pulse GST, a gate shift clock GSC, a gate output enable signal GOE Enable).

The timing controller 220 generates a control signal DCS of the data driver 260. The data control signal DCS includes a source start pulse SSP and a source shift clock SSC ) And a source output enable (SOE).

The timing controller 220 according to the embodiment of the present invention compensates the image data (RGB DATA) input through the interface 210 and supplies the image data to the data driver 260. Here, the timing controller 220 receives the compensation data DVS from the EEPROM 230, which is an external memory storing the encoded digital gamma data, for inputting the image data (RGB DATA) And outputs the compensated image data (RGB DATA ') corresponding thereto.

The DGA compensates the input image data based on a plurality of variables according to a predetermined compensation algorithm. The DGA compensates at least one of the characteristics related to the image quality such as the color temperature characteristics, the gamma characteristics, and the response characteristics of the liquid crystal of the liquid crystal panel 100 The image data is modulated.

As an example, if a value of 0 is assigned to gray 1 (gray 1), 4 is assigned to gray 2 (gray 2), 8 is assigned to gray 3 (gray 3), and a value of 11 is assigned to gray 4 (gray 4) 4 is assigned to address 1, address 4 is assigned to address 2, and address 3 is assigned to address 3 (address 3) in EEPROM 230. [ In order to reduce the memory capacity, instead of storing all the data for all the gradations, only the values according to the difference values are stored, and only the difference value is provided to the timing controller 220 to reproduce the original gradation values through decoding. And performs compensation for the data.

Accordingly, unlike the conventional method in which the size is required to be 2048 X 3 bytes by encoding, only the difference value between each gradation can be stored and the data size thereof can be reduced. Here, the timing controller 220 temporarily stores the horizontal line compensation data in the line memory to compensate the image data. The data stored in the line memory may be deleted or changed in accordance with the change in the external environment.

In order to solve such a problem, the timing controller 220 of the present invention generates checksums for each of the lines before and after data is stored in the line memories, and generates image data (RGB DATA) through the stored data in the line memories Compensated, or re-transmitted to perform the compensating step.

A more specific configuration of the timing controller 220 for performing this compensation process will be described later.

A gate driver 250 including a plurality of shift registers is provided at one end of the liquid crystal panel 100 and is electrically connected to the gate lines GL1 to GLn formed on the liquid crystal panel 100, And sequentially outputs a gate driving signal.

The gate driver 250 turns on the thin film transistor T arranged on the liquid crystal panel 100 in response to the gate control signal GCS input from the timing controller 220 So that the data voltage of the analog waveform supplied from the data driver 260 is applied to the pixels connected to the thin film transistors T. [

In this case, among the gate control signals input to the gate driver 250, a gate start pulse (GSP) is a signal to be applied to a shift register for generating a first gate pulse to control the shift register to generate a first gate pulse, The gate shift clock GSC is a clock signal commonly input to all the shift registers, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE is a signal that controls the output of the shift registers.

The data driver 260 arranges the digital video signals RGB corresponding to the data control signals input from the timing controller 260 and selects the reference voltages gamma to be converted into an analog data voltage do. The data voltages are latched by one horizontal line and input to the liquid crystal panel 100 simultaneously through all the data lines DL1 to DLm.

A source start pulse SSP is a signal for controlling a data sampling start timing of the data driver 260 and a source sampling clock SSC is a rising or falling edge of a data control signal input to the data driver 260. [ And is a clock signal for controlling sampling timing of data in each driving IC constituting the data driver 260 in response thereto. The polarity control signal POL is a signal for controlling the horizontal polarity inversion timing of the data voltages simultaneously output from the respective driving ICs and the source output enable signal SOE controls the output timing of the data driver 260 .

According to the above-described structure, the liquid crystal display device provided with the timing controller of the present invention can secure a driving stability even in a change of the external environment, and can realize a high-quality image. Hereinafter, the structure of a timing controller according to an embodiment of the present invention will be described in detail with reference to the drawings.

3 is a diagram showing a structure of a timing controller for a liquid crystal display according to an embodiment of the present invention.

As shown in the figure, the timing controller 220 of the present invention includes a control signal generating unit 221 for generating a control signal for controlling the driving unit and an image data modulating unit 225 for modulating image data.

The control signal generating unit 221 receives the timing signals such as the vertical and horizontal synchronizing signals Vsync and Hsync, the data enable signal DE and the clock signal DCLK and outputs the timing signals to the gate driving unit 250 and the data driving unit 260, (DCS, GCS) for controlling the operation timing of the control signal.

The image data modulator 225 receives and modulates the image data (RGB DATA) and supplies the compensated image data (RGB DATA ') to the data driver 260. In particular, the timing controller 220 is connected to an EEPROM (230 in FIG. 2) which is a nonvolatile memory in which data allocated to each gradation of input digital video data RGB is stored to improve color temperature, gamma, And receive compensation data (DVS).

Here, the above-described video data modulating unit may or may not have a register as a temporary storage unit of the compensation data depending on the type of the timing controller. Hereinafter, the register according to the first embodiment of the present invention will be described with reference to the drawings. The structure of the image data modulating section of the timing controller for a liquid crystal display device will be described.

FIG. 4A is a diagram illustrating a structure of an image data modulator of a timing controller according to a first embodiment of the present invention, and FIG. 4B is a diagram illustrating a method of driving the timing controller of FIG. 4A.

4A, the image data modulating unit 225 of the timing controller of the present invention includes an I2C master 2251, a register 2252, a checksum generating unit 2253, a decoding unit 2254 A line memory 2255, a data compensating unit 2256, a comparing unit 2257 and a vertical blanking detecting unit 2258.

The I2C master 2251 is connected to the EEPROM 210, which is an external memory, through the I2C scheme and receives the compensation data DVS decoded and stored in the EEPROM 310 and stores the compensated data DVS in the register 2254. To this end, the I2C master 2251 outputs a clock signal for synchronization through the SCL, and reads the compensation data DVS stored in the EEPROM 210 via the SDA. In the embodiment of the present invention, the I2C data transmission scheme is applied, but it may be replaced with another data transmission scheme.

The register 2252 serves to store the compensation data DVS read by the I2C master 2251. The compensation data DVS stored in the register 2252 is used for compensation of image data (RGB DATA) through a checksum generation and decoding process. When an error occurs in the data stored in the line memory 2255 described later, The data stored in the register 2252 can be used for restoration without reloading through the master 2251. [ Here, the compensation data DVS read by the I2C master 2251 is about 384 bytes X 3, and therefore the register 2252 has at least a larger storage capacity.

The checksum generator 2253 generates a checksum for detecting an error of data stored in the line memory 2255 and comprises a first checksum 2253a and a second checksum 2253b generating block . First, when the compensation data DVS is stored in the register 2252, a first checksum 1 is generated through the first checksum block 2253a based on the compensation data DVS, (DVS ') prior to the compensation step in the compensation of the image data (RGB DATA) using the decoded compensation data DVS' stored in the second compensation data DVS ' Generates a checksum (checksum2).

The decoding unit 2254 decodes the compensation data DVS stored in the register 2252 with the first checksum 1 and stores the decoded data in the line memory 2255 in a form applicable to the video data RGB DATA do.

The line memory 2255 temporarily stores the compensation data DVS 'decoded by the decoding unit 2254 for each horizontal line. Accordingly, the data stored in the line memory 2255 has a size of 10 bits for each of R, G, and B. The line memory 2255 may be an SDRAM (Synchronous Dynamic Random Access Memory).

The data compensating unit 2256 reads the decoded compensated data DVS 'stored in the line memory 2255 and outputs color temperature deviation characteristics, gamma characteristics, and the like of the liquid crystal to the image data RGB DATA input to the timing controller. Response characteristics, and the like related to the image quality.

Before the compensation of the image data of the data compensator 2256 is performed, the above-described checksum generator 2253 outputs the decoded compensation data DVS 'read from the line memory 2255 to the EEPROM 210 Re-encodes it in the same form as the data to generate the original compensation data DVS and generates a second checksum through the second checksum block 2253b. Thereafter, the data compensating unit 2256 compensates using the compensation data previously stored in the line memory 2255, or updates the line memory 2255 from the line memory 2255 according to the data change discriminated by the comparing unit 2257 And then outputs the compensated image data RGB DATA 'by reading the compensated data DVS' again.

The comparing unit 2257 reads and compares the first and second checksums generated from the first checksum block 2253a and the second checksum block 2253b with checksum2 and checksum2, And detects an error of the compensation data DVS '. Accordingly, when no error is detected, the data compensating unit 2256 outputs compensated image data (RGB DATA ') corresponding to the compensation data DVS' currently read. At the time of error detection, the decoding unit 2254 decodes the compensation data DVS stored in the register 2252 again to update the data in the line memory 2255. At this time, the comparison time of the first and second checksums (checksum1 and checksum2) is the start time of the frame change, which corresponds to the vertical blank interval between the frames. Therefore, it is determined by a later-described vertical blank sensing unit 2258 that senses the vertical blanking.

The vertical blank sensing unit 2258 senses a frame change point according to one of the timing control signals input to the timing controller, and informs the comparator 2257 of the frame change point. The timing control signal used at this time is preferably the vertical synchronization signal Vsync.

According to the above structure, the image data modulator of the timing controller of the present invention temporally stores the compensation data (DVS) read from the EEPROM in the line memory, compensates the image data corresponding to the stored data, And the data stored in the line memory is updated by using the data of the register mounted when the error occurs, so that the data can be normally operated even if the data of the line memory is changed.

Hereinafter, a driving method of the timing controller will be described with reference to the drawings.

Referring to FIG. 4B, a method of driving a timing controller according to a first embodiment of the present invention includes a data read step S400, a data storage step S410, a first checksum generation step S420, And a storage step S430, a data read READ and a second checksum generation step S440, a checksum comparison step S450 and a data compensation and output step S460.

First, the data reading step (S400) is a step of reading the compensation data (DVS) stored in the EEPROM by the I2C master. At this time, the compensation data (DVS) stored in the EEPROM is encoded and its data size is 384 bytes X 3 than the original data.

 The data storage step (S410) is a step of storing the compensation data (DVS) loaded by the I2C master in a register. At this time, since the compensation data (DVS) has a size of 384 bytes X 3 as described above, the register has at least a larger storage capacity.

The first checksum generating step S420 is a step in which the checksum generating unit generates the first checksum for the compensation data DVS stored in the register.

In the data decoding and storing step S430, the compensation data DVS stored in the register is data reflecting only the difference value of the original data, and the decoding unit decodes and restores the original data again, and the line memory stores the decoded compensation data DVS ' ) Is temporarily stored.

The data read and second checksum generation step S440 is a step of reading the decoded compensation data DVS 'stored in the line memory by the data compensation unit and generating a second checksum 2 through the checksum generation unit .

The checksum comparison step S450 compares the first and second checksums (checksum1, checksum2) generated in steps S420 and S440, and determines whether the data stored in the line memory is changed. If the first checksum and the second checksum are the same, it is determined that there is no data fluctuation. In the next step S460, if the first checksum and the second checksum are different from each other, In step S430, the decoding unit re-reads and decodes the compensation data DVS stored in the register.

The above step S450 may be performed at the start of each frame of the image, and may further include a step of determining a frame start time by the vertical blank sensing unit.

The data compensation and output step S460 compensates the input image data RGB DATA. In this step, the data compensating unit corrects the color temperature deviation characteristic, the gamma characteristic, the response characteristic of the liquid crystal, and the like relating to the image quality, such as the color temperature deviation characteristic, the gamma characteristic, and the liquid crystal response characteristic with respect to the image data (RGB DATA) through the decoded compensation data stored in the line memory or the updated compensation data DVS ' And compensated image data (RGB DATA ') are output.

Hereinafter, a timing controller for a liquid crystal display according to a second embodiment of the present invention, which is not provided with a separate register in the timing controller, will be described with reference to the drawings.

FIG. 5A is a diagram illustrating a structure of an image data modulator of a timing controller according to a second embodiment of the present invention, and FIG. 5B is a diagram illustrating a method of driving the timing controller of FIG. 5A.

5A, the image data modulating section 325 of the timing controller of the present invention includes an I2C master 3251, a checksum generating section 3253, a decoding section 3254, a line memory 3255, a data compensating unit 3256, a comparing unit 3257, and a vertical blanking detecting unit 3258.

The I2C master 3251 is connected to the EEPROM 310 through the I2C scheme and receives the compensation data DVS decoded and stored in the EEPROM 310 and stores the compensation data DVS in the register 3254. [

The checksum generator 3253 generates a checksum for detecting an error of data stored in the line memory 3255 to be described later. The checksum generator 3253 generates a checksum for the first checksum 3253a and the second checksum 3253b, Lt; / RTI > First, when the compensation data DVS is loaded by the I2C master 3251, a first checksum 1 is generated through the first checksum block 3253a based on the compensation data DVS, (RGB DATA) using the decoded compensated data DVS 'stored in the second checksum generating block 3253b, re-encodes the decoded compensated data DVS' before the compensating step and transmits the decoded compensated data DVS 'through the second checksum generating block 3253b And generates a second checksum (checksum2).

When the compensation data DVS is loaded by the I2C master 3251, the decoding unit 3254 decodes the image data into a form applicable to the image data (RGB DATA) and stores the decoded image data in the line memory 3255.

The line memory 3255 serves to temporarily store the compensation data DVS 'decoded by the decoding unit 3254 for each horizontal line.

The data compensating unit 3256 reads the decoded compensated data DVS 'stored in the line memory 3255 and outputs color temperature deviation characteristics, gamma characteristics, and the like of the image data RGB DATA input to the timing controller Response characteristics, and the like related to the image quality.

The data compensating unit 3256 compensates the image data immediately according to whether the data discriminated by the comparison unit 3257 described later is changed or the compensated data DVS ' READ) and outputs the compensated image data (RGB DATA ').

The comparator 3257 reads and compares the first and second checksums generated from the first checksum block 3253a and the second checksum block 3253b with checksum1 and checksum2, And detects an error of the compensation data DVS '. Accordingly, when no error is detected, the data compensating unit 3256 outputs the compensated image data (RGB DATA ') corresponding to the compensation data DVS' currently read, and when the error is detected, the I2C master The decoder 3251 reloads the compensation data DVS from the EEPROM 310 and decodes the compensation data DVS to update the data in the line memory 3255. [ At this time, the comparison time of the first and second checksums (checksum1, checksum2) is the start time of the frame change, which is determined by the later-described vertical blank detection unit 3258.

The vertical blank sensing unit 3258 senses a frame change point according to any one of the timing control signals input to the timing controller, and informs the comparator 3257 of the frame change point. The vertical synchronization signal Vsync used at this time can be used.

According to the above structure, the image data modulator of the timing controller of the present invention temporally stores the compensation data (DVS) read from the EEPROM in the line memory, compensates the image data corresponding to the stored data, And the data in the line memory is updated by reading the data from the EEPROM again in the event of an error so that the data can be normally operated even if the data in the line memory is changed.

Hereinafter, a driving method of the timing controller will be described with reference to the drawings.

Referring to FIG. 5B, a method of driving a timing controller according to a second embodiment of the present invention includes a data reading step S500, a first checksum generating step S510, a data decoding and storing step S520, A second checksum generation step S530, a checksum comparison step S540, and a data compensation and output step S550.

First, the data reading step (S500) is a step of reading the compensation data (DVS) stored in the EEPROM by the I2C master.

The first checksum generation step S510 is a step for generating a checksum 1 for the checksum generator for the loaded compensation data DVS.

In the data decoding and storage step (S520), the loaded compensation data DVS is data reflecting only the difference value of the original data, and the decoding unit decodes the restored original data and restores the original compensation data DVS ' As shown in FIG.

The data read and second checksum generation step S530 is a step of reading the decoded compensation data DVS 'stored in the line memory by the data compensation unit and also generating a second checksum 2 through the checksum generation unit .

The checksum comparison step S540 compares the first and second checksums (checksum1, checksum2) generated in steps S510 and S530, and determines whether the data stored in the line memory is varied. If the first checksum and the second checksum are identical to each other, it is determined that there is no data fluctuation. In the next step S550, if the first checksum and the second checksum are different from each other, The I2C master again reads the compensation data DVS stored in the EEPROM and decodes the data loaded by the decoding unit.

Here, the step S540 may be performed at the start of each frame of the image. For this purpose, a step of determining a start time of a frame by the vertical blank sensing unit may be further included.

The data compensation and output step S550 compensates the input image data RGB DATA. In this step, the data compensating unit corrects the color temperature deviation characteristic, the gamma characteristic, the response characteristic of the liquid crystal, and the like relating to the image quality, such as the color temperature deviation characteristic, the gamma characteristic, and the liquid crystal response characteristic with respect to the image data (RGB DATA) through the decoded compensation data stored in the line memory or the updated compensation data DVS ' And compensated image data (RGB DATA ') are output.

While a number of embodiments have been described in detail above, it should be construed as being illustrative of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

100: liquid crystal panel 200:
210: Interface 220: Timing controller
230: EEPROM 250: Gate driver
260: Data driver T: Thin film transistor
LC: liquid crystal cells GL1 to GLn: gate line
DL1 to DLm: data line RGB DATA: image data
RGB DATA ': Compensated image data GCS: Gate control signal
DCS: Data control signal DVS: Compensation data
DE, Hsync, Vsync, DCLK: Timing control signal

Claims (11)

A control signal generator for receiving a timing control signal from an external system and generating a control signal of the liquid crystal display driver; And
Reads the ecoding compensated data stored in the external memory,
Decoding the encoded compensation data to generate decoded compensation data,
Temporarily storing the decoded compensated data to compensate the image data on a line-by-line basis,
A checksum for the encoded compensation data and a checksum for the re-encoded compensation data generated by re-encoding the decoded compensation data to determine whether the decoded compensation data temporarily stored is erroneous,
An image data modulating part for compensating the image data through updated compensation data when an error occurs,
And a timing controller for the liquid crystal display device. The method according to claim 1,
The image data modulating unit,
An I2C master for reading the encoded compensation data from an external memory;
A checksum generator for generating a first checksum corresponding to the encoded compensation data;
A decoding unit decoding the encoded compensation data;
A line memory for temporarily storing the decoded compensation data in units of horizontal lines;
Encoding the compensated data stored in the line memory to generate a second checksum corresponding to the re-encoded compensation data generated by re-encoding the decoded compensated data stored in the line memory, and comparing the decoded compensated data stored in the line memory with the first checksum A comparing unit for determining whether the image is changed; And
And a data compensator for compensating and outputting the video data corresponding to any one of the decoded compensated data previously stored in the line memory or the updated compensated data,
And a timing controller for the liquid crystal display device. 3. The method of claim 2,
Wherein the re-encoded compensation data for the second checksum is data obtained by encoding the decoded compensation data stored in the line memory in a manner stored in the external memory. 3. The method of claim 2,
And the decoding unit decodes the encoded compensation data read by the I2C master again when the data stored in the line memory fluctuates. 3. The method of claim 2,
The image data modulating unit,
A register for storing the encoded compensation data read by the I2C master,
And a timing controller for controlling the timing controller. 6. The method of claim 5,
Wherein the decoding unit decodes the encoded compensation data stored in the register again when the decoded compensation data stored in the line memory fluctuates. 3. The method of claim 2,
A vertical blank sensing unit for synchronizing the timing control signal with the timing control signal,
And a timing controller for controlling the timing controller. Reading compensation data encoded from an external memory;
Generating a first checksum corresponding to the encoded compensation data;
Decoding the encoded compensation data to generate decoded compensation data;
Temporarily storing the decoded compensation data in a line memory in units of horizontal lines;
Encoding the compensated data to generate re-encoded compensated data, generating a second checksum corresponding to the re-encoded compensated data, comparing the decoded compensated data with the first checksum, and decoding the decoded compensated data stored in the line memory Determining whether the compensation data has changed; And
Compensating and outputting the image data corresponding to any one of the decoded compensated data previously stored in the line memory or the compensated data updated in accordance with the determination result of the comparator
And a timing controller for driving the timing controller. 9. The method of claim 8,
Wherein the decoding of the encoded compensation data comprises:
And decodes the encoded compensation data read from the external memory again when the decoded compensation data stored in the line memory fluctuates. 9. The method of claim 8,
Wherein generating the second checksum comprises:
And encoding the decoded compensation data stored in the line memory in a manner stored in the external memory to generate the re-encoded compensation data. 9. The method of claim 8,
After the step of reading the encoded compensation data from the external memory,
Further comprising storing the encoded compensation data in a register, the encoded compensation data being read from the external memory,
Decode the encoded compensation data stored in the register, upon re-encoding of the encoded compensation data stored in the line memory
And a driving method of the timing controller for a liquid crystal display device.

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