KR101874054B1 - Semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

A semiconductor memory device includes a first selection transistor connected in series to a shared bit line and connected in series, the channel region being of an incremental type having a first conductivity type and having a threshold voltage higher than the first reference voltage, A first cell string including a second selection transistor having a threshold voltage lower than a second reference voltage, cell transistors, and a ground selection transistor; and a second cell string connected in common to the common bit line and serially connected in series, A fourth selection transistor having a threshold voltage higher than the second reference voltage by an electric operation, a fourth selection transistor formed of a depletion type having a two-conductivity type and having a threshold voltage lower than the first reference voltage, And a second cell string including a ground selection transistor. The selection transistors included in the semiconductor memory device are easy to control the threshold voltage.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device,

The present invention relates to a semiconductor memory device and a manufacturing method thereof. More particularly, the present invention relates to a highly integrated NAND flash memory device and a method of manufacturing the same.

Among semiconductor memory devices, NAND flash memory devices can store large amounts of data and are used as main memories of various electronic devices. The NAND flash memory devices are highly integrated and variously researched to store a large number of data.

It is an object of the present invention to provide a semiconductor memory device having excellent operation characteristics and highly integrated.

It is another object of the present invention to provide a method of manufacturing the semiconductor memory device.

According to an aspect of the present invention, a semiconductor memory device includes a shared bit line. A first selection transistor connected in series to the common bit line and connected in series, the channel region being of an increasing type having a first conductivity type and having a threshold voltage higher than the first reference voltage, A first cell string including a second selection transistor having a lower threshold voltage, cell transistors, and a ground selection transistor is provided. A third selection transistor connected in common to the shared bit line and serially connected in series, the channel region being of a depletion type having a second conductivity type and having a threshold voltage lower than the first reference voltage, And a second cell string including a fourth selection transistor having a threshold voltage higher than the second reference voltage, cell transistors, and a ground selection transistor. Further, a common source line commonly connected to the ends of the ground selection transistors included in the first and second cell strings is provided.

In an embodiment of the present invention, the channel regions of the second and fourth selection transistors may have the same conductivity type. The second and fourth selection transistors may be an enhancement type transistor having a channel region of the first conductivity type or a depletion type transistor having a channel region of the second conductivity type.

In an embodiment of the present invention, the channel regions of the second and fourth selection transistors may have opposite conductivity types. The second select transistor may be a depletion transistor having a channel region of a second conductivity type or an enhancement transistor having a channel region of a first conductivity type.

In an embodiment of the present invention, the second and fourth selection transistors may have the same stacking structure as the cell transistors.

In an embodiment of the present invention, the second selection transistor may be in an erased state, and the fourth selection transistor may be in a programmed state.

In an embodiment of the present invention, the second selection transistor has a threshold voltage in an initial state, and the fourth selection transistor may be in a programmed state.

In an embodiment of the present invention, the second and fourth selection transistors may include a plurality of transistors connected in series.

In one embodiment of the present invention, at least one region of the region between the shared bit line and the selection transistor adjacent to the shared bit line and the selection transistor adjacent to the cell transistor and the cell transistor, Selection transistors can be connected in series.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor memory device, the method comprising: forming a channel region of an increase type having a first conductivity type on a substrate, And a second selection transistor having a threshold voltage lower than the second reference voltage by electric operation, cell transistors, and a ground selection transistor. A third selection transistor having a channel region on the substrate of a depletion type having a second conductivity type and having a threshold voltage lower than the first reference voltage, a third selection transistor having a threshold voltage higher than the second reference voltage by an electrical operation, 4 selection transistors, cell transistors, and ground selection transistors. And a common source line commonly connected to the ends of the ground selection transistors included in the first and second cell strings is formed. In addition, shared bit lines commonly connected to the ends of the first and third cell selection transistors included in the first and second cell strings are formed.

In one embodiment of the present invention, a process of adjusting the threshold voltages of the second and fourth selection transistors by an electrical operation in the process of forming the first and second cell strings is included. In order to adjust the threshold voltage, the second and fourth selection transistors are erased. Next, the fourth selection transistor is selectively programmed.

In the step of selectively programming the fourth selection transistor, a programming disturb voltage may be applied to the shared bit line such that the threshold voltage is no longer raised when the fourth selection transistor reaches a desired threshold voltage.

In an embodiment of the present invention, the gates of the second and fourth selection transistors and the cell selection transistor have the same stacked structure, and may be formed to stack the tunnel insulating film, the charge storage film pattern, the blocking dielectric film, and the control gate electrode .

The charge storage film pattern at the gates of the second and fourth selection transistors and the cell selection transistor may be formed as a floating gate electrode or a charge trap film pattern.

In an embodiment of the present invention, in order to form the third selection transistor, an impurity of the second conductivity type may selectively be doped under the substrate surface corresponding to the channel region of the third selection transistor.

In one embodiment of the present invention, the dopant concentration in the channel region of the first and third selection transistors is higher than the dopant concentration in the channel region of the second and fourth selection transistors.

In one embodiment of the present invention, the second and fourth selection transistors are formed so as to have a plurality of transistors connected in series, and when performing the operation of erasing the second and fourth selection transistors, Among the transistors included in the fourth selection transistor, a positive voltage lower than the erase voltage may be applied to the gate line of the transistor adjacent to the first and third selection transistors, and a ground voltage may be applied to the gate line of the remaining transistors .

In the cell string of the semiconductor memory device according to the present invention, one of the selection transistors is a threshold voltage controlled by an electrical operation. Therefore, it is possible to suppress the defective threshold voltage dispersion caused by the diffusion of impurities in the channel region. Therefore, the semiconductor memory device according to the present invention can reduce the program disturb defect.

1 is a block diagram showing the overall configuration of a NAND flash memory device according to embodiments of the present invention.
2A is a circuit diagram of a cell array of a NAND flash memory device according to the first embodiment of the present invention.
2B is a circuit diagram of a modified form of the cell array of the NAND flash memory device according to the first embodiment of the present invention.
3A to 3C are circuit diagrams for explaining a method of adjusting a threshold voltage of a selection transistor.
4 is a plan view of an example of a cell array of the NAND flash memory device shown in FIG. 2B.
5 is a cross-sectional view showing an example of a cell array of the NAND flash memory device shown in FIG. 2B.
6A and 6B are plan views illustrating a method of manufacturing the NAND flash memory device shown in FIG.
FIGS. 7A through 7C are cross-sectional views illustrating another method of manufacturing the NAND flash memory device shown in FIGS. 4 and 5. FIG.
8 is a plan view of another example of a cell array of the NAND flash memory device shown in FIG. 2B.
9 is a cross-sectional view showing a cell array of the NAND flash memory device shown in FIG.
FIG. 10 is a plan view for explaining a method of manufacturing the NAND flash memory device shown in FIGS. 8 and 9. FIG.
11 is a cross-sectional view of another example showing a cell array of the NAND flash memory device shown in FIG. 2B.
12 is a circuit diagram of a cell array of a NAND flash memory device according to a second embodiment of the present invention.
13 is a cross-sectional view of the cell array shown in Fig.
14A and 14B are circuit diagrams for explaining a threshold voltage adjusting operation of a transistor included in the NAND flash memory device shown in FIG.
15 is a circuit diagram of a NAND flash memory device according to a third embodiment of the present invention.
16 is a circuit diagram for explaining a threshold voltage adjusting operation of a transistor included in the NAND flash memory device shown in FIG.
17 is a cross-sectional view showing a cell array of the NAND flash memory device shown in FIG.
18 is a cross-sectional view of another laminated structure showing a cell array of the NAND flash memory device shown in FIG.
19 is a circuit diagram of a cell array of a NAND flash memory device according to a fourth embodiment of the present invention.
20 is a cross-sectional view of a cell array of a NAND flash memory device according to a fourth embodiment of the present invention.
21 is a circuit diagram of a cell array of a NAND flash memory device according to a fifth embodiment of the present invention.
22 is a cross-sectional view of a cell array of a NAND flash memory device according to a fifth embodiment of the present invention.
23 is a circuit diagram of a cell array of the NAND flash memory device according to the sixth embodiment of the present invention.
24 is a cross-sectional view of a cell array of a NAND flash memory device according to a sixth embodiment of the present invention.
25 is a schematic diagram of a memory card according to an embodiment of the present invention.
26 is a block diagram of an electronic system according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the drawings of the present invention, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

In the present invention, the terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In the present invention, it is to be understood that each layer (film), region, electrode, pattern or structure may be formed on, over, or under the object, substrate, layer, Means that each layer (film), region, electrode, pattern or structure is directly formed or positioned below a substrate, each layer (film), region, or pattern, , Other regions, other electrodes, other patterns, or other structures may additionally be formed on the object or substrate.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, But should not be construed as limited to the embodiments set forth in the claims.

That is, the present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the following description. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Example 1

1 is a block diagram showing the overall configuration of a NAND flash memory device according to embodiments of the present invention. 2A is a circuit diagram of a cell array of a NAND flash memory device according to the first embodiment of the present invention.

Referring to FIG. 1, a NAND flash memory device includes a memory cell array 10, a page buffer circuit 12, a data input / output circuit 14, a row decoder 16, and a control circuit 18, and the like.

2A, the memory cell array 10 includes a first cell string 102a and a second cell string 102b adjacent to the first cell string 102a, and a second cell string 102b adjacent to the first cell string 102a. A shared bit line B / L commonly connected to one end of the first and second cell strings 102a and 102b and a common source line CSL connected to the other ends of the first and second cell strings 102a and 102b do. The shared bit line B / L may extend in a first direction. In the memory cell array 10, unit cell strings in which two cell strings 102a and 102b are connected to one shared bit line B / L are repeatedly arranged.

Specifically, the first cell string 102a has a configuration in which a first selection transistor 104a, a second selection transistor 106a, cell transistors 108, and a ground selection transistor 110 are sequentially connected in series.

The second cell string 102b has a configuration in which a third selection transistor 104b, a fourth selection transistor 106b, cell transistors 108, and a ground selection transistor 110 are sequentially connected in series.

The impurity regions of the ground selection transistors 110 included in the first and second cell strings 102a and 102b are connected to a common source line CSL.

The transistors included in the first and second cell strings 102a and 102b and the gates of the ground selection transistors 110 are connected to each other in a second direction perpendicular to the first direction. That is, the gates of the first and third selection transistors 104a and 104b are provided in the second gate line SSL2, and the gates of the second and fourth selection transistors 106a and 106b are provided in the first gate line SSL1), and the gates of the cell transistors are provided as word lines.

Hereinafter, the second and fourth selection transistors 106a and 106b adjacent to the cell transistors 108 are referred to as a first group selection transistor, and the first and second selection transistors 106a and 106b adjacent to the shared bit line B / And the third selection transistors 104a and 104b are referred to as a second group selection transistor. The first group select transistors are provided with a first gate line SSL1 extending in the second direction to share gates. The second group select transistors are provided with a second gate line SSL2 extending in the second direction to share gates.

One shared bit line B / L connects one adjacent first and third selection transistors 104a and 104b in common.

However, the first and second cell strings 102a and 102b connected to the one shared bit line B / L must be individually cell-selected. That is, if one cell string of two cell strings 102a and 102b connected to the one shared bit line B / L is selected, the remaining cell strings should be designed not to be selected. For this purpose, the selection transistors included in the first and second cell strings 102a and 102b must have different configurations.

In this embodiment, the first group selection transistors 106a and 106b connected to the same shared bit line B / L are electrically operated by transistors whose threshold voltages are different for each string by an electrical operation, that is, programming or erasing operation / RTI > On the other hand, the second group select transistors 104a and 104b connected to the same shared bit line B / L are provided with transistors having different threshold voltages according to channel doping. That is, one of the second group select transistors 104a and 104b is provided as a depletion type MOS transistor, and the other is provided as an increase type MOS transistor.

The first select transistor 104a included in the second group select transistors 104a and 104b is an increase type MOS transistor E and the third select transistor 104b is a depletion type MOS transistor D, . The MOS transistor has a fixed threshold voltage value without changing the threshold voltage by an electrical operation.

The threshold voltage of the MOS transistor (E) is equal to or greater than a first reference voltage, and the threshold voltage of the depletion MOS transistor (D) is equal to or less than the first reference voltage. For example, the threshold voltage of the enhancement type MOS transistor (E) is 0 V or more and the threshold voltage of the depletion type MOS transistor (D) is 0 V or less. The depletion type MOS transistor D may not have the Id-Vd curve characteristic of a general transistor, but may have a characteristic of being turned on at a voltage of 0 V or less. Alternatively, the depletion type MOS transistor D may have a resistance characteristic.

The enhancement type MOS transistor (E) is a transistor whose channel region has a conductivity type different from that of the source / drain region. In one example, the channel region of the enhancement transistor is doped with a P-type impurity. The depletion type MOS transistor (D) is a transistor in which the channel region of the transistor has the same conductivity type as that of the source / drain region. For example, the channel region of the depletion type MOS transistor (D) is doped with an N-type impurity.

Since the first and third selection transistors 104a and 104b are provided as the increase type MOS transistor E and the depletion type MOS transistor D respectively as described above, When a voltage equal to or higher than the voltage is applied, both the first and third selection transistors 104a and 104b are turned on. On the other hand, when a voltage lower than the first reference voltage is applied to the second gate line SSL2, only the third selection transistor 104b, which is a depletion type transistor D, is turned on, The transistor 104a is turned off.

Meanwhile, the second and fourth selection transistors 106a and 106b, which are the first group selection transistors, are doped with the same conductivity type in the channel region. In the present embodiment, the second and fourth selection transistors 106a and 106b are all provided as an increase-type cell type transistor. In the cell type transistor of the enhancement type, the channel region of the transistor has a conductivity type different from that of the source / drain region. For example, the channel region of the enhancement type cell-type transistor may be doped with a P-type impurity. The cell type transistor has a structure in which a gate insulating film, a charge storage film pattern, and a gate electrode are stacked like a cell transistor. Therefore, the threshold voltage can be adjusted according to the charge stored in the charge storage film pattern.

In order to select one of the two strings 102a and 102b connected to the shared bit line B / L, two select transistors having different threshold voltages must be connected in series to one string. In addition, each select transistor sharing a gate line in two strings 102a 102b sharing the bit line B / L must have a different threshold voltage.

Specifically, since the first selection transistor 104a is an incremental MOS transistor E, the second selection transistor 106a connected in series to the first selection transistor 104a must be electrically depleted. Therefore, the second selection transistor 106a maintains the erased state, and has a lower threshold voltage than the second reference voltage. Preferably, the second selection transistor 106a has a threshold voltage of 0 V or less. Therefore, the second selection transistor 106a is physically an increasing transistor, but is electrically operated as a depletion type transistor having a low threshold voltage of 0V or less.

On the other hand, since the third selection transistor 104b is the depletion type MOS transistor D, the fourth selection transistor 106b connected in series to the third selection transistor 104b must be electrically provided as an increasing transistor. Therefore, the fourth selection transistor maintains the programmed state, and has a threshold voltage higher than the second reference voltage. The second reference voltage is a voltage of 0V or more. Therefore, the fourth selection transistor 106b is operated as an electrically increasing transistor.

When the voltage equal to or higher than the second reference voltage is applied to the first gate line SSL1, the second and fourth selection transistors 106a and 106b are all turned on. On the other hand, when a voltage lower than the second reference voltage is applied to the first gate line SSL1, only the fourth selection transistor 106b, which is an electrically depletion type transistor, is selectively turned on.

The ground selection transistor 110 is formed of an incremental MOS transistor.

The first to fourth selection transistors 104a, 106a, 104b, and 106b included in the first and second cell strings 102a and 102b sharing the bit line are configured as described above, One of the two cell strings 102a and 102b may be turned on.

In the first and second cell strings 102a and 102b sharing the bit line B / L, the channel region of the three selection transistors among the first to fourth selection transistors 104a, 106a, 104b, and 106b, Have the same conductivity type.

Therefore, the impurity implantation process for forming the first to fourth selection transistors 104a, 106a, 104b, and 106b is simplified. In addition, it is possible to suppress the occurrence of misalignment during the ion implantation process, thereby preventing problems such as mixing of ions of different conductivity types. Therefore, it is possible to suppress the malfunction of the NAND flash memory device caused by the defective ion implantation process. Also, since the first group selection transistors adjust the threshold voltage of the selection transistor by an electrical method, the selection transistors can be easily adjusted to a desired threshold voltage.

2B is a circuit diagram of a modified form of the cell array of the NAND flash memory device according to the first embodiment of the present invention.

Referring to FIG. 2B, the memory cell array includes a first cell string 102a and a second cell string 102b in the same manner as described above, and a pair of adjacent cell strings 102a and 102b ) And common bit lines (B / L) extending in a first direction. On the opposite side of the shared bit line B / L, the first and second cell strings 102a and 102b are connected to a common source line CSL.

As shown, two first cell strings 102a and two second cell strings 102b are alternately arranged. Therefore, the first group select transistors are repeatedly arranged in the order of erase, programming (P), programming (P), erase, erase, programming (P) in the extending direction of the first gate line SSL1. The second group selection transistors are arranged in the order of increase type, depletion type, depletion type, increasing type, increasing type, and depletion type MOS transistors in the extending direction of the second gate line SSL2.

In this way, when each cell string is arranged, the two group-depletion type MOS transistors D are arranged adjacent to each other in the second group selection transistors. Therefore, the impurity doped region is widened during the ion implantation process for forming the depletion-type MOS transistors D, thus facilitating the process.

The memory cell array differs in the arrangement of cell strings, and the operation of each cell string is the same as that of the memory cell array of FIG. 2A.

Hereinafter, a method of adjusting the threshold voltages of the second and fourth selection transistors in the cell array shown in FIG. 2A will be described.

3A to 3C are circuit diagrams for explaining a method of adjusting a threshold voltage of a selection transistor.

In the case of the NAND flash memory device shown in FIG. 2A, the second selection transistor 106a must be in an erased state and the fourth selection transistor 106b must be in a programmed state. To this end, an erase operation is performed on both the second and fourth selection transistors 106a and 106b. Thereafter, only the fourth selection transistors 106b selectively perform a programming operation.

In order to perform a programming or erasing operation on the second and fourth selection transistors, separate circuits 125 for independently applying voltages to the second and fourth transistors, as shown in FIG. 3A, are further provided .

3A shows performing an erase operation on the second and fourth select transistors. For erase operation, an electrical signal is applied as shown in the following table.

When the above operation is performed, the erase operation is performed on the second and fourth selection transistors 106a and 106b and the cell transistor 108. [ In this embodiment, the erase operation is also performed on the cell transistor 108, but the cell transistor 108 may not perform erase operation.

3B shows performing a programming operation for the fourth selection transistors. For programming operation, an electrical signal is applied as shown in the following table.

When the ground voltage is applied to the second gate line SSL2 as described above, the first select transistor 104a having a threshold voltage higher than the first reference voltage is turned off. Therefore, no programming operation is performed on the second selection transistor 106a connected to the first cell string.

On the other hand, when the ground voltage is applied to the second gate line SSL2 as described above, the third selection transistor 104b having the threshold voltage lower than the first reference voltage is turned on. Therefore, a programming operation is selectively performed on the fourth selection transistor 106b connected to the second cell string 102b. Therefore, the threshold voltage of the fourth selection transistor 106b becomes higher than the second reference voltage.

On the other hand, all the plurality of fourth selection transistors 106b sharing the first gate line SSL1 must have a target threshold voltage (Target Vth) higher than the second reference voltage. However, if the programming operation is continuously performed on the fourth selection transistor 106b that has reached the target threshold voltage through the programming operation, the over-programmed fourth selection transistor 106b is set to a threshold voltage higher than the target threshold voltage It is not desirable to have. Further, the distribution of the electrical characteristics of the plurality of fourth selection transistors 106b is deteriorated. Therefore, in order for the plurality of fourth selection transistors 106b to all have the same target threshold voltage, programming operation is no longer performed for the fourth selection transistor 106b that has reached the target threshold voltage.

To do this, a threshold voltage verification operation must be performed during the programming operation to check the threshold voltages of the respective fourth selection transistors 106b. That is, after voltage pulses for the programming operation are applied, voltage pulses for threshold voltage verification must be applied.

During the threshold voltage check operation, an electrical signal is applied as shown in the following table.

Through the threshold voltage check, the programming operation is no longer performed in the fourth selection transistor 106b that has reached the set target threshold voltage.

3C shows an operation for the fourth selection transistor which has reached the target threshold voltage at the time of programming.

When the fourth selection transistor 106b of any of the fourth selection transistors 106b reaches the set target threshold voltage (left string unit), the corresponding bit line B / L, as shown in FIG. 3C, (Inhibit Voltage, Vinhibit) is applied without applying a ground voltage. The disturbance voltage Vinhibit is a voltage equal to or greater than a voltage applied to the second gate line SSL2 minus a threshold voltage of the fourth selection transistor 106b.

Therefore, the programming operation is no longer performed in the fourth selection transistor 106b that has reached the target threshold voltage. By the above operation, the fourth selection transistors 106b have a set target threshold voltage.

On the other hand, the fourth selecting transistor 106b of the right string unit which has not reached the target threshold voltage is caused to continue the programming operation.

With the above-described method, the second and fourth selection transistors 106a and 106b can be adjusted to have a desired threshold voltage.

The circuits of the cell array of the NAND flash memory device of Figs. 2A and 2B can be implemented in various forms on the substrate according to the process design. Hereinafter, an example in which the cell arrays of the NAND flash memory device shown in FIG. 2B are implemented on a substrate will be described.

4 is a plan view of an example of a cell array of the NAND flash memory device shown in FIG. 2B. 5 is a cross-sectional view showing an example of a cell array of the NAND flash memory device shown in FIG. 2B.

The present embodiment describes that the charge storage film of the cell transistors is a floating gate.

4 and 5, a device isolation film pattern 112a is provided on a semiconductor substrate, for example, a P-type silicon substrate. The device isolation film pattern 112a has a line shape extending in the first direction and an area between the device isolation film patterns 112a becomes an active area 112b.

In the active region 112b, the first channel region 114, which is a channel region of the third select transistor 104b, is doped with a low concentration n-type impurity.

In the active region 112b, the first, second and fourth select transistors 104a, 106a and 106b and the second channel region 116, which is a channel region of the ground select transistor 110, are doped with a p-type impurity have. The second channel region 116 may be doped with a p-type impurity at a higher concentration than the channel region of the cell transistors.

Although not shown, if the channel region of the third selection transistor 104b is arranged differently, the cell array of the NAND flash memory device shown in FIG. 2A can be realized. That is, in order to implement the NAND flash memory device of FIG. 2A, the channel region of the third select transistor 104b is formed so that the first and second cell strings 102a and 102b are alternately arranged.

On the substrate, a first gate structure 140 for the cell transistor, a second gate structure 142 for the second and fourth selection transistors, and a third gate structure 144 for the first and third selection transistors and the ground selection transistor Respectively.

In Figure 5, a bottom cross-sectional view shows a first cell string, and a top cross-sectional view shows a second cell string.

5, the first gate structures 140 have a stacked structure of a tunnel insulating layer 130, a floating gate electrode 132, a blocking dielectric layer pattern 134, and a control gate electrode 136 . The control gate electrode 136 is provided as a word line (W / L) and has a shape extending in a second direction perpendicular to the active region. Also, the first gate structure 140 has a first line width d1. The floating gate electrode 132 may comprise polysilicon. The blocking dielectric layer pattern 134 may have a structure in which oxides, nitrides, and oxides are stacked. As another example, the blocking dielectric layer 134 may include a metal oxide having a high dielectric constant.

The second gate structures 142 have a shape in which a tunnel insulating layer 130, a floating gate electrode 132, a blocking dielectric layer pattern 134, and a control gate electrode 136 are stacked. However, since the second gate structure must be used as a selection transistor, the second gate structure has a second line width d2 that is wider than the first line width d1. In the second gate structure, since the second selection transistors 106a are in an erased state, a positive charge is injected into the floating gate electrode 132 of the second selection transistor 106a. In addition, since the fourth selection transistors 106b are in the programmed state, a negative charge is injected into the floating gate electrode 132 included in the fourth selection transistor 106b.

Although the third gate structures 144 have a stacked structure of the tunnel insulating film 130, the floating gate electrode 132, the blocking dielectric film pattern 134a and the control gate electrode 136a, the floating gate electrode 132 And the control gate electrode 136a are connected to each other. Therefore, the floating gate electrode 132 does not function as a charge storage film. In addition, the third gate structure has to be used as a selection transistor, and thus has a second line width d2 that is wider than the first line width d1.

N-type impurity regions are formed in the active regions on both sides of the second to third gate structures 142 and 144. N-type impurity regions may also be formed in the active regions on both sides of the first gate structure 140.

An interlayer insulating film (not shown) covering the first to third gate structures 142 and 144 is provided.

And one bit line contact 138 which penetrates the interlayer insulating film and electrically connects the impurity region of the first select transistor 104a and the impurity region of the third select transistor 104b.

And a bit line (B / L, not shown) connected to the bit line contact 138 and extending in the extension direction of the active region. And a common source line (not shown) connected to the one-side impurity region of the ground selection transistor 110 is provided.

Hereinafter, a method of manufacturing the NAND flash memory device having the cell array shown in FIGS. 4 and 5 will be briefly described.

6A and 6B are plan views illustrating a method of manufacturing the NAND flash memory device shown in FIG.

Referring to FIG. 6A, a substrate low-trench isolation process is performed on a substrate to form a device isolation film pattern 112a. The substrate may be doped with a low concentration p-type impurity.

An ion implantation mask (not shown) for selectively exposing the channel region region of the third selection transistor 104b is formed in the active region 112b between the device isolation film patterns 112a. Thereafter, the exposed region is doped with a low concentration n-type impurity to form a first channel region 114.

6B, an ion implantation mask for selectively exposing the first, second, and fourth selection transistors 104a, 106a, 104b and the ground selection transistor 110 formation region in the active region 112b, . Thereafter, the exposed region is doped with a p-type impurity to form a second channel region 116.

By performing the above process, channel regions of the first to fourth selection transistors 104a, 106a, 104b, and 106b are formed. The processes described with reference to FIGS. 6A and 6B may be performed by changing the order.

Referring again to FIGS. 4 and 5, a tunnel oxide film, a floating gate electrode film, a blocking dielectric film, and a control gate electrode film are formed on the substrate. When the thin films are stacked, a process of removing the blocking dielectric film of the portion so that the floating gate electrode and the control gate electrode are in contact with each other is performed at a portion where the first and third selection transistors 104a and 104b are formed. Thereafter, the thin films are patterned. Thereby, the first gate structure 140 for the cell transistor 108, the second gate structure 142 for the second and fourth selection transistors 106a and 106b, and the first and third selection transistors 104a and 104b, And a third gate structure 144 for the ground selection transistor.

An active region on both sides of the first to third gate structures 140, 142 and 144 is doped with an N-type impurity.

An interlayer insulating film (not shown) is formed to cover the first to third gate structures 140, 142 and 144. And one bit line contact 138 electrically connecting the impurity region of the first select transistor 104a and the impurity region of the third select transistor 104b through the interlayer insulating film is formed.

(B / L, not shown) extending in the direction of extension of the active region in connection with the bit line contact 138.

And forms a common source line (not shown) connected to the one-side impurity region of the ground selection transistor 110.

By performing the above-described process, a NAND flash memory device can be formed.

Thereafter, the threshold voltage adjusting process is performed on the first group select transistors of the NAND flash memory device. That is, the second selection transistors 106a are erased, and the fourth selection transistors 106b are programmed. The method of adjusting the threshold voltage is the same as that described with reference to FIGS. 3A to 3C.

FIGS. 7A through 7C are cross-sectional views illustrating another method of manufacturing the NAND flash memory device shown in FIGS. 4 and 5. FIG.

Referring to FIG. 7A, a first ion implantation mask 146a selectively exposing the first through fourth selection transistors and the ground selection transistor formation region is formed. Thereafter, the p-type impurity 147 is doped into the exposed region.

Referring to FIG. 7B, a first gate structure 140 for the cell transistor 108, a second gate structure 142 for the second and fourth selection transistors 106a and 106b, and a second gate structure 142 for the first and third The selection transistors 104a and 104b, and the third gate structure 144 for the ground selection transistor 110, respectively.

Referring to FIG. 7C, a second ion implantation mask 146b is formed to expose a channel region of the third selection transistor 104b. Through the halo ion implantation process, only the channel region 114 of the third selection transistor 104b is doped with an N-type impurity selectively. Through the above process, the second selection transistor 106a becomes a depletion type transistor.

Thereafter, a NAND flash memory device can be manufactured by performing N-type impurity doping, an interlayer insulating film, a bit line contact, a bit line, and a common source line forming process as described above.

8 is a plan view of another example of a cell array of the NAND flash memory device shown in FIG. 2B. 9 is a cross-sectional view showing a cell array of the NAND flash memory device shown in FIG.

8 and 9, in the cell array of FIG. 4 and FIG. 9, except that the doping concentrations of the channel region 116a of the enhancement type transistor and the channel region 116b of the second group selection transistor in the first group selection transistor are different, 5 cell array.

8 and 9, in the active region of the substrate, since the third select transistor 104b is a depletion type transistor, the channel region 114 is doped with a low concentration n-type impurity. In addition, in the active region, the first, second, and fourth selection transistors and the ground selection transistor are incremental transistors, so that the channel regions 116a and 116b are doped with p-type impurities.

Among the first group selection transistors, the first selection transistor 104a provided as an increase type transistor and the channel region 116a of the ground selection transistor GSL are doped with relatively high p-type impurity. In addition, the channel region 116b of the second and fourth selection transistors 106a and 106b, which are the second group selection transistors, is doped with a relatively low concentration p-type impurity.

This is because, in the case of the second and fourth selection transistors 106a and 106b which are the second group selection transistors, the threshold voltage is not determined by the channel doping but the threshold voltage is electrically determined. Therefore, do. Therefore, the channel doping concentration of the second and fourth transistors 106a and 106b adjacent to the cell transistor is reduced, so that the junction characteristic between the cell transistor 108 and the second and fourth selection transistors 106a and 106b becomes good .

FIG. 10 is a plan view for explaining a method of manufacturing the NAND flash memory device shown in FIGS. 8 and 9. FIG.

6A, the channel region 114 of the third selection transistor is selectively doped with a low concentration n-type impurity.

Referring to FIG. 10, an ion implantation mask (not shown) for selectively exposing the first selection transistor 104a and the ground selection transistor 110 formation region is formed in the active region. Next, the p-type impurity is doped into the region 116a exposed by the ion implantation mask.

In this manner, the P-type impurity is doped only in the channel region of the first and third selection transistors, so that the channel region 116b of the second to fourth selection transistors is relatively low in the P-type Impurities.

When the above process is performed, the channel doping process of each selection transistor is completed.

Subsequently, a NAND flash memory device can be manufactured by performing gate structure formation, N-type impurity doping, interlayer insulating film, bit line contact, bit line, and common source line forming processes as described above.

11 is a cross-sectional view of another example showing a cell array of the NAND flash memory device shown in FIG. 2B.

In this embodiment, the charge storage film of the cell transistors is the charge trap film, and thus is the same as the cell array of Fig. 4 except that the stacking structure of the selection transistors is changed. Therefore, the plan view of the cell array of this embodiment is the same as that shown in Fig.

11, on the substrate, a first gate structure 140a for the cell transistor 108, a second gate structure 142a for the second and fourth selection transistors 106a and 106b, Transistors 104a and 104b and a third gate structure 144a for the ground selection transistor 110 are provided.

The first gate structures 140a have a shape in which a tunnel insulating film 150, a charge trap film pattern 152, a blocking dielectric film pattern 154, and a control gate electrode 156 are stacked. The control gate electrode 156 is provided as a word line and has a shape extending in the second direction. Also, the first gate structure 140a has a first line width. The charge trap film pattern 152 may include silicon nitride.

The second gate structures 142a have a shape in which a tunnel insulating film 150, a charge trap film pattern 152, a blocking dielectric film pattern 154, and a control gate electrode 156 are stacked. However, since the second gate structure 142a must be used as a selection transistor, the second gate structure 142a has a second line width d2 that is wider than the first line width d1. In the second gate structure 142a, a positive charge is injected into the charge trap film pattern 152 included in the second selection transistor 106a. Further, a negative charge is injected into the charge trap film pattern 152 included in the fourth selection transistor 106b.

The third gate structures 144a are formed by stacking a tunnel insulating film 150, a charge trap film pattern 152, a blocking dielectric film pattern 154 and a control gate electrode 156 in the same manner as the second gate structure 142a Shape. The charge trap film pattern 152 of the third gate structure 144a does not function to store charge. That is, in the third gate structure 144a, the tunnel insulating film 150, the charge trap film pattern 152, and the blocking dielectric film pattern 154 function as a gate oxide film. The third gate structure 144a has a second line width d2 that is wider than the first line width d1 since it must be used as a selection transistor.

The NAND flash memory device shown in FIG. 11 is the same as the flash memory device shown in FIG. 4 except for the lamination structure of the thin films included in the gate structure. Therefore, it can be manufactured in almost the same manner as the method of manufacturing the NAND flash memory device of FIG. 4, while changing the thin film to be formed to form the gate structure. However, since the first through third gate structures all have the same lamination structure, a process for partially removing the blocking dielectric film is not performed when patterning the first through third gate structures.

Example 2

12 is a circuit diagram of a cell array of a NAND flash memory device according to a second embodiment of the present invention. 13 is a cross-sectional view of the cell array shown in Fig.

The NAND flash memory device according to the second embodiment is the same as the NAND flash memory device according to the first embodiment except for the configuration of the first to fourth selection transistors.

12 and 13, any one of the second group select transistors connected to the shared bit line is provided as a depletion type MOS transistor (D), and the other is provided as an increase type MOS transistor (E). In one example, the first selection transistor 104a is provided as a depletion type MOS transistor (D), and the third selection transistor 104b is provided as an increasing type MOS transistor (E).

In addition, the second and fourth selection transistors 106a and 106b, which are the first group selection transistors, are provided with a depletion type cell type transistor D having the same conductivity type as the impurity regions provided in the channel region and the source drain do.

The second and fourth selection transistors 106a and 106b physically have the same lamination structure. However, the second and fourth selection transistors 106a and 106b are charged differently in the respective charge storage film patterns, and have different threshold voltages.

That is, the second selection transistor 106a connected in series with the first selection transistor 104a must be electrically provided as an increasing transistor. Thus, the second selection transistor 106a maintains the programmed state P and has a relatively high threshold voltage of 0V or higher.

On the other hand, the fourth selection transistor 106b connected in series with the third selection transistor 104b must be provided as an electrically depletion type transistor D. [ However, since the fourth selection transistor 106b is the depletion type transistor D even in the initial state in which no programming or erasing operation is performed, the fourth selection transistor 106b has a low threshold voltage of 0 V or less without any additional electrical operation. Therefore, the fourth selection transistor may be an erased state or an initial state.

Hereinafter, a method of adjusting the threshold voltages of the second and fourth selection transistors in the NAND flash memory device shown in Figs. 12 and 13 will be described.

14A and 14B are circuit diagrams for explaining a threshold voltage adjusting operation of a transistor included in the NAND flash memory device shown in FIG.

In the NAND flash memory device shown in FIG. 12, the second selection transistors 106a have a relatively high threshold voltage, and the fourth selection transistors 106b have a relatively low threshold voltage. To this end, an erase operation is performed on both the second and fourth selection transistors 106a and 106b. Thereafter, only the second selection transistors 106a selectively perform a programming operation.

14A shows performing the erase operation for both the second and fourth selection transistors 106a and 106b. For erase operation, an electrical signal is applied as shown in the following table.

When the above operation is performed, the erase operation is also performed on the second and fourth selection transistors 106a and 106b and the cell transistor 108. [

However, in the case of this embodiment, since the fourth selection transistor 106b is provided as a depletion type transistor, it has a threshold voltage lower than 0V even if a separate erasing operation is not performed. Therefore, the erase operation described above may not be performed.

14B shows performing a programming operation for the second selection transistors. For programming operation, an electrical signal is applied as shown in the following table.

When the above operation is performed, the third selection transistor 104b is turned off and the programming operation is not performed on the fourth selection transistor 106b. On the other hand, the programming operation is performed on the second selection transistor 106a by turning on the first selection transistor 104a. Therefore, the threshold voltage of the second selection transistor 106a is set to be higher than 0V.

During the programming operation, the threshold voltage verification operation must be continuously performed. When the threshold voltage of the second selection transistor 106a rises above the set reference voltage, the programming operation is no longer performed.

In the cell array of Example 2, the charge storage film pattern can be used as a floating gate electrode or as a charge trap film pattern.

The NAND flash memory device of the second embodiment is the same as the NAND flash memory device of the first embodiment except for the conductivity type of the impurity doped in the channel region of the second and fourth selection transistors 106a and 106b. Therefore, the NAND flash memory device of the second embodiment can be manufactured in substantially the same manner as the manufacturing method described in the first embodiment. However, in the step of doping the N-type impurity for forming the channel region of the first select transistor 104a, the channel regions of the second and fourth select transistors 106a and 106b are doped with N-type impurities Only the channel regions of the second and fourth selection transistors are formed.

Example 3

15 is a circuit diagram of a NAND flash memory device according to a third embodiment of the present invention.

The NAND flash memory device according to the third embodiment is the same as the NAND flash memory device according to the first embodiment except for the configuration of the select transistor.

Referring to FIG. 15, one of the second group selection transistors is provided as a depletion type MOS transistor (D), and the other is provided as an increasing type MOS transistor (E). For example, the first selection transistor 104a is provided as an enhancement type MOS transistor E and the third selection transistor 104b is provided as a depletion type MOS transistor D.

Also, the second and fourth selection transistors 106a and 106b, which are the first group selection transistors, are all provided with an increase-type cell type transistor having a channel region and an impurity region provided as a source / drain with different conductivity types .

And a plurality of second selection transistors 106a are connected in series to one cell string sharing a bit line. Each of the second selection transistors 106a physically has the same configuration as the cell transistors 108. [ In addition, each of the second selection transistors 106a has a shorter gate length than the first group selection transistors 104a and 104b. In one example, each of the second selection transistors 106a may have a gate length substantially equal to the cell transistor 108. [ The plurality of second select transistors connected in series have channel regions connected to each other, so that they can be electrically operated as one transistor.

And the other cell string sharing the bit line has a shape in which a plurality of fourth selection transistors 106b are connected in series. Each of the fourth selection transistors 106b physically has the same configuration as the cell transistors 108. [ In addition, each of the fourth selection transistors 106b has a shorter gate length than the first group selection transistors 104a and 104b. In one example, each of the second selection transistors 106a may have a gate length substantially equal to the cell transistor 108. [ The plurality of fourth selection transistors connected in series may have a configuration in which channel regions are connected to each other, so that they can be electrically operated as one transistor.

The second and fourth selection transistors 106a and 106b have different charges injected into the respective charge storage film patterns, and have different threshold voltages.

Specifically, since the first selection transistor 104a is an incremental MOS transistor, the second selection transistors 106a connected in series to the first selection transistor 104a are electrically provided as a depletion type transistor. Thus, the second select transistor remains in the erased state and has a threshold voltage lower than 0V.

On the other hand, since the third selection transistor 104b is a depletion type MOS transistor, the fourth selection transistors 106b connected in series to the third selection transistor 104b are electrically provided as an increasing transistor. Therefore, the fourth selection transistor 106b is maintained in the programmed state, and has a threshold voltage lower than 0V.

16 is a circuit diagram for explaining a threshold voltage adjusting operation of a transistor included in the NAND flash memory device shown in FIG.

In the NAND flash memory device shown in FIG. 15, the second select transistors have a relatively high threshold voltage, and the fourth select transistors have a relatively low threshold voltage.

To this end, an erase operation is performed on all of the second and fourth selection transistors. The electrical signals applied during the erase operation are as follows.

When the erase operation is performed on the cell transistor 108, a Vrelax voltage is applied to the first gate line closest to the second gate line among the plurality of first gate lines. The Vrelax voltage is higher than 0 V and smaller than the erase voltage applied to the P-well. Thus, by applying a voltage higher than 0 V to the first gate line closest to the second gate line, it is possible to suppress the breakdown between the floating second gate line and the first gate line.

Next, as shown in FIG. 16, programming operations are sequentially performed on the fourth selection transistors, respectively. For programming operation, an electrical signal is applied as shown in the following table.

When the operation is performed as described above, the first selection transistor 104a is turned off, and no programming operation is performed on the second selection transistors 106a. On the other hand, the third selection transistor 104b is turned on. A programming operation is performed by applying the programming voltage Vpgm to the selected first gate line SSL1 " '. Also, the path voltage Vpass is applied to the unselected first gate lines SSL1 'and SSL1' '', and is not programmed.

SSL1 ', and SSL1' '' so that all of the fourth selection transistors 106b connected in series are all programmed to sequentially perform the programming operation. Thereby, the threshold voltage of the fourth selection transistors 106b is made higher than 0V.

Further, during the programming operation, the threshold voltage verification operation can be continuously performed.

The circuits of the cell array of the NAND flash memory device of Fig. 15 can be variously formed on the substrate according to the process design. Hereinafter, an example in which the cell arrays of the NAND flash memory device shown in FIG. 15 are implemented on a substrate will be described.

17 is a cross-sectional view showing a cell array of the NAND flash memory device shown in FIG.

17, a first gate structure 140 for the cell transistor, a second gate structure 142 for the second and fourth selection transistors, and a third gate structure 142 for the first and third selection transistors and the ground selection transistor A gate structure 144 is provided.

The first gate structures 140 have a shape in which a tunnel insulating layer 130, a floating gate electrode 132, a blocking dielectric layer pattern 134, and a control gate electrode 136 are stacked. The first gate structure 140 has a first line width.

The second gate structures 142 are formed in the same manner as the first gate structure 140 by forming the tunnel insulating film 130, the floating gate electrode 132, the blocking dielectric film pattern 134 and the control gate electrode 136 in a stacked configuration . The floating gate electrode 132 of the second gate structure 142 is charged with a charge for controlling a threshold voltage. The second gate structures 142 have narrower linewidths than the third gate structures 144. In this embodiment, the second gate structure 142 has a first line width d1 as the first gate structure 140. The channel regions under the second gate structures 142 are doped with P-type impurities. The channel regions 135a of the second selection transistor connected in series have a shape connected to each other. In addition, the channel regions 135b of the fourth selection transistor connected in series have a shape connected to each other.

The third gate structures 144 have a stacked structure of a tunnel insulating layer 130, a floating gate electrode 132, a blocking dielectric layer pattern 134, and a control gate electrode 136, Are connected to each other. The third gate structure 144 has a second line width d2 that is wider than the first line width d1. The floating gate electrode of the third gate structure 144 does not function as a charge storage film.

In the present embodiment, since the second selection transistors 106a must be in an erased state, a positive charge is injected into the floating gate electrode 132 included in the second selection transistors 106a. In addition, since the fourth selection transistor must be programmed, a negative charge is injected into the floating gate electrode 132 included in the fourth selection transistor.

The cell array of the third embodiment is formed by patterning thin films to form a plurality of second and fourth selection transistors. Therefore, it can be manufactured in the same manner as the method of manufacturing the cell array of Embodiment 1 except for the above patterning process.

18 is a cross-sectional view of another laminated structure showing a cell array of the NAND flash memory device shown in FIG.

18 is the same as that shown in Fig. 17 except that the charge storage film included in each gate structure is used as the charge trap film pattern. Since the charge storage film is used as the charge trap film pattern, the first to third gate structures 140, 142b and 144a are all formed of the tunnel insulating film 150, the charge trap film pattern 152, the blocking dielectric film pattern 154, And a control gate electrode 156 are stacked.

Example 4

19 is a circuit diagram of a cell array of a NAND flash memory device according to a fourth embodiment of the present invention. 20 is a cross-sectional view of a cell array of a NAND flash memory device according to a fourth embodiment of the present invention.

The cell array according to the fourth embodiment is the same as the NAND flash memory device according to the third embodiment except that a dummy transistor is added.

Referring to FIGS. 19 and 20, dummy transistors d1 and d2 are connected between the first group selection transistors 106a and 106b and the second group selection transistors 104a and 104b. The dummy transistors d1 and d2 may be the same channel type transistors as the first group selection transistors 106a and 106b.

That is, a first dummy transistor d1 is connected between the first and second selection transistors 104a and 106a. A second dummy transistor d2 is connected between the third and fourth selection transistors 104b and 106b. The first and second dummy transistors d1 and d2 may be enhancement transistors. The first and second dummy transistors d1 and d2 may have the same gate length as the first group select transistor.

The dummy transistors d1 and d2 are pass transistors and do not perform a switching function. Therefore, the dummy transistors d1 and d2 serve to increase the interval between the first group selection transistor and the second group selection transistor. Therefore, it is possible to suppress an operation failure caused by an inhibit operation in the selection transistor adjacent to the second group selection transistor by the second group selection transistors.

Among the first group selection transistors 106a and 106b, the second selection transistors 106a are in an erased state and electrically function as a depletion type transistor and have a threshold voltage of 0 V or less. In addition, since the fourth selection transistors 106b are in a programming state, they electrically function as an increasing transistor and have a threshold voltage of 0V or more.

No programming or erasing operations are performed on the dummy transistors d1 and d2, so that the dummy transistors d1 and d2 have an initial state threshold voltage. The threshold voltage of the initial state is lower than the threshold voltage of the programming state and becomes a threshold voltage higher than the threshold voltage of the erasing state.

As shown, the third and fourth selection transistors 104b and 106b are depletion type and increment type transistors, respectively, so that impurities in the channel region have different conductivity types. Therefore, when the distance between the third and fourth selection transistors 104b and 106b is narrow, impurities in the channel region of the third selection transistor 104b, which is the depletion type transistor, The threshold voltage of the fourth selection transistor 106b may be varied. However, since the second dummy transistor d2 is provided between the third and fourth selection transistors 104b and 106b as in the present embodiment, the interval between the third and fourth selection transistors 104b and 106b So that the problem that the threshold voltage fluctuates due to the impurity diffusion can be suppressed.

And one dummy transistor is formed in each string. However, in another embodiment, a plurality of dummy transistors may be serially connected between the first group select transistor and the second group select transistor in each string. In this case, the interval between the first group selection transistors 104a and 104b and the second group selection transistors 106a and 106b is further increased.

In the cell array of the NAND flash memory device of FIGS. 19 and 20, an erase operation is performed on the second selection transistor 106a so that a positive charge is stored in the charge storage film pattern. A programming operation is performed on the fourth selection transistor 106b so that a negative charge is stored in the charge storage film pattern. However, the dummy transistors d1 and d2 must not be subjected to erase and programming operations.

Hereinafter, a method of adjusting the threshold voltages of the selection transistors in the NAND flash memory device of the present embodiment will be described.

First, an erase operation is performed on the second and fourth selection transistors. At this time, the first and second dummy transistors (d1, d2) are not subjected to the erasing operation or the erasing operation is suppressed, so that the first and second dummy transistors (d1, d2) . For erase operation, an electrical signal is applied as shown in the following table.

Thus, the erase operation is suppressed to the dummy transistors d1 and d2 by applying the erase suppression voltage Vrelex to the dummy gate line. The erase suppression voltage Vrelex may be set to a value lower than the threshold voltage of the depletion type transistor and lower than the erase voltage Vers supplied to the p-well for erasing the selection transistor.

Next, the programming operation is sequentially performed for each of the fourth selection transistors.

For the programming operation of the fourth selection transistor, an electrical signal is applied as shown in the following table.

As described above, by applying the power supply voltage to the gate line of the dummy transistors d1 and d2, the dummy transistors d1 and d2 can be maintained in the initial state without being programmed. In addition, the fourth selection transistors 106b sequentially perform a programming operation.

During the programming operation, the threshold voltage verification operation can be continuously performed.

The cell array of the NAND flash memory device shown in Figs. 19 and 20 is the same as that described in the third embodiment, except that a dummy transistor is added, and the cross-sectional structure and manufacturing method of each cell are also described.

In Fig. 20, the charge storage film included in each cell array is shown as a charge trap film pattern. However, the charge storage film may be formed of a floating gate electrode.

Example 5

21 is a circuit diagram of a cell array of a NAND flash memory device according to a fifth embodiment of the present invention. 22 is a cross-sectional view of a cell array of a NAND flash memory device according to a fifth embodiment of the present invention.

The NAND flash memory device according to the sixth embodiment is the same as the NAND flash memory device according to the fifth embodiment except that dummy transistors included in one string are further added.

21 and 22, first group dummy transistors d1 and d2 are provided between the first group select transistor and the second group select transistor. In addition, second group dummy transistors d3 and d4 are provided between the first group select transistor and the cell transistor.

The first group of dummy transistors includes a first dummy transistor d1 between the first and second selection transistors 104a and 106a and a second dummy transistor d1 between the third and fourth selection transistors 104b and 106b. d2). The first and second dummy transistors d1 and d2 are increase type transistors.

The second group of dummy transistors includes a third dummy transistor d3 between the second selection transistor 106a and the cell transistors 108 and a third dummy transistor d3 between the fourth selection transistor 106b and the cell transistors 108. [ And a fourth dummy transistor d4 are included. The third and fourth dummy transistors d3 and d4 are increase type transistors.

The second group dummy transistor is provided for suppressing the threshold voltage of the selection transistor adjacent to the cell transistor from being changed by the disturbance driving in the operation of the cell transistor.

The second selection transistors 106a have a threshold voltage of 0 V or less in an erased state. The fourth selection transistors 106b have a threshold voltage of 0 V or more in a programmed state.

The first and second group dummy transistors d1 to d4 are provided as pass transistors without switching. The first and second group dummy transistors (d1, d2) have first and second initial threshold voltages, respectively. The first and second initial threshold voltages are respectively lower than the threshold voltage of the programmed select transistor and higher than the threshold voltage of the select transistor in the erase state. The first and second initial threshold voltages may be the same or different from each other.

In another embodiment, although not shown, the first group dummy transistor and the second group dummy transistor may include a plurality of dummy transistors.

In another embodiment, although not shown, the first group of dummy transistors may not be provided, and only the second group of dummy select transistors may be provided.

In the cell array shown in Figs. 21 and 22, an erase operation is performed on the second selection transistor 106a so that a positive charge is stored in the charge storage film pattern. A programming operation is performed on the fourth selection transistor 106b so that a negative charge is stored in the charge storage film pattern. In addition, the first group and second group dummy transistors (d1 to d4)) should be prevented from interfering with a selection transistor adjacent to the dummy transistor while suppressing erasing and programming operations.

The method of adjusting the threshold voltages of the selection transistors is the same as that described in the fifth embodiment. The same voltage signal as that applied to the dummy transistors of the fifth embodiment is applied to the first and second group dummy transistors.

As described above, the second group of dummy transistors d3 and d4 are provided for suppressing the threshold voltage of the selection transistor adjacent to the cell transistor 108 from being changed by the disturbance driving when the cell transistor is operated .

More specifically, when the erase operation is performed on the cell transistor 108, the threshold voltage level of the select transistor adjacent to the cell transistor 108 may be lowered. That is, the threshold voltage of the selection transistor to be maintained in the programmed state is lowered. Conversely, when the programming operation is performed on the cell transistor 108, the threshold voltage level of the selection transistor adjacent to the cell transistor 108 can be increased. That is, the threshold voltage of the selection transistor to be maintained in the erased state is increased.

In order to reduce this problem, when the erase operation is performed on the cell transistor 108, a Vrelax voltage is applied to the gate line dummy2 of the second group of dummy transistors d3 and d4. The Vrelax voltage is higher than 0 V and smaller than the erase voltage applied to the P-well. Thus, by applying a constant voltage to the gate lines of the second group of dummy transistors d3 and d4 during the erase operation of the cell transistors, it is possible to prevent the threshold voltages of the first group select transistors 106a and 106b from being lowered have.

When a programming operation is performed on the cell transistor 108, a power supply voltage Vcc, which is a voltage lower than the programming voltage, is applied to the gate line dummy2 of the second group of dummy transistors d3 and d4. Thus, it is possible to prevent the threshold voltages of the first group select transistors 106a and 106b from increasing.

The cell array of the NAND flash memory device shown in Figs. 21 and 22 is the same as that described in the third embodiment, except that a dummy transistor is further added, and the cross-sectional structure and manufacturing method of each cell are described.

In Fig. 22, the charge storage film included in each cell array is shown as a charge trap film pattern. However, the charge storage film may be formed of a floating gate electrode.

Example 6

23 is a circuit diagram of a cell array of the NAND flash memory device according to the sixth embodiment of the present invention. 24 is a cross-sectional view of a cell array of a NAND flash memory device according to a sixth embodiment of the present invention.

23 and 24, a first cell string 102a and a second cell string 102b connected to the shared bit line B / L are included. The first and second selection transistors 105a and 107a are connected in series to the first cell string 102a and the third and fourth selection transistors 105b and 107b are connected in series to the second cell string. The first to fourth selection transistors 105a, 107a, 105b, and 107b are provided as a depletion type or an increasing type transistor in accordance with a conductivity type doped to a channel, and transistors of different types are serially connected to each string.

In the present embodiment, the first selection transistor 105a is an increase type transistor E and the second selection transistor 107a is a depletion type transistor D. [ The third selection transistor 105b is a depletion type transistor D and the fourth selection transistor 107b is an increasing type transistor E. [ As described above, the first and third selection transistors 105a and 105b adjacent to the shared bit line B / L are referred to as a second group selection transistor, and the second and third selection transistors 105a and 105b adjacent to the cell transistor 108, Fourth selection transistors 107a and 107b are referred to as a first group selection transistor.

As shown in the figure, the first group selection transistors may be connected in series with a plurality of transistors having a smaller line width than the second group selection transistors.

The channel regions of the first and fourth selection transistors 105a and 107b, which are the increase type transistors E, are doped with impurities at a higher concentration than the channel region of the cell transistor.

The fourth selection transistor 107b, which is the incremental transistor E in the first group selection transistor, has a target threshold voltage by programming. That is, the fourth selection transistor 107b is in a programmed state (P). On the other hand, the threshold voltage of the first select transistor 105a, which is the enhancement transistor E of the second group select transistor, is determined by the impurity concentration doped in the channel.

As another example, the fourth selection transistor 107b, which is the incremental transistor E in the first group selection transistor, has a target threshold voltage by programming. That is, the fourth selection transistor 107b is in a programmed state (P). Also, the first selection transistor 105a, which is the incremental transistor E of the second group selection transistor, also has a target threshold voltage by programming.

In this way, the threshold voltage of the selection transistor can be adjusted by programming.

25 is a schematic diagram of a memory card according to an embodiment of the present invention.

Referring to FIG. 25, the memory card 400 may include a controller 410 and a memory 420 in a housing 430. Controller 410 and memory 420 may exchange electrical signals. For example, in accordance with a command of the controller 410, the memory 420 and the controller 410 can exchange data. Accordingly, the memory card 400 can store data in the memory 420 or output the data from the memory 420 to the outside.

For example, the memory 420 may include a NAND flash memory device according to an embodiment of the present invention described above. The memory card 400 may be used as a data storage medium of various portable devices. For example, the memory card 400 may include a multi media card (MMC) or a secure digital card (SD) card.

26 is a block diagram of an electronic system according to an embodiment of the present invention.

26, the electronic system 500 may include a processor 510, an input / output device 530, and a memory chip 520, which may communicate with each other using a bus 540 can do. The processor 510 may be responsible for executing the program and controlling the system 500. The input / output device 530 may be used to input or output data of the system 500. The system 500 may be connected to an external device, e.g., a personal computer or network, using the input / output device 530 to exchange data with the external device. The memory 520 may store code and data for operation of the processor 510. For example, the memory 520 may include a NAND flash memory device according to an embodiment of the present invention described above.

As described above, according to the present invention, it is possible to provide a highly integrated NAND flash memory device having a shared bit line. The NAND flash memory device can configure various electronic control devices and can be used for, for example, a mobile phone, an MP3 player, navigation, a solid state disk (SSD), or household appliances .

102a, 102b: first and second cell strings
104a, 106a, 104b, 106b: first to fourth selection transistors
108: Cell transistor 110: Ground selection transistor
130: tunnel insulating film 132: floating gate electrode
134: blocking dielectric layer pattern 136: control gate electrode
138: bit line contact 140, 140a: first gate structure
142, 142a, 142b: a second gate structure
144, 144a: third gate structure 150: tunnel insulating film
152: charge trap film 154: blocking dielectric film
156: Control gate electrode

Claims (13)

A shared bit line;
A first selection transistor connected in series to the common bit line and connected in series, the channel region being of an increasing type having a first conductivity type and having a threshold voltage higher than the first reference voltage, A first cell string including a second select transistor having a lower threshold voltage, cell transistors, and a ground select transistor;
A third selection transistor connected in common to the shared bit line and serially connected in series, the channel region being of a depletion type having a second conductivity type and having a threshold voltage lower than the first reference voltage, A second cell string including a fourth selection transistor having a threshold voltage higher than the second reference voltage, the cell transistors, and the ground selection transistor; And
And a common source line commonly connected to ends of the ground selection transistors included in the first and second cell strings,
And the second and fourth selection transistors have the same stacking structure as the cell transistors. The semiconductor memory device according to claim 1, wherein the channel regions of the second and fourth selection transistors have the same conductivity type. 3. The semiconductor memory device according to claim 2, wherein the second and fourth selection transistors are depletion type transistors whose channel region is the first conductivity type or whose channel region is the second conductivity type. The semiconductor memory device according to claim 1, wherein the channel regions of the second and fourth selection transistors have opposite conductivity types. The semiconductor memory device according to claim 4, wherein the second selection transistor is a depletion type transistor having a channel region of a second conductivity type, and the fourth selection transistor is an enhancement type transistor having a channel region of a first conductivity type. delete The semiconductor memory device according to claim 1, wherein said second select transistor is in an erased state and said fourth select transistor is in a programmed state. The semiconductor memory device according to claim 1, wherein the second select transistor has a threshold voltage in an initial state, and the fourth select transistor is in a programmed state. The semiconductor memory device according to claim 1, wherein the second and fourth selection transistors include a plurality of transistors connected in series. The semiconductor memory device according to claim 1, wherein at least one of a region between the shared bit line and the selection transistor adjacent to the shared bit line, and a region between the cell transistors and the selection transistor adjacent to the cell transistor, Are connected in series. delete delete delete

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