KR101863578B1 - Apparatus for Adaptive Cache Access in Computing System and Method thereof - Google Patents

Abstract

[0001] The present invention relates to an adaptive cache memory access apparatus and method for a computing system, and more particularly, to an adaptive cache memory access apparatus and method for a computing system, which comprises a CPU core, a hierarchical memory cache, a plurality of IP (Intellectual Properties) A cache memory access device, comprising: a CPU core including an L1 cache and an L2 cache in a core clock domain, and installed between the L1 cache and the L2 cache, for accessing the L2 cache according to memory latency performance And a bypass controller for determining either one of a bypass mode for bypassing bypass mode and a normal mode using the L2 cache, wherein the bypass controller has a clock domain different from the CPU core and the plurality of IPs, And a system level cache installed between the plurality of IPs. Accordingly, the present invention is based on the fact that when the access speed of the L2 cache and the system level cache is reversed due to the influence of the DVFS when the PU core and the system level cache (corresponding to the L3 cache) operate in different clock domains, By bypassing and directly accessing the system level cache, performance can be improved, by applying power gating to the L2 cache, reducing unnecessary energy and increasing overall system performance and energy efficiency.

Description

[0001] Apparatus for Adaptive Cache Memory Access in a Computing System [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an adaptive cache memory access apparatus and method for a computing system, and more particularly, To an adaptive cache memory access apparatus and method thereof.

Recently, mobile devices are required to have high performance and high energy efficiency according to user's demand. Large system level caches (typically L3 caches in computing systems) within mobile on-chips (SoCs) are very helpful in improving the performance of mobile devices.

Recently, a level (L1, L2, L3, etc.) cache is interposed between the CPU and the main memory for fast data processing. Caches have faster access times than main memory, but they are slower in size. Therefore, in the case of the L1 cache (or level 1), the size is reduced to increase the access speed, and in the case of the L2 cache (or the level 2), the size is increased instead of slowing the speed, Cache design is being done.

As described above, as the utilization of the cache memory becomes higher, the capacity of the cache becomes larger and the structure becomes more complicated, the influence of the cache memory on the power consumption of the entire chip is also increasing.

1 is a diagram illustrating a memory hierarchy structure of a general computing system.

1, a typical computing system may comprise a SoC 10 including a CPU core 11, a system level cache 13, a plurality of IPs 12, and a memory subsystem 20 .

From the CPU's point of view, the system level cache 13 can be shared across all IPs in the SoC 10 but operates as a last-level cache.

CPU core 11, system level cache 13, IPs 12 operate in different clock frequency domains for fine-grained power / energy management. The CPU core 11 operates at 0.4 GHz to 2.0 GHz, and one frequency step is 400 MHz while the system level cache operates at 1 GHz.

In terms of energy efficiency, the mobile SoC uses Dynamic Voltage-Frequency Scaling (DVFS), which changes the voltage and operating frequency of the internal function block according to the application for efficient power / energy management. That is, DVFS can adjust the clock frequency of the CPU core according to the voltage (size of operation). Mobile processors have different voltage and frequency ranges, and operating systems typically control the voltage and frequency levels depending on the amount required by the computing loads.

For example, when high computational power is required, the operating system increases to the voltage and frequency levels suited to the performance requirements, and in the opposite case the operating system reduces the voltage and frequency to reduce voltage / energy consumption.

On the other hand, typical mobile SoCs have multiple clock frequency domains for energy efficiency than those with a single glance frequency domain. Thus, mobile CPUs, GPUs, various types of controllers or accelerators, and large system level caches have different operating clock frequencies. However, due to the difference in clock frequencies of the various IPs in the SoC, in the case of abnormal cache access behavior, i.e. higher level caches have a longer latency than system level cache or L3 cache operating in different clock domains as compared to CPU and GPU . This may occur when the CPU is running at a relatively low clock frequency while the last level caches operate at a high clock frequency. In this case, accessing the cache in the CPU has a problem in that it leads to performance degradation and energy inefficiency rather than directly accessing the system level cache.

If the CPU core 11 operates at 2 GHz and operates at 400 MHz, when the CPU core 11 operates at 2 GHz, the L2 cache normally operates at a faster access speed The conventional memory hierarchy is maintained. However, when the CPU core 11 operates at 400 MHz, the L2 cache has a slower access speed than the system level cache.

In the case of the L2 cache, since the clock is operated in the same clock domain as the CPU core, the number of cycles is increased, so that the clock cycle time is increased and the actual access time is increased when the clock frequency is lowered. However, since the system level cache operates in a clock domain different from the clock domain of the CPU core 11, the access time remains the same regardless of the clock frequency of the CPU core without DVFS.

That is, when the clock frequency of the CPU core is 2 GHz, the access latency of the L1 cache is 2 ns, the access latency of the L2 cache is 6 ns, and the access latency of the system level cache is 15 ns. However, when the clock frequency of the CPU core is 400 MHz, the L1 cache access latency is 10 ns, the L2 cache access latency is 30 ns, and the system level cache access latency is 15 ns.

Thus, when the L2 cache and the system level cache operate in different clock domains, the access speed is reversed due to the DVFS, so accessing the L2 cache is slower than accessing the system level cache, There is a problem that energy consumed at the same time as wasting energy is also wasted.

Korea Publication No. 2015-0067433 "Multi-core CPU system capable of controlling L2 cache characteristics, method of operating the same, and apparatuses including the same"

A bypass controller is provided between the L1 cache and the L2 cache of the CPU core. The bypass controller determines whether to use the L2 cache dynamically by comparing the access latency of the L2 cache with the access latency of the system level cache, The present invention provides an adaptive cache memory access apparatus and method for a computing system that can improve performance and reduce energy consumption by applying power gating when L2 cache is not used.

Among the embodiments, an adaptive cache memory access device of a computing system includes a CPU core, a hierarchical memory cache, a plurality of intellectual properties (IPs), and an adaptive cache memory access of a computing system having multiple clock frequency domains Wherein the CPU core includes an L1 cache and an L2 cache in a core clock domain and is installed between the L1 cache and the L2 cache and bypasses access to the L2 cache according to memory latency performance Bypass mode or a normal mode using the L2 cache, wherein the bypass controller has a clock core different from the CPU core and a plurality of IPs, And a system level cache installed between the IPs.

The bypass controller compares the access latency (LAT _sys) of the L2 cache access latency (LAT _L2) and system-level cache of performing the normal mode if the LAT _L2 the LAT _sys is less than, and the LAT _L2 the LAT and the bypass mode is performed when the value is equal to or greater than the value of _sys .

At this time, in the normal mode, the CPU core operates in a normal cache hierarchy structure while using the L2 cache, and in the bypass mode, bypass access to the L2 cache and directly accesses the system level cache.

Wherein the bypass controller comprises: control logic for determining whether to bypass or use the L2 cache; Power gating logic for controlling to supply or block power supplied to the L2 cache; And data update logic for updating, in the system level cache, dirty data present in the L2 cache for data consistency when the L2 cache enters a power gating state.

The control logic is a decision algorithm for calculating the access latency (LAT _L2 ) of the L2 cache and the access latency (LAT _sys ) of the system level cache; And a frequency profiler for maintaining the clock frequency of the CPU core and the system level cache so that the decision algorithm is performed.

Meanwhile, the data update logic temporarily suspends the operation of the CPU core to prevent the data from being deformed during data update.

The bypass controller performs a process of determining a mode of either the bypass mode or the normal mode for each Dynamic Voltage-Frequency Scaling (DVFS) scheduling time allocation amount.

When the operation mode is changed from the bypass mode to the normal mode, the control logic informs the power gating logic of the operation mode change state to operate the L2 cache, and when the operation mode is changed to the bypass mode in the normal mode Wherein the control logic informs the power gating logic and the data update logic of the operating mode change state.

Among embodiments, an adaptive cache memory access method of a computing system includes a CPU core, a hierarchical memory cache, a plurality of intellectual properties (IPs), and an adaptive cache memory approach of a computing system having multiple clock frequency domains The method comprising: placing an L1 cache and an L2 cache in the CPU core, and placing a system level cache between the CPU core and a plurality of IPs to maintain a memory hierarchy; Installing a bypass controller in the CPU core to determine whether to bypass access to the L2 cache according to memory latency performance; Determining whether to use the L2 cache by comparing the access latency (LAT _L2 ) of the _L2 cache with the access latency (LAT _sys ) of the system level cache when the clock frequency of the CPU core is determined; And if the use of the L2 cache is determined, the CPU core operates in a normal memory hierarchy, bypassing access of the L2 cache and directly accessing the system level cache if the L2 cache is unused .

The bypass controller compares the access latency (LAT _L2 ) of the _L2 cache with the access latency (LAT _sys ) of the system level cache to perform a normal mode using the L2 cache when the LAT _L2 is less than LAT _sys And a bypass mode for directly accessing the system level cache without using the L2 cache when the LAT _L2 is equal to or greater than LAT _sys .

The bypass controller performs a process of determining a mode of either the bypass mode or the normal mode for each Dynamic Voltage-Frequency Scaling (DVFS) scheduling time allocation amount.

Bypassing access to the L2 cache and directly accessing the system level cache when the L2 cache is not used may comprise operating the power gating logic to perform power gating to supply or block power supplied to the L2 cache The method comprising the steps of:

Bypassing access to the L2 cache and directly accessing the system level cache when the L2 cache is unused is further characterized in that when the L2 cache enters a power gating state, And operating the data update logic to update the existing dirty data to the system level cache.

And when the data update logic is operated, suspends the operation of the CPU core to prevent deformation of the data during data update.

Wherein the bypass controller determines whether to use the L2 cache by comparing the access latency (LAT _L2 ) of the _L2 cache with the access latency (LAT _sys ) of the system level cache when the clock frequency of the CPU core is determined, Performing a decision algorithm to calculate an access latency (LAT _L2 ) of the cache and an access latency (LAT _sys ) of the system level cache, and maintaining the clock frequency of the CPU core and the system level cache such that the decision algorithm is performed .

An adaptive cache memory access device and method of a computing system of the present invention is characterized in that when a CPU core and a system level cache (corresponding to an L3 cache) operate in different clock domains, The L2 cache can be bypassed and the system level cache can be directly accessed to improve the performance. In this case, power gating can be applied to the L2 cache to reduce unnecessary energy, Energy efficiency can be improved.

1 is a diagram illustrating a memory hierarchy structure of a general computing system.
2 is a diagram illustrating a configuration of an adaptive cache memory access apparatus of a computing system according to an embodiment of the present invention.
3 is a block diagram for explaining a configuration of a bypass controller which is a component of Fig.
4 is a flowchart illustrating an adaptive memory access method of a computing system according to an embodiment of the present invention.

The description of the present invention is merely an example for structural or functional explanation, and the scope of the present invention should not be construed as being limited by the embodiments described in the text. That is, the embodiments are to be construed as being variously embodied and having various forms, so that the scope of the present invention should be understood to include equivalents capable of realizing technical ideas. Also, the purpose or effect of the present invention should not be construed as limiting the scope of the present invention, since it does not mean that a specific embodiment should include all or only such effect.

Meanwhile, the meaning of the terms described in the present invention should be understood as follows.

The terms "first "," second ", and the like are intended to distinguish one element from another, and the scope of the right should not be limited by these terms. For example, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" to another element, it may be directly connected to the other element, but there may be other elements in between. On the other hand, when an element is referred to as being "directly connected" to another element, it should be understood that there are no other elements in between. On the other hand, other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

It should be understood that the singular " include "or" have "are to be construed as including a stated feature, number, step, operation, component, It is to be understood that the combination is intended to specify that it does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In each step, the identification code (e.g., a, b, c, etc.) is used for convenience of explanation, the identification code does not describe the order of each step, Unless otherwise stated, it may occur differently from the stated order. That is, each step may occur in the same order as described, may be performed substantially concurrently, or may be performed in reverse order.

All terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs, unless otherwise defined. Commonly used predefined terms should be interpreted to be consistent with the meanings in the context of the related art and can not be interpreted as having ideal or overly formal meaning unless explicitly defined in the present invention.

2 is a diagram illustrating a configuration of an adaptive cache memory access apparatus of a computing system according to an embodiment of the present invention.

2, an adaptive cache memory access device of a computing system includes a CPU core 11, a hierarchical memory cache of an L1 cache, an L2 cache and a system level cache (or L3 cache) 13, a plurality of IP (12) and a mobile SoC (10) having multiple clock frequency domains and a memory subsystem (20).

The CPU core 11 includes a bypass mode for bypassing access to the L2 cache in accordance with the memory latency performance, which is installed between the L1 cache and the L2 cache, including the L1 cache and the L2 cache in the core clock domain, And a bypass controller (100) for determining an operation mode of any one of the normal modes using the L2 cache.

That is, the bypass controller 100 performs a bypass mode when bypassing access to the L2 cache and determining that direct access to the system level cache 13 is advantageous in terms of performance, and the L2 cache performs power gating To reduce energy consumption.

On the other hand, the system level cache 13 has a different clock domain from the CPU core 11 and the plurality of IPs 12.

3 is a block diagram for explaining a configuration of a bypass controller which is a component of Fig.

3, the bypass controller 100 includes control logic 110, power gating logic 120, and data update logic 130.

The control logic 110 determines whether to bypass or use the L2 cache. This control logic 110 includes a decision algorithm 111 and a frequency profiler 112.

The decision algorithm 111 calculates the access latency (LAT _L2 ) of the L2 cache and the access latency (LAT _sys ) of the system level cache, and the frequency profiler 112 determines whether the CPU core 11 and the system level And maintains the clock frequency of the cache 13.

The clock frequency of the CPU affects performance and power usage. The frequency governor determines the clock frequency of the CPU at any given time based on a set of rules for the kind of message behavior to change the high or low frequency. Thus, the frequency profiler 112 maintains the determined clock frequency in the frequency governor.

The power gating logic 120 may control to supply or block power supplied to the L2 cache to reduce energy consumption.

The data update logic 130 updates dirty data in the L2 cache to the system level cache 13 for consistency of data when the L2 cache enters a power gating state. At this time, the data update logic 130 temporarily suspends the operation of the CPU core 11 to prevent the data from being deformed during data update.

Meanwhile, when the operation mode is changed from the bypass mode to the normal mode (b_to_n change), the control logic 110 notifies the power gating logic 120 of the operation mode change state so that the L2 cache is operated, The power gating logic 120 and the data update logic 130 are informed of the operation mode change state when the operation mode is changed (n_to_b change).

4 is a flowchart illustrating an adaptive memory access method of a computing system according to an embodiment of the present invention.

4, when the computing system's adaptive memory access method determines the clock frequency of the CPU core 11 in the operating system, the bypass controller 100 controls the access latency (LAT _L2 ) of the L2 cache and the system level cache The access latency (LAT _sys ) of the L2 cache is compared to determine whether to use the L2 cache (S1, S2)

That is, the bypass controller 100 compares the access latency (LAT _L2 ) of the L2 cache with the access latency (LAT _sys ) of the system level cache 13 and performs a normal mode when the LAT _L2 is less than LAT _sys . S3, and S4. When the normal mode is performed, the CPU core 11 operates in a normal memory hierarchy. (S5)

However, bypass controller 100 performs a bypass mode when LAT _L2 is equal to or greater than LAT _sys (S3, S6). When bypass mode is performed, CPU core 11 bypasses L2 cache access After power gating is applied to the L2 cache, direct access to the system level cache 13 results in data going directly back and forth between the L1 cache and the system level cache 13 (S7, S8) without going through the L2 cache.

In order to ensure data consistency, the bypass controller 100 updates the dirty data existing in the L2 cache to the system level cache when the L2 cache enters the power gating state, Block the operation of the core momentarily.

The bypass controller 100 performs a process of determining a mode of either the bypass mode or the normal mode for each dynamic frequency-frequency scaling (DVFS) scheduling time allocation amount.

When the CPU core is capable of operating at a clock frequency of 2 GHz at 400 MHz, if the CPU core operates at a clock frequency of 2 GHz, access to the L2 cache results in a performance gain, so that the bypass controller 100 performs a normal mode And operates in a normal memory hierarchy without applying power gating to the L2 cache.

However, if the CPU core operates at a clock frequency of 400 MHz, it is slower than accessing the L2 cache because it is slower than accessing the system level cache. Therefore, the bypass controller 100 performs bypass mode to apply power gating to the L2 cache And direct access to the system level cache.

As described above, the adaptive cache memory access apparatus and method for a computing system according to an exemplary embodiment of the present invention uses a cache bypassing technique to improve performance and energy in a DVFS-capable CPU in an SoC having multiple clock domains, And system-level cache energy consumption can be reduced by up to 14.5% and performance can be improved by up to 0.13%.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention as defined by the following claims It can be understood that

100: bypass controller 110: control logic
111: Decision Algorithm 112: Frequency Profiler
120: Power gating logic 130: Data update logic

Claims (15)

An adaptive cache memory access device of a computing system comprising a CPU core, a hierarchical memory cache, and a plurality of intellectual properties (IPs) and having multiple clock frequency domains,
A CPU core including an L1 cache and an L2 cache in a core clock domain;
A bypass mode for bypassing access to the L2 cache in accordance with memory latency performance or a normal mode using the L2 cache, which is provided between the L1 cache and the L2 cache, A bypass controller; And
And a system level cache having a clock domain different from that of the CPU core and a plurality of IPs, the system level cache being installed between the CPU core and a plurality of IPs,
Wherein the bypass controller comprises:
Control logic for determining whether to bypass or use the L2 cache;
Power gating logic for controlling to supply or block power supplied to the L2 cache; And
And data update logic for updating dirty data present in the L2 cache to the system level cache for data consistency when the L2 cache enters a power gating state. Access device.
The method according to claim 1,
Wherein the bypass controller comprises:
Compares the access latency (LAT _sys) of the L2 cache access latency (LAT _L2) and system-level cache of performing the normal mode if the LAT _L2 the LAT _sys is less than, and the LAT _L2 is bypassed if LAT _sys or more Mode of the computing system.
3. The method of claim 2,
In the normal mode, the CPU core operates in a normal cache hierarchical structure while using the L2 cache,
Wherein the bypass mode bypasses access of the L2 cache and directly accesses the system level cache.
delete The method according to claim 1,
The control logic
A decision algorithm for calculating the access latency (LAT _L2 ) of the L2 cache and the access latency (LAT _sys ) of the system level cache; And
And a frequency profiler for maintaining the clock frequency of the CPU core and the system level cache such that the decision algorithm is performed.
The method according to claim 1,
Wherein the data update logic suspends operation of the CPU core to prevent modification of the data during data update.
The method according to claim 1,
Wherein the bypass controller performs a process for determining a mode of either the bypass mode or the normal mode for each Dynamic Voltage-Frequency Scaling (DVFS) scheduling time allocation amount.
The method according to claim 1,
When the operation mode is changed from the bypass mode to the normal mode, the control logic notifies the power gating logic to the operation mode change state so that the L2 cache is operated,
Wherein the control logic informs the power gating logic and the data update logic of the operating mode change state when the operating mode is changed from the normal mode to the bypass mode.
1. An adaptive cache memory access method of a computing system comprising a CPU core, a hierarchical memory cache, and a plurality of intellectual properties (IPs) and having multiple clock frequency domains,
Placing an L1 cache and an L2 cache in the CPU core, and arranging a system level cache between the CPU core and a plurality of IPs to maintain a memory hierarchy;
Installing a bypass controller in the CPU core to determine whether to bypass access to the L2 cache according to memory latency performance;
Determining whether to use the L2 cache by comparing the access latency (LAT _L2 ) of the _L2 cache with the access latency (LAT _sys ) of the system level cache when the clock frequency of the CPU core is determined; And
And if the use of the L2 cache is determined, the CPU core operates in a normal memory hierarchy and bypassing access of the L2 cache and direct access to the system level cache if the L2 cache is unused ,
Bypassing access of the L2 cache and directly accessing the system level cache comprises:
The L2 cache is operated by power gating logic that performs power gating to cut off power supplied to the L2 cache, and when the L2 cache enters a power gating state, dirty data existing in the L2 cache ) To the system level cache. ≪ RTI ID = 0.0 > [0002] < / RTI >
10. The method of claim 9,
Wherein the bypass controller comprises:
Performing a normal mode using the L2 cache compared to the access latency (LAT _L2) and the access latency (LAT _sys) of the system-level cache, the L2 cache is the LAT _L2 when LAT _sys is less than, and the LAT _L2 the LAT _sys, a bypass mode for accessing the system level cache directly without using the L2 cache is performed.
11. The method of claim 10,
Wherein the bypass controller performs a process for determining a mode of either the bypass mode or the normal mode for each Dynamic Voltage-Frequency Scaling (DVFS) scheduling time allocation amount.
delete delete 10. The method of claim 9,
And when the data update logic is operated, suspends operation of the CPU core to prevent deformation of the data during data update.
10. The method of claim 9,
Wherein the bypass controller determines whether to use the L2 cache by comparing the access latency (LAT _L2 ) of the _L2 cache with the access latency (LAT _sys ) of the system level cache when the clock frequency of the CPU core is determined,
Performing a decision algorithm to compute an access latency (LAT _L2 ) of the L2 cache and an access latency (LAT _sys ) of a system level cache, and maintaining a clock frequency of the CPU core and a system level cache such that the decision algorithm is performed The method comprising the steps of:

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