KR101849572B1 - Method of fabricating liquid crystal display device - Google Patents

Abstract

The method of manufacturing a liquid crystal display of the present invention uses ITO (Indium Tin Oxide) as a barrier metal of a data line to form a data line and a pixel electrode in a single mask, thereby reducing the number of masks and simplifying the manufacturing process Providing an array substrate divided into a pixel portion, a data pad portion, and a gate pad portion for reducing manufacturing cost; Forming a gate electrode and a gate line made of a first conductive film in a pixel portion of the array substrate; Forming a first insulating layer on the entire surface of the array substrate where the gate electrode and the gate line are formed; Forming an active layer and an n + amorphous silicon thin film pattern on a pixel portion of the array substrate on which the first insulating film is formed; The second conductive layer and the third conductive layer are formed on the entire surface of the array substrate on which the active layer and the n + amorphous silicon thin film pattern are formed, and then the second conductive layer and the third conductive layer are selectively removed through the half- Forming a source electrode, a drain electrode, and a data line made of a third conductive film while forming a pixel electrode made of the second conductive film; Selectively removing the n + amorphous silicon thin film pattern on the active layer to form an ohmic contact layer; Forming a second insulating layer on the entire surface of the array substrate on which the ohmic-contact layer is formed; And attaching the array substrate and the color filter substrate together.
In particular, in the method of manufacturing a liquid crystal display device of the present invention, the drain electrode is directly connected to the pixel electrode without passing through the contact hole, and an active tail is not generated compared to the existing four mask structure, .

Description

TECHNICAL FIELD [0001] The present invention relates to a method of manufacturing a liquid crystal display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a liquid crystal display device, and more particularly, to a liquid crystal display device capable of reducing the number of masks and simplifying a manufacturing process, .

Recently, interest in information display has increased, and a demand for using portable information media has increased, and a light-weight flat panel display (FPD) that replaces a cathode ray tube (CRT) And research and commercialization are being carried out. Particularly, among such flat panel display devices, a liquid crystal display (LCD) is an apparatus for displaying an image using the optical anisotropy of a liquid crystal, and is excellent in resolution, color display and picture quality and is actively applied to a notebook or a desktop monitor have.

The liquid crystal display comprises a color filter substrate, an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.

Hereinafter, a general liquid crystal display device will be described in detail with reference to FIG.

1 is an exploded perspective view schematically showing a structure of a general liquid crystal display device.

As shown in the figure, a liquid crystal display generally comprises a color filter substrate 5, an array substrate 10, and a liquid crystal layer formed between the color filter substrate 5 and the array substrate 10, (30).

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 implementing colors of red (R), green (G) and blue (B) A black matrix 6 for separating the sub-color filters 7 from each other and shielding light transmitted through the liquid crystal layer 30 and a transparent common electrode for applying a voltage to the liquid crystal layer 30 8).

The array substrate 10 includes a plurality of gate lines 16 and data lines 17 arranged vertically and horizontally to define a plurality of pixel regions P and a plurality of gate lines 16 and data lines 17 A thin film transistor T which is a switching element formed in the intersection region and a pixel electrode 18 formed on the pixel region P. [

The color filter substrate 5 and the array substrate 10 constituted as described above are adhered to each other by a sealant (not shown) formed on the periphery of the image display area to constitute a liquid crystal panel, and the color filter substrate 5 (Not shown) formed on the color filter substrate 5 or the array substrate 10 are bonded to each other.

In this case, there is a twisted nematic (TN) method in which a nematic liquid crystal molecule is driven in a direction perpendicular to a substrate by a driving method generally used in the liquid crystal display device. However, the twisted nematic liquid crystal display Has a disadvantage that the viewing angle is as narrow as 90 degrees. This is due to the refractive anisotropy of the liquid crystal molecules, because the liquid crystal molecules aligned horizontally with the substrate are oriented in a direction substantially perpendicular to the substrate when a voltage is applied to the panel.

There is an in-plane switching (IPS) type liquid crystal display device in which liquid crystal molecules are driven in a horizontal direction with respect to a substrate to improve a viewing angle to 170 degrees or more.

Since the manufacturing process of the liquid crystal display device basically requires a plurality of mask processes (that is, a photolithography process) to fabricate an array substrate including thin film transistors, a method of reducing the number of masks in terms of productivity is required The following is a detailed description.

FIGS. 2A to 2E are cross-sectional views sequentially illustrating the steps of manufacturing an array substrate of a general liquid crystal display device. In FIGS. 2A to 2E, a process of fabricating an array substrate of a pixel portion is shown on the left side and an array substrate of a data pad portion and a gate pad portion .

2A, a gate electrode 21 and a gate line (not shown) made of a first conductive film are formed in a pixel portion of the array substrate 10 by using a photolithography process (first mask process) And a gate pad line 16p made of the first conductive film is formed on the gate pad portion of the array substrate 10.

Next, as shown in FIG. 2B, a first insulating layer 15a, an amorphous silicon layer 16b, and a second insulating layer 16c are sequentially formed on the entire surface of the array substrate 10 on which the gate electrode 21 and the gate line and gate pad line 16p are formed. The active layer 24 made of the amorphous silicon thin film is formed on the gate electrode 21 by selectively patterning the thin film, the n + amorphous silicon thin film and the second conductive film using a photolithography process (second mask process) .

Further, the source electrode 22 and the drain electrode 23, which are the second conductive film, are formed on the active layer 24 through the second mask process.

In addition, a data line 17 made of the second conductive film is formed in the data line region of the array substrate 10 through the second mask process, and a data line 17 is formed in the data pad portion of the array substrate 10, Thereby forming a data pad line 17p made of a conductive film.

At this time, the n + amorphous silicon thin film is formed on the active layer 24 and ohmic contact is made between the source / drain region of the active layer 24 and the source / drain electrodes 22 and 23 The ohmic-contact layer 25n is formed.

The first n + amorphous silicon thin film pattern 25 'and the first amorphous silicon thin film pattern 20', which are the n + amorphous silicon thin film and the amorphous silicon thin film, are formed under the data line 17, The second n + amorphous silicon thin film pattern 25 '' and the second amorphous silicon thin film pattern 20 'made of the n + amorphous silicon thin film and the amorphous silicon thin film are formed below the pad line 17p, respectively.

2C, a second insulating layer 15b is deposited on the entire surface of the array substrate 10 on which the source / drain electrodes 23, the data lines 17 and the data pad lines 17p are formed, A portion of the first insulating film 15a and the second insulating film 15b are removed through a photolithography process (a third mask process) to form the drain electrode 23, the data pad line 17p, A first contact hole 40a, a second contact hole 40b, and a third contact hole 40c exposing a part of the first contact hole 16p are formed.

Lastly, as shown in FIG. 2D, a third conductive film is deposited on the entire surface of the array substrate 10, and then selectively patterned using a photolithography process (fourth mask process) to form the first contact hole 40a A pixel electrode 18 electrically connected to the drain electrode 23 is formed while a common electrode 8 for generating a transverse electric field in the pixel region together with the pixel electrode 18 is formed.

The third conductive layer may be selectively patterned through the fourth mask process so that the data pad portion and the gate pad portion are electrically connected to the data pad line through the second contact hole 40b and the third contact hole 40c, A data pad electrode 27p and a gate pad electrode 26p electrically connected to the gate pad line 17p and the gate pad line 16p are formed.

As described above, the fabrication of the array substrate including the thin film transistor requires a plurality of photolithography processes. As described above, the half-tone mask is used to form the active layer and the data line, that is, The drain electrode and the data line are formed by a single mask process, so that an array substrate can be manufactured by a total of four mask processes.

However, the conventional four-mask liquid crystal display device has a structure in which the active layer and the data line are simultaneously patterned through two etching processes using a half-tone mask, and as shown in FIG. 3, The active layer, that is, the active tail, remains.

The active layer is made of a pure amorphous silicon thin film. At this time, the active layer under the data line is exposed to the lower backlight except the gate line, that is, the portion covered by the gate electrode and the gate line, A photocurrent is generated. At this time, due to the minute flickering of the backlight, the amorphous silicon thin film reacts finely and is repeatedly activated and deactivated, thereby causing a change in the photocurrent. Such a photocurrent component is coupled together with a signal flowing to neighboring pixel electrodes to distort the movement of the liquid crystal located on the pixel electrodes. As a result, wavy noise is generated on the screen of the liquid crystal display device in which a thin line of a wave pattern appears.

In addition, the active tail located below the data line protrudes a predetermined distance (~ 2 mu m) to both sides of the data line, so that the aperture ratio of the liquid crystal display device decreases as the aperture region of the pixel portion is eroded by the protruded distance.

Also, in the above-described general liquid crystal display device, a contact hole is required for connection between the drain electrode and the pixel electrode, and the aperture ratio is reduced due to the loss of transmittance according to the formation of the contact hole.

An object of the present invention is to provide a method of manufacturing a liquid crystal display device in which an array substrate of a liquid crystal display device is manufactured by four mask processes.

It is another object of the present invention to provide a method of manufacturing a liquid crystal display device in which an aperture ratio is improved because an active tail is not generated compared to a conventional four-mask structure.

Other objects and features of the present invention will be described in the following description of the invention and claims.

According to an aspect of the present invention, there is provided a method of manufacturing a liquid crystal display device, comprising: providing an array substrate divided into a pixel portion, a data pad portion, and a gate pad portion; Forming a gate electrode and a gate line made of a first conductive film in a pixel portion of the array substrate; Forming a first insulating layer on the entire surface of the array substrate where the gate electrode and the gate line are formed; Forming an active layer and an n + amorphous silicon thin film pattern on a pixel portion of the array substrate on which the first insulating film is formed; The second conductive layer and the third conductive layer are formed on the entire surface of the array substrate on which the active layer and the n + amorphous silicon thin film pattern are formed, and then the second conductive layer and the third conductive layer are selectively removed through the half- Forming a source electrode, a drain electrode, and a data line made of a third conductive film while forming a pixel electrode made of the second conductive film; Selectively removing the n + amorphous silicon thin film pattern on the active layer to form an ohmic contact layer; Forming a second insulating layer on the entire surface of the array substrate on which the ohmic-contact layer is formed; And attaching the array substrate and the color filter substrate together.

The method may further include forming a common line of the first conductive film on a pixel portion of the array substrate.

And forming a gate pad line made of the first conductive film on the gate pad portion of the array substrate.

The method may further include selectively removing the first insulating layer and the second insulating layer to expose the gate pad line.

And forming a common electrode made of the second conductive film on a pixel portion of the array substrate.

And forming a data pad line including the third conductive film on a data pad portion of the array substrate.

The method may further include selectively removing the second insulating layer to expose the data pad line.

The forming of the source electrode, the drain electrode, the data line, and the pixel electrode includes: forming a second conductive layer and a third conductive layer on the entire array substrate on which the active layer and the n + amorphous silicon thin film pattern are formed; Forming a first photoresist pattern to a sixth photoresist pattern on the array substrate using a half-tone mask; The second conductive film and the third conductive film formed under the first photosensitive film pattern to the sixth photosensitive film pattern are selectively removed to selectively remove a portion of the active layer from the source and drain electrodes, Forming a pixel electrode and a pixel electrode pattern including the second conductive film and the third conductive film in the pixel region; Selectively removing the n + amorphous silicon thin film on the active layer to form an ohmic contact layer made of the n + amorphous silicon thin film; The fourth photoresist pattern to the sixth photoresist pattern are removed and a part of the first photoresist pattern to the sixth photoresist pattern is partially removed by a thickness of the fourth photoresist pattern to the sixth photoresist pattern, Forming a photoresist pattern; And removing the third conductive layer formed under the seventh photoresist pattern to the ninth photoresist pattern using a mask to remove the pixel electrode pattern on the pixel electrode.

In this case, the third conductive film is formed of copper to form a source electrode, a drain electrode, and a data line, and the second conductive film is formed of ITO or IZO for use as a barrier metal of copper and for forming a pixel electrode .

At this time, a molybdenum or molybdenum alloy, aluminum or an aluminum alloy is deposited to a thickness of 50 Å to 500 Å on the array substrate before forming the second conductive layer, and the ohmic contact layer between the ITO and the active layer is used.

In this case, a data line made of the third conductive film is formed in the pixel portion.

At this time, the first conductive film pattern to the sixth conductive pattern pattern are masked to selectively remove portions of the second conductive film and the third conductive film formed under the source and drain electrodes, A source electrode pattern, a drain electrode pattern and a data line pattern made of a film are formed.

As described above, in the method of manufacturing a liquid crystal display device according to the present invention, the number of masks is reduced by using the ITO as the barrier metal of the data line, and the data line and the pixel electrode are formed as a single mask, Thereby providing a cost saving effect.

In addition, the method of manufacturing a liquid crystal display according to the present invention provides an effect that the drain electrode is directly connected to the pixel electrode without passing through the contact hole, and the aperture ratio is improved because the active tail does not occur compared to the conventional four mask structure.

1 is an exploded perspective view schematically showing a structure of a general liquid crystal display device.
FIGS. 2A to 2D are sectional views sequentially showing a manufacturing process of an array substrate of a general liquid crystal display device. FIG.
3 is a Scanning Electron Microscope (SEM) photograph showing a state where an active tail is generated under a source / drain electrode.
4 is a plan view schematically showing a part of an array substrate of a liquid crystal display device according to an embodiment of the present invention.
5 is a cross-sectional view schematically showing a part of an array substrate of a liquid crystal display device according to an embodiment of the present invention.
6A to 6D are plan views sequentially showing the manufacturing steps of the array substrate shown in FIG.
7A to 7D are cross-sectional views sequentially showing a manufacturing process of the array substrate shown in FIG. 5;
FIGS. 8A to 8F are cross-sectional views illustrating a third mask process according to an embodiment of the present invention shown in FIGS. 6C and 7C. FIG.

Hereinafter, preferred embodiments of a method of manufacturing a liquid crystal display device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 4 is a plan view schematically showing a part of an array substrate of a liquid crystal display device according to an embodiment of the present invention, and FIG. 5 is a cross-sectional view schematically showing a part of an array substrate of a liquid crystal display device according to an embodiment of the present invention.

In this case, one pixel including a pixel portion, a data pad portion, and a gate pad portion is shown for convenience of explanation. In an actual liquid crystal display device, N gate lines and M data lines cross each other and MxN pixels However, in order to simplify the description, one pixel is shown in the drawing.

In the drawings, a liquid crystal display device of a transverse electric field system in which a liquid crystal molecule is driven in a horizontal direction with respect to a substrate to improve a viewing angle to 170 degrees or more is described as an example, but the present invention is not limited thereto.

As shown in the figure, a gate line 116 and a data line 117 are vertically and horizontally arranged on the array substrate 110 to define a pixel region in the array substrate 110 of the embodiment of the present invention. A thin film transistor, which is a switching element, is formed in an intersection region of the gate line 116 and the data line 117. A common electrode 108 (not shown) for generating a transverse electric field to drive a liquid crystal And the pixel electrode 118 are alternately arranged.

The thin film transistor is electrically connected to the pixel electrode 118 through a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, and a pixel electrode line 118L. And the drain electrode 123 is formed. The thin film transistor includes an active layer 124 which forms a conductive channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121.

The source electrode 122, the drain electrode 123 and the data line 117 may be made of a low-resistance conductive material such as copper, and a barrier metal of ITO (Indium Tin A source electrode pattern 122 'and a drain electrode pattern 123' patterned in substantially the same manner as the source electrode 122, the drain electrode 123 and the data line 117, A pattern 117 'is formed.

On the active layer 124, an ohmic contact layer is formed to ohmic contact between the source / drain regions of the active layer 124 and the source / drain electrode patterns 122 'and 123' .

A part of the source electrode 122 and the source electrode pattern 122 'extend in one direction to form a part of the data line 117 and the data line pattern 117', and the drain electrode pattern 123 ' Is extended toward the pixel region to constitute the pixel electrode line 118L.

As described above, in the pixel region, the common electrode 108 and the pixel electrode 118 for generating a transverse electric field are alternately arranged.

At this time, a common line 108l arranged in a direction substantially parallel to the gate line 116 is formed above and below the pixel region, and the common line 108l is connected to the data line 117 And are connected to each other by left and right connection lines 108a arranged in a substantially parallel direction with respect to each other.

At this time, the plurality of common electrodes 108 are connected to the common electrode line 108L arranged in a direction substantially parallel to the common line 1081, and the common electrode line 108L is connected to the first insulating film 108L. And is electrically connected to the common line 1081 under the first contact hole 140a formed in the first contact hole 115a.

The plurality of pixel electrodes 118 are connected to the pixel electrode lines 118L arranged in a direction substantially parallel to the gate lines 116 and are electrically connected to the drain electrodes 123. [

The connection electrode 108a and the common line 1081 are made of the same opaque conductive material as the gate lines 121 and the gate lines 116. The common electrode 108, The common electrode line 108L and the pixel electrode line 118L may be made of the same transparent conductive material as the source electrode pattern 122 ', the drain electrode pattern 123' and the data line pattern 117 '.

A data pad line 117p and a gate pad line 116p connected to the data line 117 and the gate line 116 are formed in the edge region of the array substrate 110, And transmits a data signal and a scan signal applied from a circuit unit (not shown) to the data line 117 and the gate line 116, respectively.

That is, the data line 117 and the gate line 116 extend to the driving circuit portion and are connected to the corresponding data pad line 117p and the gate pad line 116p, The lines 116p receive a data signal and a scan signal from the driver circuit through the second contact hole 140b and the third contact hole 140c, respectively.

For reference, a gate pad line pattern 117p patterned in substantially the same shape as the gate pad line 117p is formed under the gate pad line 117p.

Here, a liquid crystal display device according to an embodiment of the present invention may be formed by forming an active layer and then using a half-tone mask or a diffraction mask (hereinafter, referred to as a half-tone mask includes a diffraction mask) The data lines, the pixel electrodes, and the common electrode are formed by the mask process of FIG. 4A, so that the array substrate can be manufactured by a total of four mask processes.

That is, the number of masks can be reduced by forming the data line, the pixel electrode, and the common electrode in one mask by using ITO as the barrier metal of the data line, and the drain electrode is connected to the pixel electrode without passing through the contact hole , The active tail is not generated as compared with the conventional four mask structure, and the aperture ratio is improved. This will be described in detail with reference to the following manufacturing method of the liquid crystal display device.

6A to 6D are plan views sequentially showing the manufacturing steps of the array substrate shown in FIG.

7A to 7D are cross-sectional views sequentially illustrating the manufacturing steps of the array substrate shown in FIG. 5. FIG. 7A to FIG. 7D illustrate a process of fabricating an array substrate of a pixel portion on the left side and an array substrate of a data pad portion and a gate pad portion, And the like.

6A and 7A, a gate electrode 121, a gate line 116, a common line 1081, and a connection line 108a (not shown) are formed in a pixel portion of an array substrate 110 made of a transparent insulating material such as glass, And a gate pad line 116p is formed in the gate pad portion of the array substrate 110. [

Here, the common line 108l is disposed substantially parallel to the gate line 116, and the connection line 108a is disposed substantially in a direction perpendicular to the gate line 116, And is connected to the light source 108l. However, the present invention is not limited to the arrangement of the common line 108l and the connection line 108a.

The gate electrode 121, the gate line 116, the common line 1081, the connection line 108a and the gate pad line 116p are formed by depositing a first conductive layer on the entire surface of the array substrate 110, And then selectively patterned through a lithography process (first mask process).

The first conductive layer may include at least one selected from the group consisting of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum Or a low-resistance opaque conductive material such as an alloy or the like. The first conductive layer may have a multi-layer structure in which two or more low-resistance conductive materials are stacked.

Next, as shown in FIGS. 6B and 7B, an array substrate (not shown) having the gate electrode 121, the gate line 116, the common line 1081, the connection line 108a and the gate pad line 116p 110, a first insulating layer 115a, an amorphous silicon thin film, and an n + amorphous silicon thin film are formed.

Thereafter, the amorphous silicon thin film and the n + amorphous silicon thin film are selectively removed through a photolithography process (second mask process) to form an active layer 124 made of the amorphous silicon thin film in the pixel portion of the array substrate 110 do.

At this time, an n + amorphous silicon thin film pattern 125 formed of the n + amorphous silicon thin film and patterned substantially in the same manner as the active layer 124 is formed on the active layer 124.

If a half-tone mask is used in the second mask process, a first contact hole 140a exposing a part of the common line 1081 is formed by selectively removing a part of the first insulating film 115a You may.

Next, as shown in FIGS. 6C and 7C, a second conductive film and a third conductive film are formed on the entire surface of the array substrate 110 on which the active layer 124 and the n + amorphous silicon thin film pattern are formed.

Here, the third conductive layer may be formed of a low-resistance opaque conductive material such as copper to form a source electrode, a drain electrode, and a data line, and the second conductive layer may be used as a barrier metal of copper, And may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form an electrode.

Thereafter, the n + amorphous silicon thin film, the second conductive film, and the third conductive film are selectively removed through a photolithography process (a third mask process) to form a source electrode And a plurality of pixel electrodes 118 and a common electrode 108 of the second conductive film are formed in the pixel region.

In this case, a data line 117 made of the third conductive film is formed in the data line region of the array substrate 110 through the third mask process, Thereby forming a data pad line 117p made of a conductive film.

The second conductive film is formed under the source electrode 122, the drain electrode 123 and the data line 117 through the third mask process and is electrically connected to the source electrode 122 and the drain electrode 123 The source electrode pattern 122 'and the drain electrode pattern 123' and the data line pattern 117 ', which are patterned in substantially the same manner as the data line 117 and the data line 117, are formed.

At this time, on the active layer 124, an n + amorphous silicon thin film is formed on the active layer 124, and an ohmic contact layer 123 is formed between the source / drain region of the active layer 124 and the source / (125n) is formed.

A part of the source electrode 122 and the source electrode pattern 122 'extend in one direction to form a part of the data line 117 and the data line pattern 117' (108) are connected to a common electrode line (108L) arranged in a direction substantially parallel to the common line (108l), and the plurality of pixel electrodes (118) are substantially parallel to the gate line And is electrically connected to the drain electrode 123 by being connected to the pixel electrode line 118L arranged in one direction.

At this time, the source / drain electrodes 122 and 123, the source / drain electrode patterns 122 'and 123', the data lines 117, the data line patterns 117 ', the data pad lines 117p, The pattern 117p ', the pixel electrode 118, the pixel electrode line 118L, the common electrode 108 and the common electrode line 108L can be formed through a single mask process by using half-tone exposure , Which will be described in detail with reference to the following drawings.

8A to 8F are cross-sectional views illustrating a third mask process according to an embodiment of the present invention shown in FIGS. 6C and 7C.

The second conductive layer 120 and the third conductive layer 130 are formed on the entire surface of the array substrate 110 on which the active layer 124 and the n + amorphous silicon thin film pattern 125 are formed, as shown in FIG. 8A .

In this case, as described above, the third conductive layer 130 may be formed of a low-resistance opaque conductive material such as copper to form a source electrode, a drain electrode, and a data line, And may be formed of a transparent conductive material such as ITO or IZO in order to use the barrier metal of copper and to form the pixel electrode and the common electrode.

At this time, a molybdenum or molybdenum alloy, aluminum or an aluminum alloy is deposited to a thickness of 50 Å to 500 Å on the array substrate 110 before the second conductive layer 120 is formed, thereby forming ohmic- It can also be used as a contact layer.

8B, a photosensitive film 170 made of a photosensitive material such as a photoresist is formed on the array substrate 110 on which the third conductive film 130 is formed. Then, - selectively irradiates light to the photoresist layer 170 through the tone mask 180. [

At this time, the half-tone mask 180 is provided with a first transmission region I through which all the irradiated light is transmitted, a second transmission region II through which only a part of light is transmitted and a portion is blocked, And only the light transmitted through the half-tone mask 180 is irradiated on the photoresist layer 170.

Then, after the photoresist layer 170 exposed through the half-tone mask 180 is developed, light is irradiated through the blocking region III and the second transmissive region II, as shown in FIG. 8C. The first photosensitive film pattern 170a to the sixth photosensitive film pattern 170f having a predetermined thickness remain in the area where all the light is blocked or partially blocked and the photosensitive film is completely removed in the first transmission area I The surface of the third conductive layer 130 is exposed.

The first photoresist pattern 170a to the third photoresist pattern 170c formed in the blocking region III may include a fourth photoresist pattern 170d through a sixth photoresist pattern 170f formed through the second transmissive area II, . Further, the photoresist layer is completely removed in the region where the light is completely transmitted through the first transmissive region I because the positive type photoresist is used. The present invention is not limited to this, It may be used.

Next, as shown in FIG. 8D, using the first photoresist pattern 170a to the sixth photoresist pattern 170f formed as described above as a mask, a second conductive film and a part of the third conductive film The source electrode 122 and the drain electrode 123 of the third conductive layer are formed on the active layer 124 and the plurality of second conductive layers The pixel electrode 118, the common electrode 108, and the pixel electrode line 118L are formed.

A data line 117 made of the third conductive film is formed on the data line area of the array substrate 110 and a data pad line made of the third conductive film is formed on the data pad part of the array substrate 110. [ (117p) is formed.

At this time, the second conductive layer is formed under the source electrode 122, the drain electrode 123, the data line 117, and the data pad line 117p, and the source electrode 122 and the drain electrode 123 A source electrode pattern 122 ', a drain electrode pattern 123', a data line pattern 117 ', and a data pad line pattern 117' that are patterned in substantially the same pattern as the data line 117, the data line 117, (117p ') is formed.

The third conductive film is formed on the pixel electrode 118 and the common electrode 108 and the pixel electrode line 118L and is electrically connected to the common electrode 108 and the pixel electrode line The pixel electrode pattern 130 ', the common electrode pattern 130', and the pixel electrode line pattern 130 '' are formed in substantially the same pattern as the pixel electrode pattern 118 '.

Thereafter, the n + amorphous silicon thin film on the active layer 124, that is, the upper part of the back channel is selectively removed using the first photoresist pattern 170a to the sixth photoresist pattern 170f as a mask to form the n + amorphous silicon thin film Thereby forming the ohmic contact layer 125n.

When the ashing process for removing a part of the thickness of the first to sixth photoresist patterns 170a to 170f is performed, as shown in FIG. 8E, The photoresist pattern to the sixth photoresist pattern are completely removed.

In this case, the first to third photoresist patterns to the seventh photoresist pattern 170a 'to the ninth photoresist pattern 170c', which are removed by the thicknesses of the fourth to sixth photoresist patterns, (III). ≪ / RTI >

Then, as shown in FIG. 8F, using the seventh photosensitive film pattern 170a 'to the ninth photosensitive film pattern 170c' as masks, a part of the third conductive film formed at the lower part thereof is selectively removed, The pixel electrode pattern, the common electrode pattern, and the pixel electrode line pattern on the pixel electrode 118, the common electrode 108, and the pixel electrode line 118L are removed.

As shown in FIGS. 6D and 7D, a second insulating layer 115b is formed on the entire surface of the array substrate 110. FIG.

At this time, the second insulating film (115b) may be formed of an organic insulating film such as formed of an inorganic insulating film or an acrylic photo, such as a silicon nitride film (SiNx), silicon oxide (SiO _2).

Thereafter, the first insulating film 115a and the second insulating film 115b are selectively removed through a photolithography process (a fourth mask process) to form the data pad portion and the gate pad portion of the array substrate 110, respectively, A second contact hole 140b and a third contact hole 140c for exposing a part of the pad line 117p and the gate pad line 116p to the outside are formed.

The array substrate of the present invention having the above-described structure according to the present invention is adhered to the color filter substrate by a sealant formed on the outer periphery of the image display area. In this case, the color filter substrate is provided with color A filter is formed.

At this time, the color filter substrate and the array substrate are bonded together through a covalent key formed on the color filter substrate or the array substrate.

Although the amorphous silicon thin film transistor using the amorphous silicon thin film as the active layer is described as an example of the liquid crystal display device of the embodiment of the present invention, the present invention is not limited to this, And is also applied to a polycrystalline silicon thin film transistor.

In addition, although the liquid crystal display device of the present invention has been described as an example of a liquid crystal display device of a transverse electric field system, the present invention is not limited thereto. The present invention can be applied to a liquid crystal display device of a twisted nematic type or a liquid crystal display device of vertical orientation Vertical Alignment (VA) type liquid crystal display device.

In addition, the present invention can be applied not only to a liquid crystal display device but also to other display devices manufactured using thin film transistors, for example, organic electroluminescent display devices in which organic light emitting diodes (OLEDs) have.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Accordingly, the invention is not to be determined by the embodiments described, but should be determined by equivalents to the appended claims and the claims

108: common electrode 108l: common line
108L: common electrode line 110: array substrate
116: gate line 117: data line
117 ': Data line pattern 118: Pixel electrode
118L: pixel electrode line 121: gate electrode
122: source electrode 122 ': source electrode pattern
123: drain electrode 123 ': drain electrode pattern

Claims (12)

Providing an array substrate divided into a pixel portion, a data pad portion, and a gate pad portion;
Forming a gate electrode and a gate line made of a first conductive film in a pixel portion of the array substrate;
Forming a first insulating layer on the entire surface of the array substrate where the gate electrode and the gate line are formed;
Forming an active layer and an n + amorphous silicon thin film pattern on a pixel portion of the array substrate on which the first insulating film is formed;
The second conductive layer and the third conductive layer are formed on the entire surface of the array substrate on which the active layer and the n + amorphous silicon thin film pattern are formed, and then the second conductive layer and the third conductive layer are selectively removed through the half- A data electrode line formed of the first conductive film, a source electrode and a drain electrode of the third conductive film, a data line, and a pixel electrode made of the second conductive film, Forming a data pad line including the third conductive film;
Selectively removing the n + amorphous silicon thin film pattern on the active layer to form an ohmic contact layer;
Forming a second insulating layer on the entire surface of the array substrate on which the ohmic-contact layer is formed; And
And bonding the array substrate and the color filter substrate,
Wherein a side surface of the data pad line pattern and a side surface of a data pad line disposed on the data pad line pattern are in contact with the second insulating layer. The manufacturing method of a liquid crystal display device according to claim 1, further comprising forming a common line made of the first conductive film on a pixel portion of the array substrate. The method of claim 1, further comprising forming a gate pad line made of the first conductive film on a gate pad portion of the array substrate. The method of claim 3, further comprising selectively removing the first insulating layer and the second insulating layer to expose the gate pad line. The manufacturing method of a liquid crystal display device according to claim 1, further comprising forming a common electrode made of the second conductive film on a pixel portion of the array substrate. delete The method of claim 1, further comprising selectively removing the second insulating layer to expose the data pad line. The method of claim 1, wherein forming the source electrode, the drain electrode, the data line, and the pixel electrode comprises:
Forming a second conductive layer and a third conductive layer on the entire array substrate on which the active layer and the n + amorphous silicon thin film pattern are formed;
Forming a first photoresist pattern to a sixth photoresist pattern on the array substrate using a half-tone mask;
The second conductive film and the third conductive film formed under the first photosensitive film pattern to the sixth photosensitive film pattern are selectively removed to selectively remove a portion of the active layer from the source and drain electrodes, Forming a pixel electrode and a pixel electrode pattern including the second conductive film and the third conductive film in the pixel region;
Selectively removing the n + amorphous silicon thin film on the active layer to form an ohmic contact layer made of the n + amorphous silicon thin film;
The fourth photoresist pattern to the sixth photoresist pattern are removed and a part of the first photoresist pattern to the sixth photoresist pattern is partially removed by a thickness of the fourth photoresist pattern to the sixth photoresist pattern, Forming a photoresist pattern; And
And removing the third conductive layer formed under the seventh photoresist pattern to the ninth photoresist pattern using a mask to remove the pixel electrode pattern on the pixel electrode. The method of claim 1 or claim 8, wherein the third conductive layer is formed of copper to form a source electrode, a drain electrode, and a data line, the second conductive layer is used as a barrier metal of copper, Wherein the first electrode is formed of ITO or IZO. The liquid crystal display according to claim 9, wherein a molybdenum or molybdenum alloy, aluminum or aluminum alloy is deposited to a thickness of 50 Å to 500 Å on the array substrate to form an ohmic contact layer between the ITO and the active layer, ≪ / RTI > delete The method of claim 8, further comprising selectively removing portions of the second conductive layer and the third conductive layer formed under the first to sixth photoresist patterns to mask the source and drain electrodes And forming a source electrode pattern, a drain electrode pattern, and a data line pattern made of the second conductive film.

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