KR101843181B1 - Transistor Substrate For Flat Panel Display Device and Method For Manufacturing The Same - Google Patents

Abstract

The present invention relates to a method of manufacturing a thin film transistor substrate for a flat panel display and a thin film transistor by the method. A thin film transistor substrate for a flat panel display according to the present invention comprises: a substrate divided into a display region and a non-display region; A semiconductor layer formed in the display region on the substrate; A gate insulating film covering the semiconductor layer; A gate element formed on the gate insulating film; An insulating film covering the gate element; A source-drain element formed on the insulating film; A planarization film covering the display region and the source-drain element formed in the non-display region; An anode electrode formed on the planarization layer and connected to the source-drain element; And a connection terminal formed on the planarization film and connecting two source-drain elements spaced apart from each other in the non-display region. In the thin film transistor substrate according to the present invention, the source-drain metal layer, which is exposed by omitting the protective film, is covered with the planarizing film, thereby preventing damage caused by the etchant and the developer.

Description

[0001] The present invention relates to a thin film transistor substrate for a flat panel display,

The present invention relates to a method of manufacturing a thin film transistor substrate for a flat panel display and a thin film transistor by the method. In particular, the present invention relates to a method of manufacturing a thin film transistor substrate for a flat panel display in which the number of mask processes is reduced by removing a protective film, and a thin film transistor by the method.

2. Description of the Related Art Recently, various flat panel display devices capable of reducing weight and volume, which are disadvantages of cathode ray tubes (CRTs), have been developed. Such flat panel display devices include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an electroluminescence device (EL) have.

Flat panel display devices include a thin film transistor substrate having switching elements arranged in a matrix array to realize active driving. FIG. 1 is a plan view showing a structure of a thin film transistor substrate used in an organic light emitting diode (OLED) according to a related art. FIG. 2 is a cross-sectional view taken along a cutting line I-I 'in FIG. 1, illustrating a structure of a conventional thin film transistor substrate for an OLED display.

1 and 2, a thin film transistor substrate for an organic light emitting display includes a switching TFT ST, a driving TFT DT connected to the switching TFT, an anode electrode ANO of the organic light emitting diode connected to the driving TFT DT, . Although not shown in the drawings, the organic materials and the cathode electrodes formed in the organic light emitting diode deposition process are stacked on the anode electrode ANO.

On the glass substrate SUB, the switching TFT ST is formed at a position where the gate line GL and the data line DL cross each other. The switching TFT ST functions to select a pixel. The switching TFT ST includes a gate electrode SG, a semiconductor layer SA, a source electrode SS and a drain electrode SD which branch off from the gate line GL. The driving TFT DT serves to drive the anode electrode ANO of the pixel selected by the switching TFT ST. The driving TFT DT includes a gate electrode DG connected to the drain electrode SD of the switching TFT ST, a source electrode DS connected to the semiconductor layer DA, the driving current transfer wiring VDD, (DD). The drain electrode DD of the driving TFT DT is connected to the anode electrode ANO of the organic light emitting diode.

The thin film transistor shown in FIG. 2 has a top gate structure. The semiconductor layer DA of the switching TFT ST and the semiconductor layer DA of the driving TFT DT are formed on the substrate SUB first and the gate electrodes SG , DG are formed overlapping with the center portions of the semiconductor layers SA, DA. On both sides of the semiconductor layers SA and DA, source electrodes SS and DS and drain electrodes SD and DD are connected through a contact hole. The source electrodes SS and DS and the drain electrodes SD and DD are formed on the insulating film IN covering the gate electrodes SG and DG.

A gate pad GP formed at one end of each gate line GL and a data pad DP formed at one end of each data line DL are formed in the outer periphery of the display region where the pixel region is disposed, A driving current pad VDP formed at one end of the current transfer wiring VDD is disposed. The protective film PAS is entirely coated on the substrate SUB on which the switching TFT ST and the driving TFT DT are formed. A contact hole exposing the gate pad GP, the data pad DP, the driving current pad VDP, and the drain electrode DD of the driving TFT DT is formed. Then, a flattening film PL is applied onto the display area of the substrate SUB. The planarization layer PL serves to uniformize the roughness of the substrate surface in order to apply the organic material constituting the organic light emitting diode in a smooth planar state.

An anode electrode ANO is formed on the planarizing film PL in contact with the drain electrode DD of the driving TFT DT through the contact hole. The gate pad GP, the data pad DP, and the gate formed on the driving current pad VDP, which are exposed through the contact hole formed in the passivation film PAS, are formed on the outer periphery of the display region where the planarization film PL is not formed. A pad terminal GPT, a data pad terminal DPT, and a driving current pad terminal VDPT, respectively. The bank BA is formed on the substrate SUB except for the pixel region in the display region. Then, a spacer SP is further formed on a part of the bank BA.

In order to manufacture a thin film transistor substrate having such a structure, at least 9 mask processes are required. If the number of mask processes is large, the manufacturing process is lengthened, the manufacturing cost is increased, and the production yield is lowered due to errors due to mask alignment. There is a need for a method of manufacturing a thin film transistor substrate having the same performance by simplifying the mask process and a thin film transistor substrate by the method.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a thin film transistor substrate in which a protective film is removed to reduce the number of mask processes, and a thin film transistor substrate by the method. It is another object of the present invention to provide a thin film transistor substrate and a method of manufacturing the thin film transistor substrate, which prevent damage to the element layer which is protected by the protective film even when the protective film is removed.

According to an aspect of the present invention, there is provided a thin film transistor substrate for a flat panel display comprising: a substrate divided into a display region and a non-display region; A semiconductor layer formed in the display region on the substrate; A gate insulating film covering the semiconductor layer; A gate element formed on the gate insulating film; An insulating film covering the gate element; A source-drain element formed on the insulating film; A planarization film covering the display region and the source-drain element formed in the non-display region; An anode electrode formed on the planarization layer and connected to the source-drain element; And a connection terminal formed on the planarization film and connecting two source-drain elements spaced apart from each other in the non-display region.

Wherein the source-drain element comprises: a source electrode and a drain electrode respectively contacting both sides of the semiconductor layer; And a data line connected to the source electrode and extending in the longitudinal direction of the substrate, the gate element including: a gate electrode overlapping the semiconductor layer; A gate wiring connected to the gate electrode and extending in a lateral direction of the substrate; A gate pad formed on one end of the gate wiring; A first signal pad arranged in parallel with the gate pad and a first connection wiring extended from the first signal pad; A data pad disposed at one end of the data line; And a second signal pad arranged in parallel with the data pad.

A first contact hole formed in the insulating film to expose one end of the first connection wiring; A second contact hole formed in the insulating film to expose one end of the second signal pad; A second connection wiring connected to the first connection wiring through the first contact hole as a part of the source-drain element; A third connection line connected to the second signal pad through the second contact hole as a part of the source-drain element; And further comprising connection contact holes formed in the planarization layer to expose upper surfaces of mutually facing surfaces of the second connection wiring and the third connection wiring, respectively, and the second connection wiring and the third connection wiring, And is connected by the connection terminal.

And a data contact hole formed in the insulating layer to expose one end of the data pad, wherein the data line is connected to the data pad via the data contact hole.

A bank layer exposing a part of the anode electrode on the planarization film on which an anode electrode is formed; And a spacer formed at a predetermined height above the bank layer.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate for a flat panel display, including: a first mask process for forming a semiconductor layer on a substrate; A second masking step of continuously depositing a gate insulating layer and a gate metal layer on the semiconductor layer and patterning the gate metal layer to form a gate element; A third masking step of applying an insulating film on the gate element and patterning the insulating film and the gate insulating film to expose both sides of the semiconductor layer and a part of the gate element; A fourth mask process of applying a source-drain metal layer over the insulating layer and patterning to form a source-drain element in contact with the exposed gate element; A fifth masking step of applying a planarization film over the source-drain element and patterning the planarization film to cover the entire source-drain and expose a part of the upper surface of the source-drain element; And a sixth mask process of applying a transparent conductive material on the planarization film and patterning the anode electrode and the connection terminal to contact a part of the exposed source-drain element.

Wherein the source-drain element formed in the fourth masking step comprises: a source electrode and a drain electrode which are in contact with both exposed sides of the semiconductor layer; And a data line connected to the source electrode and extending in the longitudinal direction of the substrate, wherein the gate element formed in the second mask process includes: a gate electrode overlapping the semiconductor layer; A gate wiring connected to the gate electrode and extending in a lateral direction of the substrate; A gate pad formed on one end of the gate wiring; A first signal pad arranged in parallel with the gate pad and a first connection wiring extended from the first signal pad; A data pad disposed at one end of the data line; And a second signal pad arranged in parallel with the data pad.

In the third masking step, a first contact hole is formed in the insulating film so as to expose one end of the first connection wiring line. And forming a second contact hole in the insulating film to expose one end of the second signal pad; A second connection wiring connected to the first connection wiring through the first contact hole as a part of the source-drain element in the fourth mask process; And forming a third connection wiring as a part of the source-drain element, the third connection wiring being connected to the second signal pad through the second contact hole; Further forming connection contact holes in the planarization film to expose upper surfaces of mutually facing one side surfaces of the second connection wiring and the third connection wiring in the fifth mask process; And the second connection wiring and the third connection wiring are connected by the connection terminal in the sixth mask process.

Wherein in the third mask process, a data contact hole is further formed in the insulating film so as to expose one end of the data pad, and in the fourth mask process, the data line is connected to the data pad through the data contact hole .

A bank layer exposing a part of the anode electrode on the planarizing film on which the anode electrode is formed; and a seventh masking step of forming a spacer having a predetermined height on the bank layer.

The method for manufacturing a thin film transistor substrate for a flat panel display according to the present invention does not use a protective film. Therefore, a mask process for patterning the contact holes formed in the protective film is not required. As a result, the manufacturing process is simple, the cost is low, and the decrease in manufacturing yield due to the mask error can be reduced. In addition, the thin film transistor substrate for a flat panel display according to the present invention has a structure in which a source-drain metal layer exposed by omitting a protective film is covered with a flattening film. Therefore, it is possible to prevent the source-drain metal from being damaged by the etchant used in the planarization film pattern process, the anode electrode pattern process, and the bank and spacer pattern process.

1 is a plan view showing a structure of a thin film transistor substrate used in an organic light emitting display according to a related art.
FIG. 2 is a cross-sectional view taken along a cutting line I-I 'in FIG. 1, showing a structure of a conventional thin film transistor substrate for an OLED display.
3 is a plan view showing a structure of a thin film transistor substrate used in an organic light emitting diode display according to a first embodiment of the present invention.
FIG. 4 is a cross-sectional view cut along the cutting line IV-IV 'in FIG. 3, showing a structure of the thin film transistor substrate according to the first embodiment;
FIG. 5 is a cross-sectional view cut along a perforated line V-V 'in FIG. 3, showing a connection wiring structure of a gate metal layer and a source metal layer in the thin film transistor substrate according to the first embodiment;
6 is a plan view showing a structure of a thin film transistor substrate used in an organic light emitting diode display according to a second embodiment of the present invention.
FIG. 7 is a cross-sectional view cut along the perforated lines VII-VII 'in FIG. 6, showing a connection wiring structure of a gate metal layer and a source metal layer in the thin film transistor substrate according to the second embodiment;
8 is a plan view showing a structure of a thin film transistor substrate used in an organic light emitting diode display according to a third embodiment of the present invention.
FIG. 9 is a cross-sectional view cut along the perforated line VIIII-VIIII 'in FIG. 8, showing a connection wiring structure of the gate metal layer and the source metal layer in the thin film transistor substrate according to the third embodiment.
FIGS. 10A to 10G are cross-sectional views showing a method of manufacturing the thin film transistor substrate according to the third embodiment, as cross sections taken along the perforated line X-X 'in FIG.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings 3 to 10g. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known units relating to the present invention will be omitted when it is determined that a detailed description of the configuration may unnecessarily obscure the gist of the present invention.

3 is a plan view showing a structure of a thin film transistor substrate used in an organic light emitting diode display according to a first embodiment of the present invention. FIG. 4 is a cross-sectional view cut along the cutting line IV-IV 'in FIG. 3, illustrating the structure of the thin film transistor substrate according to the first embodiment. Referring to FIGS. 3 and 4, the thin film transistor substrate for an organic light emitting display according to the present invention has much the same structure as a conventional thin film transistor substrate. It does not include the protective film PAS of FIG. 2 covering the switching TFT ST and the driving TFT DT, if there is a difference.

According to the thin film transistor substrate for an organic light emitting display according to the first embodiment of the present invention, a portion where the gate pad GP and the data pad DP are formed in the non-display region except for the display region is later mounted A problem may arise in a portion where the gate circuit portion (GIP) and the driver IC (DIC) to be mounted are to be mounted. In this embodiment, a non-display area which is not considered in the prior art will be described in detail intensively. In the case of a thin film transistor substrate for mobile, the data driver IC may use an integrated driver IC including both a timing controller and a DC-DC converter. In this case, it further includes connection wirings (SL1, SL2, SL3) for transferring a clock signal, a gate enable signal, a gate high signal and a gate low signal from the driver IC (DIC) to the gate circuit portion (GIP).

3 shows a case where a first signal pad SP1 is formed at the outermost part of the gate pad GP and a second signal pad SP2 is formed at the outermost part of the data pad DP. In practice, although a greater number of signal pads can be formed, this embodiment will be described with a minimum number. The first signal pad SP1 is formed like the gate pad GP and thus is formed on the gate insulating film GI and covered with the insulating film IN. The second signal pad SP2 is formed when the data pad DP is formed, and therefore, the second signal pad SP2 is formed on the insulating film IN. That is, the first signal pad SP1 and the second signal pad SP2 are formed on different layers, and an insulating film is interposed therebetween. Therefore, in order to connect the first signal pad SP1 and the second signal pad SP2, the first signal pad SP1 and the second signal pad SP2 are connected by the connection wiring SL2 through the contact hole passing through the insulating film IN covering the first signal pad SP1 .

In the first embodiment, the first connection wiring SL1 formed by extending the same material as the first signal pad SP1, the second connection wiring SL1 formed on the insulating film IN, A second connection wiring SL2 connected to the first connection wiring SL1 through a hole and a third connection wiring SL3 extended from the same material as the second signal pad SP2 and formed on the insulating film IN, And a connection terminal SLC for connecting the second connection wiring SL2 and the third connection wiring SL3 will be described. FIG. 5 is a cross-sectional view cut along a perforated line V-V 'in FIG. 3, showing a connection wiring structure of a gate metal layer and a source metal layer in the thin film transistor substrate according to the first embodiment.

In the first embodiment, since the protective film covering the entire display area and the non-display area of the substrate SUB is omitted, the source-drain metal layer formed in the same layer as the data pad DP is exposed in the non-display area . 3 and 5, a gate insulating film GI is coated on a substrate SUB, and a first connection wiring SL1 which is a gate metal layer is formed on the gate insulating film GI. The first connection wiring SL1 is covered with the insulating film IN and is exposed only through the contact hole formed at one end. A second connection wiring SL2 and a third connection wiring SL3, which are source-drain metal layers, are formed on the insulating film IN. The second connection interconnection line SL2 contacts the first connection interconnection line SL1 exposed through the contact hole. The third connection wiring SL3 is formed as one body with the second signal pad SP2, as shown in Fig. The second connection interconnection SL2 and the third connection interconnection SL3 are connected to each other through a connection terminal SLC which is formed when the anode electrode ANO is formed.

However, in the case where the source-drain metal layer includes a metal material having high resistance to the etching solution, no serious problem arises. However, problems may arise if the etchant, such as aluminum or copper, or the developer contains a vulnerable metal to reduce the resistance. The enlarged drawing of Fig. 5 shows a case where a problem occurs.

For example, the source-drain metal layer may comprise a metal layer stacked with titanium (Ti) / aluminum (Al) / titanium (Ti). At this time, the aluminum (Al) layer is exposed in the patterned cross section of the second connection interconnection line SL2 and the third connection interconnection line SL3. Then, the aluminum (Al) layer is damaged by the etching solution or the developing solution used in the subsequent process of forming the thin film elements. As a result, the side profile of the second connection interconnection line SL2 or the third connection interconnection line SL3 is not smooth and can be eroded into a cavernous shape. As a result, disconnection occurs at the connection terminal SLC connecting the second connection interconnection SL2 and the third connection interconnection SL3.

The second embodiment provides a method and structure for solving the problem of disconnection occurring in the connection of the gate metal layer and the source-drain metal layer by damaging the exposed source-drain metal layer by omitting the protective film. 6 is a plan view showing a structure of a thin film transistor substrate used in an OLED display according to a second embodiment of the present invention. FIG. 7 is a cross-sectional view cut along the perforated lines VII-VII 'in FIG. 6, showing a connection wiring structure of a gate metal layer and a source metal layer in the thin film transistor substrate according to the second embodiment. The cross section of the display region portion in the second embodiment is the same as the cross section shown in Fig. 4, and a detailed description thereof will be omitted.

Referring to FIGS. 6 and 7, in the second embodiment, since the protective film is omitted, the planarizing film PL formed next to the protective film is used to cover the exposed source-drain metal layer. 6 and 7, in addition to the planarization film PL covering the display area, the second connection wiring line (SL2) and the second connection wiring line SL3 are formed in a portion where the second connection wiring SL2 and the third connection wiring SL3 face each other The planarizing film PL may be patterned in an island shape so as to cover the pattern end portions of the first connection wiring SL2 and the third connection wiring SL3.

However, the etchant or developer may penetrate into the portion indicated by? In Fig. Further, after patterning the data line (DL) or the data pad (DP) extending outside the display area, the pattern section remains exposed. The aluminum layer (Al) exposed in the cross section of the pattern is highly likely to be eroded into an etching solution or a developing solution in a subsequent process. In this case, a peeling-off phenomenon occurs in which the exposed source-drain metal layer is corroded and peeled, which leads to substrate damage.

The third embodiment proposes the most preferable method and structure for protecting the exposed source-drain metal layer that occurs in the first and second embodiments described above. 8 is a plan view showing the structure of a thin film transistor substrate used in an organic light emitting diode display according to a third embodiment of the present invention. FIG. 9 is a cross-sectional view cut along the perforated line VIIII-VIIII 'in FIG. 8, showing a connection wiring structure of a gate metal layer and a source metal layer in the thin film transistor substrate according to the third embodiment.

Referring to FIGS. 8 and 9, the thin film transistor substrate for an organic light emitting display according to the third embodiment of the present invention has much the same structure as the thin film transistor substrate according to the other embodiments and the conventional art. Therefore, the description of the same portions will be omitted. If there is a difference, there is a difference in the formation range of the planarizing film (PL) and the structure of the connection wiring. Hereinafter, this difference will be mainly described.

The third embodiment is characterized in that the source-drain metal layer that is exposed is completely covered with the planarizing film PL. To this end, the data pad DP and the second signal pad SP2 are formed of the same material in the same layer as the gate metal layer, such as the gate pad GP and the first signal pad SP1. The data line DL formed of the source-drain metal layer is connected to the data pad DP through the data contact hole 400 formed in the insulating film IN covering the gate metal layer. Similarly, the second connection interconnection SL2 is in contact with the first connection interconnection SL1 through the first contact hole 100 formed in the insulation film IN, and the third connection interconnection SL3 is in contact with the insulation interconnection IN, And is connected to the data pad DP through the second contact hole 200 formed in the second contact hole.

The data line DL, the second connection interconnection SL2 and the third connection interconnection SL3 are formed of a source-drain metal layer. Accordingly, the patterned cross section is exposed as it is with the lamination of titanium (TI) / aluminum (Al) / titanium (TI). At this time, in order to protect the exposed aluminum (Al) layer, a planarization film PL is formed on the substrate SUB on which the display region and the source-drain metal layer are disposed. As a result, the source-drain metal layer is not exposed, and the planarizing film PL covers the structure.

Thereafter, to connect the second connection interconnection line SL2 and the third connection interconnection line SL3, the planarization film PL is patterned to form the connection interconnection contact holes 301 and 303. Then, When the anode electrode ANO is formed, a connection terminal SLC for electrically connecting the second connection wiring SL2 and the third connection wiring SL3 through the connection wiring contact holes 301 and 303 .

Hereinafter, a method of manufacturing the thin film transistor substrate according to the third embodiment will be described in more detail with reference to FIGS. 10A to 10G. FIGS. 10A to 10G are cross-sectional views showing a method of manufacturing the thin film transistor substrate according to the third embodiment, as cross sections taken along the perforated line X-X 'in FIG.

A semiconductor material is deposited on the transparent substrate (SUB). The semiconductor layer DA of the switching TFT ST and the semiconductor layer DA of the driving TFT DT are formed by patterning in the first masking process. Although not shown in the figure, a buffer layer may be further formed on the transparent substrate SUB. (Fig. 10A)

A gate insulating film (GI) is entirely deposited on the semiconductor layers (SA, DA). A gate metal material is continuously deposited on the gate insulating film (GI). A gate wiring GL extending in the lateral direction in the substrate SUB and a gate pad GP connected to one end of the gate wiring pattern and a gate electrode SG of the switching TFT ST, The gate electrode DG of the driving TFT DT, and the data pad DP are formed. The gate electrode SG of the switching TFT ST is arranged so as to overlap the central portion of the semiconductor layer SA of the switching TFT ST. The gate electrode DG of the driving TFT DT is arranged so as to overlap the central portion of the semiconductor layer DA of the driving TFT DT. (Fig. 10B)

An insulating material IN is formed by depositing an insulating material on the entire surface of the substrate SUB including the gate elements formed by patterning the gate metal material. The insulating film IN and the gate insulating film GI are patterned by the third masking process so that the source contact holes SSH and the drain electrodes ST of the switching TFT ST for exposing both side portions of the semiconductor layer SA of the switching TFT ST Thereby forming a contact hole SDH. A source contact hole DSH and a drain contact hole DDH of the driver TFT DT exposing both side portions of the semiconductor layer DA of the drive TFT DT are formed. A gate contact hole GH exposing one side of the gate electrode DG of the driving TFT DT and a data contact hole 400 exposing one end of the data pad GP are formed. At this time, one end of the exposed data pad GP may not have a pad shape and may have the same shape as the data line DL. A gate pad contact hole GPH and a data pad contact hole DPH are formed to expose the gate pad GP and the central portion of the data pad DP. (Fig. 10C)

Drain metal material over the insulating film IN. The source electrode SS and the drain electrode SD of the switching TFT ST which are in contact with the semiconductor layer SA of the switching TFT ST and are opposed to each other and the source electrode SS and the drain electrode SD of the driving TFT DT The source electrode DS and the drain electrode DD of the driver TFT DT which are in contact with the semiconductor layer DA and opposed to each other are formed. At the same time, a driving current wiring VDD connecting the data line SL connecting the source electrode SS of the switching TFT ST and the source electrode DS of the driving TFT DT is formed. Here, the drain electrode SD of the switching TFT ST is connected to the gate electrode DG of the driving TFT DT through the gate contact hole GH. The data line DL is connected to one end of the data pad GP through the data contact hole 400. Meanwhile, the gate pad contact hole GPH and the data pad contact hole DPH maintain the exposed state of the gate pad GP and the central portion of the data pad DP. (Fig. 10D)

A planarization material PL is formed on the substrate SUB including the source-drain elements formed by patterning the source-drain metal material by applying the planarization material over the substrate SUB. The planarization film PL is patterned by a fifth mask process to form a drain contact hole DH exposing a part of the drain electrode DD of the driving TFT DT. The connection wiring contact holes 301 and 303 are formed to expose opposite ends of the second connection wiring SL2 and the third connection wiring SL3. At this time, it is preferable that the planarization film PL covers not only the display region but also the source-drain metal material formed in the non-display region. Therefore, it is preferable that the data line DL, the second connection interconnection SL2 and the third connection interconnection SL3 are completely covered with the planarization film PL. On the other hand, the portion where only the gate metal material is formed in the non-display region does not need to be covered with the planarizing film PL. Among the source-drain elements, the portions exposed by the contact holes 301 and 303 and the drain contact hole DH are exposed only on the upper surface of the source-drain metal layer. That is, when the source-drain metal layer has a titanium / aluminum / titanium triple structure, only the titanium layer (TI) is exposed. Therefore, the source-drain metal layer is not damaged by the etching solution or the developing solution in the subsequent mask process. (Fig. 10E)

A transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) is entirely coated on the planarizing film PL. A transparent conductive material is patterned by a sixth mask process to form an anode electrode ANO, a gate pad terminal GPT, a data pad terminal DPT, a driving current pad terminal VDPT, a connection terminal SLC, The terminal SPT1 and the second signal pad terminal SPT2. The anode electrode ANO is in contact with the drain electrode DD of the driving TFT DT through the drain contact hole DH. The gate pad terminal GPT contacts the gate pad GP through the gate pad contact hole GPH. The data pad terminal (DPT) contacts the data pad (DP) through the data pad contact hole (DPH). The driving current pad terminal VDPT contacts the driving current pad VDP via the driving current pad contact hole VDPH. The connection terminal SLC connects the second connection wiring SL2 and the third connection wiring SL3 to each other through the connection wiring contact holes 301 and 303. [ The first signal pad terminal SPT1 contacts the first signal pad SP1 through the first signal pad contact hole SPH1. The second signal pad terminal SPT2 contacts the second signal pad SP2 through the second signal pad contact hole SPH2. (Fig. 10F)

A bank BA and a spacer SP are sequentially formed on a substrate SUB on which an anode electrode ANO is formed. At this time, there is a method in which the bank BA is formed first in the seventh mask process, and then the spacer SP is formed in the eighth mask process. Alternatively, the bank BA and the spacer SP may be formed by a single mask process. At this time, since the heights of the banks BA and the spacers SP are different from each other, it is preferable to form them by a seventh mask process using a half-tone mask. (Fig. 10G)

The thin film transistor substrate for an organic light emitting display according to the present invention does not form a protective film. Therefore, the mask process for patterning the contact holes formed in the protective film is omitted. That is, the number of mask processes is reduced to 7 or 8 mask processes in the conventional 8 or 9 mask process. Therefore, the manufacturing time can be shortened, the manufacturing cost can be reduced, and errors occurring in the mask process can be reduced. Further, without forming a protective film, the exposed source-drain metal layer partially extends the planarization film to completely cover the source-drain metal layer. For this purpose, it is preferable that all the pads are formed using a gate metal, and only the necessary wiring part is formed of the source-drain metal layer. Therefore, it is possible to prevent the source-drain metal layer from being damaged by the etchant and the developer used in the subsequent steps.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

ST: switching TFT DT: driving TFT
SG: switching TFT gate electrode DG: driving TFT gate electrode
SS: switching TFT source electrode DS: driving TFT source electrode
SD: switching TFT drain electrode DD: driving TFT drain electrode
SA: switching TFT semiconductor layer DA: driving TFT semiconductor layer
GL: gate wiring DL: data wiring
VDD: Drive current wiring GP: Gate pad
DP: Data pad GPT: Gate pad terminal
DPT: Data pad terminal VDP: Drive current pad
VDPT: driving current pad terminal GPH: gate pad contact hole
DPH: Data pad contact hole VPH: Drive current pad contact hole
SPl: first signal pad SP2: second signal pad
SPT1: first signal pad terminal SPT2: second signal pad terminal
SPH1: first signal pad contact hole SPH2: second signal pad contact hole
SL1: first connection wiring SL2: second connection wiring
SL3: Third connection wiring SLC: Connection terminal
100: first contact hole 200: second contact hole
301, 303: connection wiring contact hole 400: data contact hole
GI: Gate insulating film IN: Insulating film
PAS: protective film PL: planarization film
BA: bank SP: spacer

Claims (10)

A substrate partitioned into a display area and a non-display area;
A semiconductor layer formed in the display region on the substrate;
A gate insulating film covering the semiconductor layer;
A gate element formed on the gate insulating film;
An insulating film covering the gate element;
A source-drain element formed on the insulating film;
A planarization film covering the display region and the source-drain element formed in the non-display region;
Connection contact holes formed in the planarization film to expose upper surfaces except an etching side of two source-drain elements spaced apart from each other in the non-display area;
An anode electrode formed on the planarization layer and connected to the source-drain element; And
And a connection terminal formed on the planarization film and connecting the two source-drain elements to each other through the connection contact holes.
The method according to claim 1,
The source-
A source electrode and a drain electrode respectively contacting both side surfaces of the semiconductor layer; And
And a data line connected to the source electrode and extending in the longitudinal direction of the substrate,
The gate element
A gate electrode overlapping the semiconductor layer;
A gate wiring connected to the gate electrode and extending in a lateral direction of the substrate;
A gate pad formed on one end of the gate wiring;
A first signal pad arranged in parallel with the gate pad and a first connection wiring extended from the first signal pad;
A data pad disposed at one end of the data line; And
And a second signal pad arranged in parallel with the data pad.
3. The method of claim 2,
A first contact hole formed in the insulating film to expose one end of the first connection wiring;
A second contact hole formed in the insulating film to expose one end of the second signal pad;
A second connection wiring connected to the first connection wiring through the first contact hole as a part of the source-drain element;
A third connection line connected to the second signal pad through the second contact hole as a part of the source-drain element; And
Further comprising a first connection contact hole and a second contact hole formed in the planarization film to expose respective upper surfaces of mutually facing one side surfaces of the second connection wiring and the third connection wiring,
Wherein the second connection wiring and the third connection wiring are connected by a connection terminal through the first connection contact hole and the second connection contact hole.
3. The method of claim 2,
And a data contact hole formed in the insulating film to expose one end of the data pad,
Wherein the data line is connected to the data pad through the data contact hole.
The method according to claim 1,
A bank layer exposing a part of the anode electrode on the planarization film on which an anode electrode is formed;
Further comprising a spacer formed on the bank layer with a predetermined height.
A first mask process for forming a semiconductor layer on a substrate;
A second masking step of continuously depositing a gate insulating layer and a gate metal layer on the semiconductor layer and patterning the gate metal layer to form a gate element;
A third masking step of applying an insulating film on the gate element and patterning the insulating film and the gate insulating film to expose both sides of the semiconductor layer and a part of the gate element;
A fourth mask process of applying a source-drain metal layer over the insulating layer and patterning to form a source-drain element in contact with the exposed gate element;
A fifth masking step of applying a planarization film over the source-drain element and patterning the planarization film to cover the entire source-drain and expose a part of the upper surface of the source-drain element; And
And a sixth masking step of applying a transparent conductive material on the planarizing film and patterning the anode electrode and the connection terminal to contact with a part of the exposed source-drain element.
The method according to claim 6,
Wherein the source-drain element formed in the fourth masking step comprises:
A source electrode and a drain electrode that are in contact with both side surfaces of the exposed semiconductor layer; And
And a data line connected to the source electrode and extending in the longitudinal direction of the substrate,
Wherein the gate element formed in the second mask process comprises:
A gate electrode overlapping the semiconductor layer;
A gate wiring connected to the gate electrode and extending in a lateral direction of the substrate;
A gate pad formed on one end of the gate wiring;
A first signal pad arranged in parallel with the gate pad and a first connection wiring extended from the first signal pad;
A data pad disposed at one end of the data line; And
And a second signal pad arranged in parallel with the data pad.
8. The method of claim 7,
In the third mask process,
A first contact hole in the insulating film so as to expose one end of the first connection wiring; And
Further forming a second contact hole in the insulating film to expose one end of the second signal pad;
In the fourth mask process,
A second connection wiring connected to the first connection wiring through the first contact hole as a part of the source-drain element; And
Forming a third connection wiring as a part of the source-drain element, the third connection wiring being connected to the second signal pad through the second contact hole;
In the fifth mask process,
Further forming connection contact holes in the planarization film so as to expose respective upper surfaces of opposed sides of the second connection wiring and the third connection wiring, respectively;
In the sixth mask process,
Wherein the second connection wiring and the third connection wiring are connected by the connection terminal.
8. The method of claim 7,
In the third mask process,
A data contact hole is further formed in the insulating film so as to expose one end of the data pad,
In the fourth mask process,
Wherein the data line is connected to the data pad through the data contact hole.
The method according to claim 6,
A bank layer exposing a part of the anode electrode on the planarizing film on which the anode electrode is formed; and a seventh masking step of forming a spacer having a predetermined height on the bank layer .

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