KR101838875B1 - Semiconductor test equipment interface and it's manufacturing method - Google Patents

Abstract

Although the pitch of the pads of the IC chip to be inspected is as dense as that of the pads and the pads are arranged in two rows or more and are complicated, a chip having a one-to-one correspondence with the IC chip on the wafer chip produced by the same method as the IC chip By forming the pads, the pads and the chip pads are accurately brought into contact with the microneedle blocks. In particular, the chip pads of the wafer chip and the main pads of the main substrate for the inspection apparatus adopt a wire bonding method, The present invention relates to an interface for a semiconductor inspection apparatus and a manufacturing method thereof, as long as a circuit pattern which overlaps with each other in a limited space can be formed.
To this end, the present invention comprises a wafer chip having chip pads corresponding one-to-one with pads of an IC chip to be inspected; A main board which is connected to the inspection apparatus in a circuit is pierced with a chip seat where the wafer chip is placed in the center, and a main pad corresponding to the chip pad is provided around the chip seat; Wherein the wafer chip is placed on the chip and then the chip pad and the main pad are connected in circuit by wire bonding and then wrapped and protected by an insulating layer; And the wafer chip is removed by melting so that only the chip pads are left.

Description

TECHNICAL FIELD [0001] The present invention relates to an interface for a semiconductor testing apparatus and a manufacturing method thereof,

The present invention relates to an interface for a semiconductor inspection apparatus and a method of manufacturing the same, and more particularly, to a semiconductor inspection apparatus, And the semiconductor chip inserted into the main board has chip pads corresponding one-to-one with the pads of the IC chip, so that the accuracy of contact with the microneedle blocks can be improved. And a method of manufacturing the same.

In recent years, as the degree of integration of ICs has increased and the pitch of pads has become smaller and smaller, a cantilever type (aka EPOXY) that has been used has reached a corresponding limit, and a checkerboard bump pad The cantilever type can not be supported, and the development of a vertical type probe card is further demanded. Recently, many companies in Korea and overseas have been making efforts to develop a vertical type probe card using MEMS (Micro Electro-Mechanical Systems) technology. However, it has a separate interface for connecting the main PCB of the inspection equipment Interface module is needed to increase production cost.

In the case of domestic companies focusing on memory semiconductors, efforts are being made to develop HTCC (High Temperature Cofired Ceramics) or LTCC (Low Temperature Cofired Ceramics), which is a multilayer ceramic product with high thermal conductivity and high electrical conductivity. However, there is no other company in the world that succeeded in mass production except Kyocera of Japan. Globally, the probe card market is expected to grow annually from $ 1.281 billion in 2013 to $ 1.46 billion by 2016. Formfactor of the United States is the most representative company in the field, and Kyocera of Japan has the best technology in the interface module field to be developed in the present invention. Currently, many academic presentations and theoretical discussions are held at home and abroad, but the interface for probe cards has been developed in reality, and there is no other company in Japan except Kyocera.

Although the interface module has the advantage of being a consumable product, the phenomenon in which the technology is in an empty state is limited in the characteristics of a probe card having a small amount of variety, a pattern formation of less than 100 μm, and a difficulty in realizing high- Show.

U.S. Patent No. 7,640,660 issued to Fujitsu of Japan in the prior art discloses a wire board in which a core portion and an outer core wiring portion are laminated, the core portion is composed of a carbon fiber and a resin, Has a structure in which at least one glass fiber insulating layer is present, and the conductor wire has a elastic modulus of 10 to 40 GPa and is bonded to a carbon fiber reinforced portion. The outer core wiring portion is a structure in which at least one insulating layer and the wiring pattern are bonded to the core portion in the inner core wiring portion.

In U.S. Patent No. 8,354,855 to Formafactor, a carbon nanotube column is used as a contact probe in which carbon nanotubes can become electrically conductive, the column is capable of growing, and the growth process parameters are the direction of the column length This can change the mechanical properties of the growth column. The metal may be attached to the interior or attached to the exterior of the column to improve the electrical conductivity of the column and the metal treated column may be fastened to the wiring substrate terminals and the contact tip may be attached to both ends of the column . The wiring substrate can be combined with other electronic components so that the carbon nanotube column has a function as a contact probe.

In US Pat. No. 8,263,874, Kyocera, Japan, a multilayer wiring board composed of a through conductor with low inductance is composed of a ceramic substrate, and the first ceramic layer and the second ceramic layer are thin And the through conductor is very short in length and has a dielectric constant lower than that of the resin insulating layer so that the operating frequency of the multilayer wiring board can be increased.

In US Pat. No. 8,378,704, Kyocera, Japan, a substrate as a substrate for assembling a probe card has a first surface with a first electrode set and a second surface with a second electrode set connected to the first electrode set Wherein the substrate has a base layer electrically connected to the third set of electrodes connected to the second set of electrodes and the second surface layer comprises a plurality of contact terminals electrically connected to the third set of electrodes, Is composed of a plurality of intermediate layers made of different materials, and the resin layer is connected to the second surface of the interconnected layer and the first surface of the base layer.

However, these conventional techniques use a multilayer ceramic or multilayer polymeric resin film, which makes it difficult to manufacture and has a disadvantage in that the durability is lowered due to thermal expansion shrinkage. Since a large number of needles are directly attached to the surface of the interface module, There is a disadvantage that an expensive interface module can not be used.

The inventor of the present invention has proposed a technique of forming a pan out circuit pattern on the surface of a composite fiber fabric in Patent Publication No. 2014-0129525. When the circuit lines are extended (Pan Out), semiconductor wafers having pads with narrow pitch intervals and IC chips for flat panel displays can be measured.

However, when the pads of the IC chip to be inspected are arrayed in a plurality of rows, the technique of forming a circuit pattern between the pads is very difficult. When a plurality of IC chips are inspected at the same time, A technique of laminating a plurality of textile fabrics is required. This technique increases the contact area between the pads, thereby increasing the contact resistance and causing poor contact.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an IC chip which is similar to the IC chip even if the intervals between the pads of the IC chip to be inspected are dense with the size of the pad and the pads are arranged in two or more rows, The chip pads and the chip pads are accurately brought into contact with the micro needle blocks by forming the chip pads corresponding one-to-one with the pads of the IC chip on the wafer chip produced by the method, The main pad of the substrate adopts a wire bonding method so that the wires are not interfered with each other in a three-dimensional manner so that a circuit pattern can be formed which overlaps with each other in a limited space, and a manufacturing method thereof.

In one embodiment of the present invention, a chip pad corresponding to a pad of an IC chip is formed on a wafer in the same manner as the manufacturing process of an IC chip to be inspected, the wafer is cut into an IC chip to form a wafer chip The chip is placed in the center of the drilled chip in the center of the main board. The main board is formed with a main pad corresponding to the chip pad of the wafer chip around the chip spot and an extension pad having a pitch larger than that of the chip pad of the IC chip is formed at a portion apart from the main pad, Forming an extended circuit pattern to be connected in circuit with the pad.

Further, the chip pads of the wafer chip and the main pads of the main substrate are connected in a circuit by bonding wires protruding three-dimensionally from the surface of the main board to skip the chip seats. Thereafter, the surface of the main substrate and the wafer chip is coated with an insulating resin to fix the wires and the chip pads, the wafer chip is treated by chemical treatment, and the surface of the remaining chip pad is polished to match the flatness with the bottom surface of the main substrate. Thereafter, the polished surface of the chip pad is plated to form a protruding portion from the bottom surface of the main substrate, and the pad is brought into contact with the pad of the IC chip with the micro needle block.

In this process, the polished surface of the chip pad may be directly brought into contact with the pad of the IC chip without forming a plating layer.

The main board of the embodiment of the present invention may be composed of a hard product of synthetic resin, a flexible soft resin product, or a composite fiber fabric. In the case of the soft resin film and the composite fiber fabric, the hardened insulating layer catches the surface, The flatness can be maintained and used. In addition, since the soft resin film and the composite fiber fabric are formed to have a thin thickness, they can be stacked in multi-stages, and the circuit pattern can be dispersed on the substrate of each layer.

According to the present invention, in the case of an IC chip to be inspected having a pattern in which pitch intervals are densely arranged and the pads are arranged in complicated arrangement of two or more rows, the interface has been constructed by extending the pitches of the pads according to the lamination method of Kyocera Japan, And the number of contact portions is increased by the number of laminations, thereby causing noise in a circuit.

In the embodiment of the present invention, a wafer chip having the same pad arrangement as the pads of the IC chip to be inspected is fabricated in a semiconductor manufacturing process, the main substrate and the wafer chip are combined with a wire bonding technology, Bonding technology is a universal technology that can be easily accessed, minimizing the contact area between the pads and advantageously making it possible to implement a circuit-stable interface easily and inexpensively.

1 is a wafer chip process diagram of an embodiment of the present invention
2 is a circuit substrate process diagram of one embodiment of the present invention
Fig. 3 is a view showing a process of bonding the wafer chip and the circuit board of the embodiment of the present invention
FIG. 4 is a cross-sectional view of a wafer chip and a circuit board according to an embodiment of the present invention;
5 is a cross-sectional view of the finished product of one embodiment of the present invention
FIG. 6 is a flowchart showing the manufacturing process of one embodiment of the present invention

The interface of the embodiment of the present invention forms a plurality of wafer chips 11 having chip pads 12 corresponding one-to-one with the pads 51 of the IC chips 50 to be inspected on the wafer 10 in the semiconductor manufacturing process . Thereafter, the wafer chips 11 are cut singly or a plurality of chips are cut into a bundle, and the main substrate 20, which is connected to the testing device in a circuit, is provided with chip spots (21).

A main pad 22 corresponding to the chip pad 12 is formed on the main substrate 20 and the chip pad 12 is separated from the main pad 22 to have a width An extended extension pad 23 is formed and the main pad 22 and the extension pad 23 are connected in circuit by the printed signal line 24 to form an extended circuit pattern.

The wafer chip 11 is placed on the chip seat 21 and the chip pad 12 and the main pad 22 are bonded to the wire 30. The wire bonding technology uses techniques used in the main board manufacturing process of soldering or semiconductor inspection equipment.

Since the bonded wire 30 is separated from the surface of the main board 20, the bonded wire protrudes from the surface of the chip seat 21, and even if a plurality of wires 30 are stacked in multiple stages, The chip pads 12 and the main pads 22 having a tight pitch interval can be effectively connected one-to-one in a limited space.

An epoxy resin insulating resin is applied to the surfaces of the main substrate 20 and the wafer chip 11 except for the extension pad 23 so that the wires 30 and the chip pads 12 are electrically connected to the main board 20 Thereby forming an insulating layer 40 to be fixed to the surface. Thereafter, the wafer chip 11 exposed to the bottom surface of the main substrate 20 is impregnated with the potassium hydroxide solution to be peeled, and the chip pad 12 and the insulating layer 40 are exposed on the bottom surface.

Thereafter, the chip pad 12 and the insulating layer 40 are polished so as to match the flatness of the bottom surface of the main substrate 20 and the polished chip pad 12 is plated with a conductive metal to form a plating layer 13, And protrudes from the bottom surface of the substrate 20.

5, the protruded plating layer 13 is connected to the pad 51 of the IC chip 50 and the probe of the micro needle block 60, and the extension pad 23 ) Is connected in circuit with the test apparatus.

A plurality of planar needles are embedded in an insulating resin or an insulator to maintain a constant pitch interval. A probe protrudes vertically through the needle block 60, and the probes protrude from the plating layer 13 and the pad 51 one to one.

The interface of the embodiment of the present invention constituted as described above is effective in the inspection of the IC chip 50 in which the pitches of the pads are as fine as the widths of the pads. The wafer chips 11 produced in the semiconductor manufacturing process are one- And is coupled to the rear main board 20. Is used for inspecting one IC chip 50 when one wafer chip 11 is used and when a plurality of wafer chips 11 are combined and used to inspect a plurality of IC chips 50 at the same time.

In the embodiment of the present invention, since the chip pads 12 corresponding to the pads 51 of the IC chip 50 on the wafer chip 11 are formed in the semiconductor manufacturing process, the pitch intervals are precise. Accordingly, the contact area between the chip pad 12 and the pad 51 is precisely perpendicular to the probe of the micro needle block 60, so that the contact area is always constant.

The main wafer 20 and the wafer 11 are fixed with the insulating layer 40 and only the wafer 11 is removed with a chemical and the bottom surface is polished flat. Since the pads corresponding one to one to the pads 51 of the IC chip 50 are formed as a single body by forming the plating layer 13, productivity is remarkably improved as compared with a method of expanding the pads while stacking the ceramics in multi- In addition, there is no risk of short circuit due to reduced number of contacts, and there is an advantage that reliability of inspection is improved by reducing contact resistance.

The chip pads 12 and the main pads 22 are connected with a technique of three-dimensionally bonding the wires 30. The chip pads 12 and the main pads 22 are connected to each other in three- It is advantageous in that highly integrated IC chips 50 can be efficiently inspected.

The main board 20 may be formed of a hard synthetic resin, a flexible soft resin film, or a composite fiber fabric. The insulating layer 40 is formed on the surface of the main substrate 20 to hold the soft resin film and the composite fiber fabric so that the soft resin film and the composite fiber fabric are kept flat without being sagged.

In another embodiment of the present invention, a plurality of main boards 20 composed of the flexible resin film or the composite fiber fabric are adhered in multiple stages. It is not necessary that the main pad 22 and the extension pad 23 are dispersed and the signal lines 24 connecting them are densely arranged on each of the bonded main boards 20.

Therefore, there is an advantage in that a plurality of IC chips 50 are simultaneously inspected. If four wafer chips 11 are provided in a bundle in order to inspect four IC chips 50 at a time, four main substrates 20 are laminated and bonded to each other, and each of the IC chips 50 It is convenient to configure the circuit pattern more than when one of the four wafer chips 11 is connected to one main substrate 20. In this case,

10: wafer 11: wafer chip
12: chip pad 13: plated layer
20: main substrate 21: chip spot
22: main pad 23: extension pad
24: signal line 30: wire
40: Insulation layer 50: IC chip
51: Pad 60: Micro Needle Block

Claims (6)

The main chip is perforated so that a chip pad corresponding to one-to-one correspondence with the pad of the IC chip to be tested is placed in the center of the main substrate, a main pad corresponding to the chip pad is formed on the main substrate around the chip chip, A method of manufacturing an interface for a semiconductor inspection apparatus in which a pad and a chip pad are bonded to a wire, an insulating resin is applied to the wire, the main pad and the chip pad are embedded in an insulating layer,
Forming a wafer chip having the chip pad on a wafer in a semiconductor manufacturing process;
Cutting the wafer chip in the wafer one by one;
Forming an extension pad on the main board, the extension pitch of which is greater than the pitch of the IC chip and the width of the pad, and connecting the main pad and the extension pad in a circuit;
Placing the wafer chip on a chip, bonding the main pad and the chip pad with wires, and applying an insulating resin to the main substrate and the wafer chip so that the main pad, the wire, and the chip pad are embedded in the insulating layer; And
And exposing the insulating layer and the chip pad to dissolve the wafer chip exposed on the bottom surface of the main substrate with a solution to allow the exposed chip pad to be connected to the pad of the IC chip and the micro needle block. Interface manufacturing method. The method according to claim 1,
The chip pad and the insulating layer exposed on the bottom surface of the main substrate are polished and a polished layer of a conductive metal is formed on the polished chip pad so as to protrude from the bottom surface of the main substrate, Wherein the semiconductor chip is connected by a needle block. An interface for a semiconductor inspection apparatus manufactured by the method of claim 1 or 2. delete delete delete

Images