KR101820665B1 - A cmos full-wave rectifier for bio-implant devices - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS full wave rectifier for a living body implantable device, and more particularly, to a CMOS full wave rectifier for a living body implantable device, To a CMOS full wave rectifier.

Description

[0001] The present invention relates to a CMOS full-wave rectifier for biomedical devices,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CMOS full-wave rectifier for a living body implantable device, and more particularly, to a CMOS full-wave rectifier for a living body implantable device that minimizes a leakage current and eliminates a threshold voltage, To a high efficiency CMOS full wave rectifier.

Recently, as the supply of bio-implantable devices such as pacemakers, artificial heart, functional electric simulators, monitoring devices and retinal simulators that require long-term use has expanded, research and development of technology for supplying power to such devices has been actively carried out have.

A sufficient amount of power supply is required for driving the biomedical device, and this is not a problem that can be solved simply because the power conversion efficiency is high because it uses a limited energy source.

Power supply technologies in biomedical devices include methods involving embedded batteries and transcutaneous power collection methods that collect power from the skin.

These power supply methods are a very limited way to apply to a biomedical device since they have energy density, device life, implementation method, structural limitations and can not be said to be entirely harmless to humans. Therefore, in order to solve this problem, recently, we are concentrating on the development of wireless power supply technology, and in particular, we are making efforts to enable power supply even at the power supply distance reaching the limit of wireless power supply. However, these conventional techniques are required to be improved because they exhibit very low power conversion efficiency due to poor coupling, power absorption in skin, and narrow band-pass. Therefore, it is necessary to supply stable power from the winding of a coupling coil used for wireless charging through a CMOS (Complementary Metal Oxide Silicon) rectifier in order to improve and stabilize the power and voltage conversion efficiency.

Voltage Conversion Efficiency (VCE) and Power Conversion Efficiency (PCE) of a CMOS rectifier are influenced by circuit topology, diode-device parameters, input RF signal frequency and amplitude and output loading conditions . The low turn-on voltage is one of the most important factors in the diode device because the input signal supplied from the secondary winding in the wireless power transmission system is considerably weak. The performance of a diode connected transistor (DCT) device is limited by the relatively high threshold voltage. Voltage conversion efficiency and power conversion efficiency can be dramatically improved by using a threshold voltage cancellation technique. Because reverse leakage current is another factor limiting the performance of MOS based diodes, various threshold rejection and reverse leakage current removal techniques have been proposed over the years to improve MOS-based diode performance come.

The SVC efficiency through (self-V _th -cancellation) technical methods have been proposed such as by Kotani (K. Kotani and T. Ito, "High efficiency CMOS rectifier circuit with self V th -cancellation and power regulation functions for UHF RFIDs, "IEEE Proc. IEEE ASSCC, Nov. 2007, pp. 119-122, K. Kotani and T. Ito," Self-V _th -cancellation high-efficiency CMOS rectifier circuit for UHF RFIDs, "IEEE Trans. , vol. E92-C, No. 1, pp. 153-160, Jan. 2009). The method eliminates the threshold voltage of the MOSFET by the gate bias voltage generated from the output voltage of the rectifier itself. The method suggests forming a simple device structure at the cost of high reverse leakage current. Kotani et al. Also proposed an improved SVC rectifier (K. Kotani, A. Sasaki, and T. Ito, "High-efficiency differential-drive CMOS rectifier for UHR RFIDs," IEEE Trans. Solid-State Circuits, vol. 44, no. 11, Nov. 2009). This results in improved voltage conversion efficiency results over the SVC method by applying a cross-coupled differential CMOS structure. However, the above method does not provide a satisfactory voltage conversion efficiency. In addition, a CMOS inverter based on an active rectifier structure is proposed by Raben et al. (H. Raben, J. Borg, and J. Johansson, "An active MOS diode with V _th cancellation for RFID rectifiers, on RFID, 2012, pp. 54-57). The techniques described in this document provide both good voltage conversion efficiency and power conversion efficiency by reducing both the reverse leakage current and the threshold voltage. A technique based on a bootstrap capacitor by Le et al. Has been proposed for rectifier improvement (Triet T. Le, J. Han, A. von Jouanne, K. Mayaram, and Terri S. Fiez, "Piezo pp. 1411-1420, Jun. 2006, " SS Hashemi, M. Sawan, and Y. Savaria, " Electron Micro-Power Generation Interface Circuits, "IEEE Journal of Solid-State Circuits, vol. Vol. 6, No. 4, pp. 326-335, Aug., 2012). &Quot; A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices, "IEEE Trans. Biomed. These techniques improve the voltage conversion efficiency and power conversion efficiency of the rectifier by reducing the threshold voltage efficiency of the main path transistor.

U.S. Patent No. 8415637B2 (Apr. 19, 2013) discloses a switch mode voltage rectifier, an RF energy conversion, and a wireless power supply. In the switching topology, a crossing using a transistor having a threshold voltage of almost zero A combined rectifier is presented, and a topology is proposed to solve the reversal problem.

However, the prior art is somewhat similar to the present invention in that it is a cross-coupled structure, but differs from the configuration in which leakage current is minimized and threshold voltage is removed by using the bootstrap capacitor and the inverter of the present invention.

In another prior art, U.S. Patent No. 8046081 (Oct. 25, 2011) is directed to an implanted system having a DC-free input and output, wherein the implantable power source includes a plurality of A full-wave rectifier including a power input port and a plurality of output power ports for outputting a sensed power signal, and a MOS transistor switched by a diode.

However, in the above prior art, there is no need for a high-efficiency CMOS full-wave rectifier that solves power problems in a system or a device capable of low-voltage biotransplantation that is supplied with power by minimizing a leakage current and eliminating a threshold voltage, There is no preview.

Accordingly, the present invention proposes a CMOS full-wave rectifier for a bio-implantable device, which has the advantages of a rectifier structure based on a CMOS inverter and a bootstrap capacitor, in order to improve the conventional rectifier described above. Also, in the present invention, the power conversion efficiency and the voltage conversion efficiency of the CMOS full-wave rectifier are improved by using a method of reducing the reverse leakage current and the effective threshold voltage of the main path transistor.

The present invention has been made for application to a small-sized device requiring a rectifier such as a bio-implantable device, and it is an object of the present invention to improve a high driving voltage, a low power conversion efficiency and a voltage conversion efficiency, And which can convert a DC output power into a DC output power through a high conversion efficiency even in an environment where the rectifier is used.

Also, the present invention provides a high-efficiency CMOS full-wave rectifier of a low driving voltage that can be turned on even under an environment where a low voltage is applied, such as a wireless charging environment, A CMOS full wave rectifier for a living body implant device.

A CMOS full-wave rectifier for a bioimplant device according to an embodiment of the present invention includes a bootstrap capacitor (C1, C2), a cross-coupled differential CMOS transistor, and an inverter, wherein the inverter is connected to the cross- And the reverse leakage current caused by the reverse leakage current is cut off.

In addition, the cross-coupled differential CMOS transistor includes a pair of nMOS (M2) transistors and a pMOS (M4) transistor which are cross-coupled to each other in a bridge form, wherein a pair of nMOS (M1) and pMOS .

The inverter also includes DCT (Diode Connected Transistors) M13 and M15 controlled through the transistors M14 and M16 connected to the power source and the differential mode, And turns off the main path transistor M3 during the half period (VRF-).

The CMOS full-wave rectifier further includes a DCT (M11, M12) connected in series to a bootstrap capacitor, the inverter performing a threshold removal operation during a positive half period (VRF +), the transistor M8 being on, The bootstrap capacitor C1 is charged through the DCT M11 and the threshold canceling operation is performed during the negative half cycle VRF + while the transistor M8 is turned on to charge the bootstrap capacitor C1 through the DCT M11 Thereby activating the in-circuit threshold cancellation of the main path transistor M3 and turning on the transistor M7 through the differential mode transistor M14 during the negative half period VRF-, The reverse leakage current through the main path transistor M3 is cut off by making the voltage between the drain and gate of the transistor M3 equal to zero.

Further, in the CMOS full-wave rectifier, if the DCT (M13) is, but to monitor the on-off switching of the transistors (M7, M8) of the inverter, VRF + <If V _OUT, M7 = ON, M8 = OFF VRF +> V _OUT, M8 = ON and M7 = OFF.

The CMOS full-wave rectifier further includes capacitor discharge MOS transistors M17 and M18 connected in parallel to both ends of the bootstrap capacitor C1.

Further, the CMOS full-wave rectifier further includes a DCT (M5) and an output capacitor (CL), and in a positive half period (VRF +), the transistor M8 of the inverter is on and the capacitor discharge MOS transistors M17 and M18 ) Is off and the DCT (M5) generates an auxiliary path charging the output capacitor (CL) during the rise time of VRF + until V _OUT = (VRF +) - V _th - M5.

The CMOS full-wave rectifier is also configured such that as the output node is charged, the bootstrap capacitor C1 is also charged through the DCT M11, and the voltage across the bootstrap capacitor C1 is V _C1 = (VRF +) - V _{_M5 th} - V _{th _M11} - characterized in that the increase in V _{th _M8} - in _{V th _M8 V C1 = V OUT} - V th _M11.

Further, V _C1 = (VRF +) - 2V _{th (pMOS)} - V _th - _{M 8} .

Further, the pMOS (M3) the voltage between the source and the gate of the transistor _{V SG _M3 = (VRF +)} - V th _M8 - V C1 or V _{SG_M3} = V _{SG _M3} = V _{th _M11} + V _{th _M5>} V _{th _M3} one time , M3 is conducting and is charged to the output node, and the M3 is characterized in that it remains in the cut-off state before the V _{SG _M3} to reach V _{th _M3.}

In _{addition, (VRF +) - V th} _M8 - V C1 ≥ a _{V th _M3, V th _M3 =} (VRF +) - V th _M8 - V OUT + V th _M11 + V th _M8, V OUT = (VRF +) - (V _{_m3 th} - V _th is _{_M11),} the effective threshold voltage of the pMOS (M3) transistors are characterized by shrinking.

In addition, the CMOS full wave rectifier is used as a power source device of a living body implantable device.

In addition, in the cross-coupled differential CMOS transistor, the nMOS (M2) transistor generates a return path for charging the output capacitor CL, the gate of M2 being biased to be activated by the differential mode signal, The gate voltage is positively biased and effectively reduces the turn-on voltage of M2, thereby reducing on-resistance.

Also, the bulk of the DCT (M5) is characterized by being connected to the highest voltage available by DBS (Dynamic Bulk Switch).

The present invention relates to a CMOS full wave rectifier that can be used in various small devices such as a system or device capable of low-voltage biotransplantation or a small RFID tag. The rectifier has been miniaturized through a simple structure, and the miniaturized CMOS full-wave rectifier can show high utility in constituting an integrated circuit which has recently attracted attention. The CMOS full wave rectifier minimizes the current leakage in the reverse direction and lowers the effective threshold voltage by applying an nMOS switch and a pMOS switch cross-coupled in differential mode gates. Therefore, the AC input signal AC can be converted into a larger DC output signal DC through the CMOS full-wave rectifier than the conventional rectifier.

In addition, by implementing a high efficiency CMOS rectifier that can turn on the low voltage to solve the power problem in the system or the device that can be powered by wireless low-voltage biotransplantation, There is an effect that it is possible to solve various problems such as the risk of the user caused by the high voltage and the interference between the peripheral devices.

In addition, the CMOS full wave rectifier uses a control method that completely turns off the diode in the reverse state and activates the threshold elimination in the forward state. Thus, reverse leakage is minimized and maximum threshold rejection can be implemented in a wide source amplitude range. It is also possible to increase the load current by managing the reverse leakage with the main path pMOS transistor turned off. Therefore, simultaneous application of differential cross-coupled structure and threshold elimination technology resulted in very low dropout results in MOS switches. And a dynamic body bias method was applied to form an alternative path. Simulation results show that the voltage and power conversion efficiency are significantly increased when compared with conventional rectifiers. Since the CMOS full-wave rectifier has a low turn-on voltage, it has an advantage of exhibiting good efficiency even when the input power voltage is low.

1A is a circuit diagram showing a structure of a conventional SVC rectifier.
1B is a circuit diagram showing a structure of a conventional differential CMOS rectifier.
1C is a circuit diagram showing a structure of a conventional bootstrap capacitor-based rectifier.
2 is a circuit diagram showing a structure of a CMOS full-wave rectifier according to an embodiment of the present invention.
3 is a graphical representation of a comparison of the reverse leakage currents of different rectifier topologies in a positive half-period (VRF +) according to an embodiment of the present invention.
4 is a flowchart of a method for reducing the effective threshold voltage of a cross-coupled differential CMOS transistor according to an embodiment of the present invention.
5A is a graph illustrating a simulation result of power conversion efficiency according to input peak amplitudes of a CMOS full-wave rectifier and various rectifiers according to an embodiment of the present invention.
5B is a graph illustrating simulation results of voltage conversion efficiency according to input peak amplitudes of a CMOS full-wave rectifier and various rectifiers according to an embodiment of the present invention.
6 is a graph illustrating simulation results of conversion efficiency according to bootstrap capacitor size according to an embodiment of the present invention.
7A is a graph illustrating voltage conversion efficiency results according to input peak amplitudes before and after a layout according to an embodiment of the present invention.
FIG. 7B is a graph showing power conversion efficiency results according to input peak amplitudes before and after a layout according to an embodiment of the present invention.
8 is a diagram illustrating an example of the structure and size of a CMOS full wave rectifier according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

First, the topologies of threshold elimination or threshold voltage removal applied to a rectifier will be described. The threshold voltage is a process-parameter that is influenced by the thickness and shape of the oxide (oxide film). Some standard CMOS processors offer a low threshold voltage structure, but are not suitable for use in general purpose devices. The performance of these devices is limited by improved channel doping, excessive power consumption, and reliability issues. Thus, using a device that requires a low-threshold voltage is a better method than using a circuit based on a method of mitigating the impact of the threshold voltage (V _th ).

Schottky diodes are used in rectifiers due to their low turn-on voltage characteristics. The rectifier circuit thus achieves high voltage conversion efficiency through a circuit including a Schottky diode. However, the above method is less compatible than a general CMOS technology, and requires a high cost for realizing a manufacturing environment.

Instead, a MOS transistor connected to a diode called DCT is used for the CMOS rectifier. It is widely used because it has high compatibility. The effective turn-on voltage of the DCT is close to the threshold voltage of the MOS transistor and is lower than that of a general purpose P / N junction diode, but still shows a higher voltage than the Schottky diode. Therefore, there is a limit to realize high voltage conversion efficiency and power conversion efficiency through a simple configuration using DCT. Therefore, various rectifier structures having improved voltage conversion efficiency and power conversion efficiency for solving such problems have been proposed.

1A is a circuit diagram showing a structure of a conventional SVC rectifier. In the SVC rectifier, the gate electrodes of the nMOS and pMOS transistors are connected to the Output and Ground terminals, respectively. Through this structure, a simple rectifier structure having high power conversion efficiency with low input power can be realized. Also, in the above structure, a static gate-source voltage is applied to a MOS transistor whose effective V _th is lowered. For a high DC bias voltage, the structure has to increase the reverse leakage current, so that the overall voltage conversion efficiency and power conversion efficiency are affected.

1B is a circuit diagram showing a structure of a conventional differential CMOS rectifier. The differential CMOS rectifier is a structure in which the cross-coupled differential CMOS elements are integrated into the bridge structure. The gate of the MOS transistor actively operates by the differential mode signal. The turn-on voltage of the MOS transistor can be significantly lowered through the method of forming the differential CMOS rectifier, and the reverse leakage current can be largely lowered by the negative gate bias. The above structure can form a high power conversion efficiency, but does not show a good voltage conversion efficiency. And a large area is required to form an improved voltage conversion efficiency in multiple stages. Therefore, this is not suitable for a recently used miniaturized living body implantable device.

Figure 1c shows a rectifier based on a bootstrap capacitor and a method for this. In this method, a small bootstrap capacitor is used to lower the effective threshold voltage of the main pass transistor. The method presents a rectifier structure with significantly improved voltage conversion efficiency and power conversion efficiency over a wide range of source voltages. And a method of forming an advanced CMOS rectifier circuit capable of improving voltage conversion efficiency and power conversion efficiency, which are disadvantages of the above-mentioned rectifiers of various structures, and driving at low power.

The present invention proposes a highly efficient CMOS full wave rectifier structure that can improve performance by configuring the bootstrap rectifier and the differential CMOS rectifier in one rectifier circuit. Both the voltage conversion efficiency and the power conversion efficiency can be improved through the CMOS full-wave rectifier. In addition, a diode or pMOS DCT, which is commonly applied for threshold rejection techniques, can be substituted, including a pair of pMOS switches. It can also take advantage of the cross-coupled differential structure, including nMOS transistors, to improve efficiency.

2 is a circuit diagram showing a structure of a CMOS full-wave rectifier according to an embodiment of the present invention.

2, the CMOS full wave rectifier comprises a circuit including cross-coupled differential CMOS transistors M1, M2, M3 and M4, inverters 100 and 200 and bootstrap capacitors C1 and C2 do. The AC input signal having passed through the CMOS full wave rectifier is converted into a DC form via the circuit and output to V _OUT . The CMOS full-wave rectifier has a structure in which a bootstrap capacitor, a threshold voltage elimination and a differential CMOS characteristic are implemented in a rectifier circuit to minimize a reverse leakage current and reduce an effective threshold voltage to improve a voltage conversion efficiency and a power conversion efficiency.

The CMOS full wave rectifier includes the cross-coupled differential COMS transistors M1, M2, M3, and M4. And further includes M17, M18, M19, and M20 transistors for discharging the bootstrap capacitor composed of C1 and C2.

During the positive half period (VRF +) of the power source VAC, the inverter 100 operates using M7, M8, M13 and M14 transistors. M13 is composed of DCT and M14 is connected to differential mode. The purpose of the inverter 100 is to fully turn off M3 during the negative half-cycle (VRF-). Thus, the reverse leakage current generated from the main path transistor M3 is minimized through the above method.

The DBS method matches the bulk connection of M5 to the highest available voltage. The DBS is formed by using M21 and M22 transistors. Through long-term simulations, it was found that V _C1 rises significantly and this effect reduces V _OUT and affects the voltage conversion efficiency. To keep V _C1 constant, a high-resistance CDT (Capacitor Discharging MOS Transistor) was used for a very small amount of C1 discharge in VRF-. Therefore, C1 maintains a constant VC1 until overtime. In VRF-, the input voltage will be corrected the same as when the double circuit consisting of M1, M4, M6, M9, M10, M12, M15, M16, M23, M24 and C2 is VRF +.

Measuring the average of the output voltage, voltage conversion efficiency and power conversion efficiency in comparing different rectifiers is the most common evaluation method. The CMOS full-wave rectifier according to an exemplary embodiment of the present invention is compatible with Samsung standard 0.18 μm CMOS processor and measured using a specter simulator in a Cadence environment. Shunt loads of CL = 200 pF and RL = 2 kΩ were considered. The load condition forms a maximum load current of 5.1 mA when a sinusoidal voltage source of 4 V and 13.56 MHz frequency is applied. The sizes of the main path pMOS transistors M3 and M4 are 45 / 0.18 mu m, and the main path nMOS transistors M1 and M2 are 40 / 0.18 mu m. Auxiliary Path Transistors M5 and M6 are connected to the DCT with a size of 1 / 0.18μm, and the other sets of DCT, M11 and M12, are 15 / 0.18μm transistors.

The nMOS transistors M8 and M10 of the inverter 100 are composed of transistors having a size of 5 / 0.18 mu m. The pMOS transistors M7 and M9 are three times larger than the nMOS transistors. M13, M14, M15, and M16, which are transistors having a size of 0.4 / 0.18 mu m, are used to monitor the proper switching operation of the inverter 100. [ The CDTs M17, M18, M19 and M20 use 0.4 / 0.18μm transistors. A 0.4 / 0.18μm pMOS transistor is used for the DBS structure. The capacitance of the bootstrap capacitors C1 and C2 is 35.6 pF.

3 is a comparison of the reverse leakage currents of different rectifier topologies in a positive half period (VRF +) according to an embodiment of the present invention.

The comparison of the reverse leakage current at VRF + for M3 in the exemplary circuit shown in FIG. 2 is complemented by the description according to the symbols and names shown in FIG. The reverse leakage generated through the main path transistor of the CMOS full wave rectifier during switching operation between VRF + and VRF- has a lower value when compared with other general rectifiers. Therefore, the CMOS full wave rectifier can realize a further improved power conversion efficiency. During VRF +, the inverter 100 assists with the threshold removal operation. At VRF +, M8 turns on and charges C1 through DCT M11. This activates in-circuit threshold rejection for M3. Similarly, in VRF-, M7 operates through differential mode transistor M14. Therefore, the voltage from the drain to the gate of M3 becomes zero, which minimizes reverse leakage through M3. M13 turns on M7 when VRF + <V _OUT , turns off M8, and turns on M8 when VRF +> V _OUT , turns off M7. At VRF +, M8 is turned on and CDT M17 and M18 are turned off.

4 is a flowchart of a method for reducing the effective threshold voltage of a cross-coupled differential CMOS transistor according to an embodiment of the present invention.

First, in the positive half period VRF +, the transistor M8 of the inverter 100 is on, the MOS discharging MOS transistors M17 and M18 are off, and DCT M5 is increased by VRF + Thereby forming an alternative path for charging the output capacitor CL for a period of time (S110).

[Equation 1]

V _OUT = (VRF +) - V _th - _{M 5}

As the output node is charged, the bootstrap capacitor C1 is charged through the DCT (M11), and the voltage across the bootstrap capacitor C1 increases according to Equation (2) (SlOO).

&Quot; (2) &quot;

V _C1 = V _OUT - V _th - _{M 11} - V _th - _{M 8}

From Equation (1), Equation (3) is derived.

&Quot; (3) &quot;

V _C1 = (VRF +) - V _th - _{M 5} - V _th - _{M 11} - V _th - _{M 8}

Since the threshold voltages of the same type of transistors are almost similar when a specific process technology is used, V _C1 can be derived from Equation (3) to set V _C1 (S131).

&Quot; (4) &quot;

V _C1 = (VRF +) - _{2Vth (pMOS)} - _{Vth_M8}

And [Equation 5] and [Equation 6] set the voltage between the source and the gate of the pMOS M3 transistor.

&Quot; (5) &quot;

V _{SG_M3} = (VRF +) - _{Vth_M8} - V _C1

&Quot; (6) &quot;

V _{SG - M 3} = V _th - _{M 11} + V _{th - M 5}

Since the voltage passed through V _{SG - M3} is twice the threshold voltage, (V _th - _{M 11} + V _{th - M 5} )> V _{th - M} 3. Consequently, M3 is able to charge, and conduction is the output node, M3 will remain in a cut-off state before the V _{SG_M3} to reach a _{th_M3} V (S132). Therefore, [Expression 7] is derived from [Expression 5].

&Quot; (7) &quot;

(VRF +) - V _th - _{M 8} - V _{C 1} ≥ V _{th - M 3}

(8) is derived by substituting V _C1 in the equation (2) into the equation (7). Therefore, the effective threshold voltage of the pMOS M3 transistor is reduced (S140).

&Quot; (8) &quot;

_{_M3 th} = V (VRF +) - V _{th _M8} - V _OUT + V _th + V _{th _M11 _M8}

V _OUT = (VRF +) - (V _th - _{M 3} - V _th - _{M 11} )

Equation (8) shows when the effective threshold voltage of M3 is reduced. The low impedance return path produces a current that CL charges by the nMOS transistor M2 to which the differential mode gate cross-coupled structure is connected. The gate of M2 is actively applied by the differential-mode signal. In VRF +, the gate voltage of M2 is applied to the anode and the turn-on voltage of M2 is effectively reduced. As a result, a low ON resistance is formed.

M5 also contributes to the output current, but this is negligible compared to the overall power rise. This is because it is insignificant compared to the main-path transistor. The source of the M5 is connected to a floating power supply and its voltage change takes a long time. The exposed terminals thus can inject leakage current into the substrate and cause latch-up.

In order to verify the performance of the CMOS full-wave rectifier according to an embodiment of the present invention, the results of simulations using various types of rectifiers as comparison groups will be described.

5A is a graph illustrating a simulation result of power conversion efficiency according to input peak amplitudes of a CMOS full-wave rectifier and various rectifiers according to an embodiment of the present invention.

As can be seen in Figure 5a, the CMOS full wave rectifier shows significantly higher power conversion efficiencies over a wide range of input peak amplitudes greater than 0.7V. In particular, at the 3.3V AC source peak input, the rectifier exhibits a power conversion efficiency of 87.8%. This power conversion efficiency result is a significant improvement over the SVC rectifier and differential rectifier topology and results in a 1% increase in power conversion efficiency compared to a bootstrap capacitor rectifier.

5B is a graph illustrating simulation results of voltage conversion efficiency according to input peak amplitudes of a CMOS full-wave rectifier and various rectifiers according to an embodiment of the present invention.

As can be seen in Figure 5b, the rectifiers perform a function similar to a rectifier driving at a low amplitude input source. For an AC input source of 0.7V, a circuit with a voltage conversion efficiency of 61% is presented. The CMOS full wave rectifier shows higher efficiency than the conventional CMOS rectifier. At 3.3V input AC amplitude, the CMOS full wave rectifier recorded a voltage conversion efficiency of 89.1%. The results are measured to show higher conversion efficiency than conventional rectifiers. The improved performance of the CMOS full wave rectifier is obtained by minimizing the reverse leakage current and decreasing the effective threshold voltage. The inverter circuit of the CMOS full wave rectifier performs an operation to immediately turn off the main path pMOS transistor after the rectifying operation. Also, the reduced effective threshold of the main path pMOS transistor forms a lower voltage drop through the drain-source terminal. The differential mode structure of the main-pass nMOS transistor affects the lower channel-on resistance. Accordingly, improved voltage conversion efficiency and power conversion efficiency are realized in the CMOS full wave rectifier.

6 is a graph illustrating simulation results of conversion efficiency according to bootstrap capacitor size according to an embodiment of the present invention.

As can be seen in Figure 6, the most important factor for implementing a rectifier for a bioimplant device is the size of the bootstrap capacitor. The bootstrap capacitors take up considerable area in constructing a standard CMOS processor. Therefore, it is necessary to apply bootstrap capacitors of small size.

In the range of 25pF to 100pF, the voltage conversion efficiency and the power conversion efficiency do not differ greatly in performance. However, a large change in the time constant of the charging path of the bootstrap capacitor is sensed at 100 pF. This means that larger size bootstrap capacitors require a longer time to reach a sufficient voltage. The main path transistor is problematic due to the low voltage from the gate to the source. Such a phenomenon causes a problem in performance that the voltage drop of the main path pMOS transistor is increased and the power conversion efficiency is lowered thereby. Based on these results, the present invention attempts to minimize the size of the CMOS full wave rectifier by applying a 35.6 pF capacitor which has good voltage conversion efficiency and power conversion efficiency and can solve the size problem.

A post-layout simulation is performed to verify the performance of the CMOS full-wave rectifier. The post-layout simulation is a method of predicting parasitic components based on the geometric structure of the physical layout.

7A is a graph illustrating voltage conversion efficiency results according to input peak amplitudes before and after a layout according to an embodiment of the present invention.

As can be seen from Fig. 7A, after layout, performance after layout can be limited to some extent by the parasitic elements necessarily included in the circuit. Therefore, after verifying the performance after the layout through the simulation, it is confirmed that the voltage conversion efficiency is lower than the voltage conversion efficiency of the schematic-level before the layout. At 0.7V and 3.3V AC peak input amplitudes, the voltage conversion efficiencies of 55% and 88.6% are measured, respectively.

FIG. 7B is a graph showing power conversion efficiency results according to input peak amplitudes before and after a layout according to an embodiment of the present invention.

As shown in Fig. 7B, the effect of the parasitic element on the power conversion efficiency is shown by comparing the graphical level before layout with the result after layout. It can be seen that the performance of the power conversion efficiency is slightly reduced due to the loss due to the parasitic elements. The power conversion efficiency values represent 53% and 87%, respectively, slightly offset by the parasitic elements at peak input amplitudes from 0.7V to 3.3V.

8 is a diagram illustrating an example of the structure and size of a CMOS full wave rectifier according to an embodiment of the present invention.

The CMOS full wave rectifier implemented in FIG. 8 is configured by applying a 0.18 μm 6-metal / 1-poly Samsung standard CMOS processor, and the size of the CMOS full wave rectifier according to an embodiment of the present invention is 310 μm × 248 μm . Bootstrap capacitors use metal-insulator-metal (MIM) capacitors that are compatible with the Samsung standard 0.18μm CMOS technology library and occupy most of the area of the capacitor banks. The size of the CMOS full wave rectifier may vary depending on the size of the capacitor, and the size may vary depending on the performance and purpose of the device.

Next, the values obtained by comparing the performance of the CMOS full-wave rectifier proposed in the present invention and the four commercially available rectifier samples having the best performance are described.

Sample 1 used an active rectifier with offset-controlled high-speed comparator, Sample 2 used a CMOS rectifier with cross-coupled latch comparator, Sample 3 used a low-voltage CMOS rectifier, and Sample 4 used a 13.56 MHz CMOS active rectifier. The results of comparing the actual characteristics of the CMOS full wave rectifier with the samples are shown in Table 1 below.

[Table 1]

Referring to Table 1, the CMOS full-wave rectifier formed a wide input driving voltage ranging from 0.7V to 3.3V with a small area of 0.07mm ² , and formed a high efficiency of voltage conversion efficiency and output conversion efficiency of more than 87% . It is also necessary to calibrate the result for a rectifier that occupies a small area, and it can be seen that the rectifier topology of the present invention operates with a low source voltage, which is a very satisfactory result.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. Or modified.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention.

100, 200: Inverter
M1, M2, M3, M4: Cross-coupled differential CMOS transistors
C1, C2: Bootstrap capacitor

Claims (14)

Bootstrap capacitors C1 and C2;
Cross-coupled differential CMOS transistors M1, M2, M3, and M4; And
A first and a second inverter,
The first inverter charges the bootstrap capacitor C1 during half an amount of the input power, and the first inverter acts as a circuit for removing the threshold for the main-path transistor M3 among the cross-coupled differential CMOS transistors, The reverse leakage current through the M4 is cut off by blocking another main path transistor M4 of the differential CMOS transistors,
During the negative half-period of the input power source, the bootstrap capacitor, the cross-coupled differential CMOS transistor and the inverter are operated in dual,
And the reverse leakage current through the main pass transistors M3 and M4 of the cross-coupled differential CMOS transistors is reduced while the positive half period and the negative half period for the input power source are switched. The method according to claim 1,
The cross-coupled differential CMOS transistor comprises:
And a pair of the nMOS transistor (M2) and the pMOS transistor (M4), which are different in the pair of the nMOS transistor (M1) and the pMOS transistor (M3), are cross-coupled to each other in a bridge form. The method of claim 2,
The first inverter includes:
The input power source; And
The main path transistor M3 is turned off during the negative half period (VRF-) of the input power supply VAC through the diode connected transistor M13 controlled through the transistor M14 connected in the differential mode,
The second inverter includes:
The input power source; And
And turns off the main path transistor M4 during a positive half period (VRF +) of the input power supply (VAC) through a diode connected transistor (M15) controlled through a transistor M16 connected in a differential mode. Full wave rectifier. The method of claim 3,
The CMOS full-
A DCT M11 serially connected to the bootstrap capacitor C1, and a DCT M12 serially connected to the bootstrap capacitor C2,
The transistor M8 of the first inverter is turned on during the positive half period (VRF +) of the input power source to charge the bootstrap capacitor C1 through the DCT M11,
And the transistor M10 of the second inverter is turned on during the negative half period (VRF-) of the input power source to charge the bootstrap capacitor C2 through the DCT M12. The method of claim 3,
The CMOS full-
DCT M13 monitors the on-off switching of transistors M7 and M8 of the first inverter,
If VRF + <output voltage (V _OUT ), M7 = ON, M8 = OFF;
And switches to M8 = ON and M7 = OFF if VRF + > output voltage (V _OUT ). The method of claim 3,
The CMOS full-
Further comprising capacitor discharging MOS transistors M17 and M18 connected in parallel at both ends of the bootstrap capacitor C1. The method of claim 6,
The CMOS full-
DCT M5; And the output capacitor CL are connected in series,
The transistor M8 of the first inverter is turned on and the capacitor discharging MOS transistors M17 and M18 are turned off and the DCT M5 is turned off at the output voltage V _OUT = VRF + And generates an auxiliary path charging the output capacitor CL during the rise time of VRF + until _{Vth_M5} . The method of claim 7,
The CMOS full-
As the output node is charged, the bootstrap capacitor C1 is also charged through the DCT M11, and the voltage across the bootstrap capacitor C1 is V _C1 = (VRF +) - _{Vth_M5 Vth_M11 Vth_M8} at V _C1 = V _OUT V _{th_M11} V _{th_M8} . &_lt; / RTI &gt; The method of claim 8,
The CMOS full-
V _C1 = (VRF +) - 2V _{th (pMOS)} - V _th - _M8 . The method of claim 2,
The CMOS full-
The voltage between the source and the gate of the pMOS transistor M3 is V _{SG_M 3} = (VRF +) - V _th - _{M 8} V _C1 or V _SG - _{M 3} = V _th - _{M 11} + V _th -
When _{V SG_M3 = V SG_M3 = V th_M11} + V th_M5> V th_M3, M3 is the conduction is charged to the output node, V _{SG_M3} is before it reaches the V _{th_M3} M3 is characterized in that it remains in the cut-off state CMOS full wave rectifier. The method of claim 10,
The CMOS full-
(VRF +) - _{Vth_M8} V _C1 ? _{Vth_M3} ,
_Wherein the effective threshold voltage of the pMOS transistor M3 is reduced because _{Vth_M3} = (VRF +) - _{Vth_M8 VOUT} + _{Vth_M11} + _{Vth_M8} , _VOUT = (VRF +) - ( _{Vth_m3} - _{Vth_M11} ) rectifier. The method according to claim 1,
The CMOS full-
Wherein the power supply is used as a power supply device of a living body implantable device. The method of claim 2,
The CMOS full-
In the cross-coupled differential CMOS transistor, the nMOS transistor M2 generates a return path for charging the output capacitor CL,
The gate of the nMOS transistor M2 is biased to be activated by a differential mode signal,
The gate voltage of the nMOS transistor M2 is positively biased in VRF + to effectively reduce the turn-on voltage of the nMOS transistor M2, thereby reducing the on-resistance. The method of claim 7,
The CMOS full-
And the bulk of the DCT M5 is connected to a highest voltage available by DBS (Dynamic Bulk Switch).

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