KR101810575B1 - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

The thin film transistor panel according to an embodiment of the present invention includes a gate electrode disposed on an insulating substrate, a gate insulating film disposed on the gate electrode, an oxide semiconductor disposed on the gate insulating film, a barrier layer disposed on the oxide semiconductor, A source electrode and a drain electrode disposed on the barrier layer, a protective film disposed on the source electrode and the drain electrode, and a pixel electrode disposed on the protective film, wherein the barrier layer includes a source electrode and a drain electrode And a second portion that is not covered by the source electrode and the drain electrode, wherein the first portion and the second portion comprise different materials.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a thin film transistor (TFT)

The present invention relates to a thin film transistor display panel and a manufacturing method thereof.

The liquid crystal display device is one of the most widely used flat panel display devices, and is composed of two display panels having electrodes formed thereon and a liquid crystal layer interposed therebetween, and applying voltage to the electrodes to rearrange the liquid crystal molecules of the liquid crystal layer It is a display device that adjusts the amount of transmitted light.

A thin film transistor (TFT) display panel, which is one of two display panels constituting a liquid crystal display, is used as a circuit substrate for independently driving each pixel in a liquid crystal display device, an organic EL (Electro Luminescence) display device and the like.

The thin film transistor display panel includes a thin film transistor connected to the gate wiring and the data wiring, a pixel connected to the thin film transistor, and a scanning signal wiring for transmitting a scanning signal or an image signal line or a data wiring for transferring an image signal to the gate wiring. An electrode, a gate insulating layer which covers and insulates the gate wiring, and an interlayer insulating layer which covers and insulates the thin film transistor and the data wiring.

In the thin film transistor display panel having a plurality of layers, a photoresist layer is formed for each layer and a thin film is etched using the mask to form a pattern of each layer.

When an oxide semiconductor is used as a semiconductor included in a thin film transistor, a mask for forming an etch stop layer is further required to form an etch stop layer on the semiconductor layer in order to reduce oxide semiconductor damage caused by the etchant when the source electrode and the drain electrode are formed So that the manufacturing cost is increased and the manufacturing steps are complicated.

Accordingly, it is an object of the present invention to provide a thin film transistor panel and a method of manufacturing the same that can reduce manufacturing cost and manufacturing steps even when an oxide semiconductor is used for a thin film transistor.

The thin film transistor panel according to an embodiment of the present invention includes a gate electrode disposed on an insulating substrate, a gate insulating film disposed on the gate electrode, an oxide semiconductor disposed on the gate insulating film, a barrier layer disposed on the oxide semiconductor, A source electrode and a drain electrode disposed on the barrier layer, a protective film disposed on the source electrode and the drain electrode, and a pixel electrode disposed on the protective film, wherein the barrier layer includes a source electrode and a drain electrode And a second portion that is not covered by the source electrode and the drain electrode, wherein the first portion and the second portion comprise different materials.

The second portion of the barrier layer may be an insulating layer.

The second portion of the barrier layer may comprise silicon oxide (SiOx).

The barrier layer may comprise silicon.

The first portion of the barrier layer may be a silicide.

The oxide semiconductor layer may include GIZO.

The oxide semiconductor layer may be a bilayer structure of a top film including a lower film including GIZO having a relatively high indium content and a GIZO having a relatively low indium content.

The upper surface of the oxide semiconductor layer may be fluorinated.

The source electrode and the drain electrode may be a bilayer structure including a lower film and an upper film.

The lower film may include titanium (Ti), and the upper film may include copper (Cu).

A method of manufacturing a thin film transistor panel according to an embodiment of the present invention includes the steps of forming a gate electrode on an insulating substrate, forming a gate insulating film on the gate electrode, forming an oxide semiconductor on the gate insulating film, Forming a source electrode and a drain electrode on the barrier layer, forming a protective film on the source electrode and the drain electrode, and forming a pixel electrode on the protective film, Wherein the step of forming the oxide semiconductor, the step of forming the blocking layer, and the step of forming the source electrode and the drain electrode comprise a photolithography process, the blocking layer including a first portion covered with the source electrode and the drain electrode, And the source electrode and the drain electrode And a second portion, wherein the first portion and the second portion may comprise different materials.

Wherein the step of forming the oxide semiconductor, the step of forming the blocking layer, and the step of forming the source electrode and the drain electrode include a step of laminating an oxide semiconductor film on the gate insulating film, a step of laminating a blocking film on the oxide semiconductor film, Forming a first photoresist pattern having a different height on the metal layer, forming a first photoresist pattern on the metal layer using the first photoresist pattern as an etch mask, Etching the semiconductor film, forming a second photoresist pattern by lowering the height of the first photoresist pattern, secondary etching the first metal layer using the second photoresist pattern as an etch mask, and And oxidizing the barrier film using the secondarily etched metal layer as a mask.

The oxidized barrier layer may be a second portion of the barrier layer.

The second portion of the barrier layer may comprise silicon oxide (SiOx).

According to the embodiment of the present invention, since the insulating layer covering the semiconductor layer like the etch stop film is formed without forming the etching stopper film separately on the semiconductor layer by using the mask, the manufacturing cost of the thin film transistor panel And the manufacturing process is simplified.

1 is a layout diagram showing one pixel of a thin film transistor panel according to the present invention.
2 is a cross-sectional view taken along the line II-II in FIG.
FIGS. 3, 5, and 8 are layout views sequentially illustrating a method of manufacturing a thin film transistor panel according to an embodiment of the present invention.
4 is a cross-sectional view taken along the line IV-IV of the thin film transistor panel of FIG.
6 is a cross-sectional view taken along line VI-VI of the thin film transistor panel of FIG.
7A to 7F are cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor panel according to an embodiment of the present invention.
9 is a cross-sectional view taken along line IXI-IX of the thin film transistor panel of FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness is enlarged to clearly represent the layers and regions. Like parts are designated with like reference numerals throughout the specification. Whenever a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it includes not only the case where it is "directly on" another portion, but also the case where there is another portion in between. Conversely, when a part is "directly over" another part, it means that there is no other part in the middle.

FIG. 1 is a layout view showing one pixel of a thin film transistor panel according to the present invention, and FIG. 2 is a cross-sectional view cut along a line II-II in FIG.

Referring to FIGS. 1 and 2, a plurality of gate lines 121 are formed on an insulating substrate 110 made of transparent glass or plastic.

The gate line 121 transmits the gate signal and extends mainly in the horizontal direction. Each gate line 121 includes a plurality of gate electrodes 124 protruding from the gate line 121 and an end portion (not shown) having a large area for connection to another layer or an external driving circuit.

On the gate line 121, a gate insulating film 140 made of silicon nitride (SiNx) or silicon oxide (SiOx) is formed. A plurality of semiconductors 154 are formed on the gate insulating film 140.

The semiconductor 154 may be made of an oxide semiconductor such as GIZO, ZTO (ZnSnO), IZO, or the like.

Although not shown, in the thin film transistor display panel according to another embodiment of the present invention, the semiconductor layer 154 may include a lower film made of GIZO (Gallium Indium Zinc Oxide) having a relatively high indium (In) content and a lower film made of GIZO And a top film composed of a silicon nitride film. Thus, by disposing a GIZO film having a relatively low indium content as an upper film, it is possible to reduce the production of indium surface protrusions that may occur in the manufacturing process.

In addition, although not shown, in the thin film transistor display panel according to another embodiment of the present invention, the upper surface of the semiconductor 154 may be fluorinated. Thus, by fluorinating the upper surface of the semiconductor 154, it is possible to reduce the generation of indium surface protrusions that may occur in the manufacturing process.

On the semiconductor 154, barrier layers 163, 164, and 165 are formed. The barrier layers 163, 164, and 165 may comprise silicon (Si). A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the blocking layers 163, 164 and 165.

The data line 171 transmits a data signal and extends mainly in the vertical direction and crosses the gate line 121. Each data line 171 includes a plurality of source electrodes 173 extending toward the gate electrode 124 and a wide end portion (not shown) for connection to another layer or an external driving circuit.

The drain electrode 175 is separated from the data line 171 and faces the source electrode 173 with the gate electrode 124 as a center.

The data line 171, the source electrode 173 and the drain electrode 175 are electrically connected to the bottom film 173p and 175p of titanium (Ti) and the top film 173q and 175q of copper (Cu) Structure.

The barrier layers 163, 164 and 165 described above are formed by the first portions 163 and 165 covered with the data lines 171 or the source electrodes 173 and the drain electrodes 175 and the data lines 171 or And a second portion 164 that is not covered with the source electrode 173 and the drain electrode 175.

The first portion 163,165 of the barrier layer 163,164,165 may comprise amorphous silicon or silicide and the second portion 164 of the barrier layer may comprise silicon oxide (SiOx) .

One gate electrode 124, one source electrode 173 and one drain electrode 175 form a single thin film transistor (TFT) together with the semiconductor 154, And is formed in the semiconductor 154 between the electrode 173 and the drain electrode 175.

A passivation layer 180 is formed on the data line 171 and the drain electrode 175 and the second portion 164 of the blocking layer. The protective film 180 is made of an inorganic insulating material such as silicon nitride or silicon oxide, an organic insulating material, or a low dielectric constant insulating material.

A plurality of contact holes 185 are formed in the passivation layer 180 to expose the drain electrodes 175, respectively.

A plurality of pixel electrodes 191 are formed on the passivation layer 180. The pixel electrode 191 is physically and electrically connected to the drain electrode 175 through the contact hole 185 and receives the data voltage from the drain electrode 175. The pixel electrode 191 to which the data voltage is applied generates an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied, To determine the orientation of the liquid crystal molecules of the layer (not shown). The pixel electrode 191 and the common electrode constitute a capacitor (hereinafter referred to as a "liquid crystal capacitor") to maintain the applied voltage even after the TFT is turned off.

The pixel electrode 191 overlaps with a sustain electrode line (not shown) to form a storage capacitor, thereby enhancing the voltage holding capability of the liquid crystal capacitor.

The pixel electrode 191 and the contact assistant members 81 and 82 may be made of a transparent conductor such as ITO or IZO.

1 and 2 will now be described in detail with reference to FIGS. 3 to 9 and FIGS. 1 and 2 described above. FIG. 3 is a cross-sectional view illustrating a method of manufacturing a thin film transistor panel according to an embodiment of the present invention. FIGS. 3, 5, and 8 are layout views illustrating a manufacturing process of a thin film transistor panel according to an exemplary embodiment of the present invention. FIGS. 4, 6, 7a to 7f, Sectional views illustrating a manufacturing process of a thin film transistor panel according to an embodiment of the present invention.

As shown in FIGS. 3 and 4, a metal film is formed on an insulating substrate 110 made of transparent glass or plastic, and then patterned to form a gate line having a gate electrode 124.

5 and 6, a gate insulating film 140, a semiconductor layer 154, barrier layers 163, 164, and 165, a data line 171, a source electrode 173, and a drain electrode 173 are formed. (175).

The gate insulating film 140, the semiconductor layer 154, the blocking layers 163, 164 and 165, the data line 171, the source electrode 173, and the drain electrode 175 are formed on the gate insulating film 140, Will be described in detail.

7A, a gate insulating film 140, a semiconductor film 150, a blocking film 160, a first metal film 170a and a second metal film 170q are formed on the gate electrode 124 The metal film 170 is laminated. Here, the gate insulating layer 140 may include silicon nitride (SiNx) or silicon oxide (SiOx), and the semiconductor layer 150 may be made of GIZO, ZTO (ZnSnO), IZO, or the like as an oxide semiconductor, The film may include titanium (Ti), and the second metal film 170q may include copper (Cu).

The oxide semiconductor can be laminated by vacuum deposition or by coating an oxide semiconductor in a solution form.

Although not shown, the semiconductor film 150 may be a bilayer structure including a lower film made of GIZO (Gallium Indium Zinc Oxide) having a relatively high indium (In) content and a top film made of GIZO having a relatively low indium content .

Although not shown, after the semiconductor film 150 is laminated, the upper surface of the semiconductor film 150 may be fluorinated.

As shown in FIG. 7B, a first photoresist pattern 400a and a second photoresist pattern 400b having different thicknesses are formed by exposing and developing the second metal film 170q with a photoresist. At this time, the photosensitive film 400a located in the wiring portion of the first photosensitive film patterns 400a and 400b is thicker than the photosensitive film 400b located in the channel portion, and the remaining photosensitive film is removed. The ratio of the thickness of the photoresist layer 400 located at the wiring portion to the thickness of the photoresist layer 400 located at the channel portion should be different according to the process conditions in the etching process to be described later, It is preferable that the thickness of the portion of the photoresist film 400a is not more than 1/2.

As described above, there are various methods of forming the thickness of the photoresist layer depending on the position. In the exposure mask, a semi-transparent area as well as a transparent area and a light blocking area are formed. For example. A semi-light-transmitting region is provided with a slit pattern, a lattice pattern, or a thin film having a middle or a middle thickness of transmittance. When the slit pattern is used, it is preferable that the width of the slit and the interval between the slits are smaller than the resolution of the exposure apparatus used in the photolithography process. Another example is to use a photoresist film capable of reflowing. That is, a reflowable photoresist pattern is formed using a conventional mask having only a transparent region and a light-shielding region, and then reflowed to flow into a region where the photoresist film remains, thereby forming a thin portion.

Next, as shown in FIG. 7C, the second metal film 170q and the first metal film 170p are etched using the first photoresist pattern 400a and 400b as a mask to form a second metal pattern 174b And the first metal pattern 174a are formed and the blocking film 160 and the semiconductor film 150 are etched to form the blocking pattern 167 and the semiconductor layer 154. [

Thereafter, as shown in Fig. 7D, the first photoresist pattern 400b of the channel portion is etched back. At this time, the first photoresist pattern 400a of another portion is partially removed to become the second photoresist pattern 400c having a reduced width of the photoresist pattern.

Next, the second metal pattern 174b and the first metal pattern 174a are etched using the second photoresist pattern 400c as a mask to form the upper films 173b and 175b and the lower films 173a and 175a The source electrode 173 and the drain electrode 175 are completed.

Thereafter, the second photoresist pattern 400c is removed and the blocking pattern 167 not covered with the source electrode 173 and the drain electrode 175 is oxidized to form a gap between the source electrode 173 and the drain electrode 175 A barrier layer 164 made of silicon oxide (SiOx) is formed. Thus, the blocking pattern 167 has the first portions 163 and 165 covered with the data line 171 or the source electrode 173 and the drain electrode 175 and the data lines 171 and 171, Or a second portion 164 that is not covered by the source electrode 173 and the drain electrode 175.

The first portion 163,165 of the barrier layer 163,164,165 may comprise amorphous silicon or silicide and the second portion 164 of the barrier layer may comprise silicon oxide (SiOx) .

As such, the barrier layer 164, which is disposed over the semiconductor layer 154 and serves to prevent damage to the semiconductor layer 154, is formed by stacking and oxidizing the silicon layer without additional mask, Can be reduced.

Next, as shown in Figs. 8 and 9, a protective film 180 is laminated on the blocking layer 164, the data line 171 and the drain electrode 175, and a contact hole (not shown) for exposing the drain electrode 175 185 are formed.

Thereafter, as shown in FIGS. 1 and 2, a metal layer is laminated and then photolithographically etched to complete the pixel electrode 191 connected to the drain electrode 175 through the contact hole 185.

Since the semiconductor layer, the barrier layer, the source electrode, and the drain electrode are formed at the same time by using one mask, the semiconductor layer, the barrier layer, the source electrode, and the drain electrode are formed using different masks The manufacturing cost is lower than that in the case of forming, and the manufacturing process is simplified.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, Of the right.

Claims (10)

A gate electrode disposed on the insulating substrate,
A gate insulating film disposed on the gate electrode,
An oxide semiconductor disposed on the gate insulating film,
A barrier layer disposed on the oxide semiconductor,
A source electrode and a drain electrode disposed on the blocking layer,
A protective film disposed on the source electrode and the drain electrode, and
And a pixel electrode arranged on the protective film,
Wherein the blocking layer includes a first portion covered with the source and drain electrodes and a second portion not covered with the source and drain electrodes,
Wherein the barrier layer comprises silicon, the first portion and the second portion comprise different materials,
Wherein the first portion of the barrier layer is a silicide and the second portion of the barrier layer comprises silicon oxide (SiOx)
Wherein the upper surface of the oxide semiconductor layer is fluorinated.
The method of claim 1,
Wherein the oxide semiconductor layer comprises GIZO.
3. The method of claim 2,
Wherein the oxide semiconductor layer is a double film structure of a top film including a lower film including GIZO having a relatively high indium content and GIZO having a relatively low indium content.
4. The method of claim 3,
Wherein the source electrode and the drain electrode are a double film structure including a lower film and an upper film.
5. The method of claim 4,
Wherein the lower film comprises titanium (Ti), and the upper film comprises copper (Cu).
Forming a gate electrode on the insulating substrate,
Forming a gate insulating film on the gate electrode,
Forming an oxide semiconductor on the gate insulating film,
Forming a barrier layer comprising silicon on the oxide semiconductor,
Forming a source electrode and a drain electrode on the blocking layer,
Forming a protective film on the source electrode and the drain electrode, and
And forming a pixel electrode on the protective film,
The step of forming the oxide semiconductor, the step of forming the blocking layer, and the step of forming the source electrode and the drain electrode comprise a single photolithography process,
Wherein the blocking layer includes a first portion covered with the source and drain electrodes and a second portion not covered with the source and drain electrodes,
Wherein the first portion and the second portion comprise different materials,
Wherein the first portion of the barrier layer is a silicide and the second portion of the barrier layer comprises silicon oxide (SiOx)
Wherein the upper surface of the oxide semiconductor layer is fluorinated.
The method of claim 6,
The step of forming the oxide semiconductor, the step of forming the blocking layer, and the step of forming the source electrode and the drain electrode
On the gate insulating film,
Stacking an oxide semiconductor film,
Stacking a barrier film including silicon on the oxide semiconductor film,
Laminating a metal layer on the blocking layer,
Forming a first photoresist pattern having a different height on the metal layer,
Etching the metal layer using the first photoresist pattern as an etching mask, etching the barrier film and the semiconductor film,
Forming a second photoresist pattern by lowering the height of the first photoresist pattern;
Etching the first metal layer using the second photoresist pattern as an etching mask, and
And oxidizing the blocking film using the secondarily etched metal layer as a mask.
8. The method of claim 7,
Wherein the oxidized barrier layer is a second portion of the barrier layer.
The method of claim 6,
Wherein the oxide semiconductor layer comprises GIZO.
The method of claim 9,
Wherein the oxide semiconductor layer is a double film structure of a top film including a lower film including GIZO having a relatively high indium content and GIZO having a relatively low indium content.

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