KR101800893B1 - Liquid crystal display - Google Patents

Abstract

The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device which includes a data driving circuit for supplying a data voltage of a first color having a first polarity to a first data line and a data voltage of a second color having a second polarity to a second data line in; And a gate driving circuit for sequentially supplying gate pulses synchronized with the first and second data voltages to the gate lines. Each of the pixels includes a plurality of sub-pixels. The subpixels connected to the first data line in a zigzag manner are sequentially supplied with the data voltages of the first color having the first polarity through the first data lines during the one frame period. And the subpixels connected to the second data line in the jig jig shape are sequentially supplied with the data voltages of the second color having the second polarity through the second data line during the one frame period.

Description

[0001] LIQUID CRYSTAL DISPLAY [0002]

The present invention relates to a liquid crystal display device.

The liquid crystal display device can be downsized as compared with a cathode ray tube (CRT), and is applied to a display device in a portable information device, an office machine, a computer, and the like, and is rapidly applied to a television, thereby quickly replacing a cathode ray tube.

The liquid crystal display device includes a liquid crystal display panel, a backlight unit for irradiating light to the liquid crystal display panel, a source drive integrated circuit (IC) for supplying a data voltage to the data lines of the liquid crystal display panel, A gate drive IC for supplying a gate pulse (or a scan pulse) to scan lines (or scan lines), a control circuit for controlling the ICs, a light source driving circuit for driving a light source of the backlight unit, and the like.

The applicant of the present application filed a Korean patent application No. 10-2002-0021792 (2002.04.20), No. 10-2002-0021795 (2002.04.20), No. 10-2002-0070305 (November 11, 2002) (Thin Film Transistor) arranged in the column direction so that the liquid crystal cells arranged in a zigzag form in the column direction (or the vertical line direction) of the pixel array share the same data line through the pixel array (Hereinafter referred to as "Z inversion liquid crystal display device").

The Z-inversion liquid crystal display device can supply the data voltages output from the source drive IC of the version with a column as a column to the data lines of the liquid crystal display panel and drive the liquid crystal cells of the liquid crystal display panel with the dot inversion. The source drive ICs of the column type, which is a column type, supply data voltages of opposite polarities to neighboring data lines, maintaining the polarity of the data voltage for one frame period. In the dot-in version, the polarities of the data voltages charged in the left and right liquid crystal cells are opposite to each other, and the polarities of the data voltages charged in the upper and lower liquid crystal cells are opposite to each other.

Since the polarity of the data voltage output from the source drive IC is maintained to be the same during one frame period, the Z inversion liquid crystal display device can reduce the heat generation and power consumption of the source drive IC, And the flicker can be minimized by reversing the polarity of the voltage to a dot-inversion form.

However, in the Z-inversion type liquid crystal display device, when the voltage difference of the sub-pixel data voltages continuously supplied through the same data line increases, the power consumption reduction effect becomes small. Here, the subpixel data voltages continuously supplied through the same data line are data voltages of different colors. Conventional Z-inversion liquid crystal display devices include data lines in which a red data voltage and a green data voltage are alternately supplied, and data lines in which a blue data voltage and a green data voltage are alternately supplied. Therefore, when the input image data having large consensus of the red data, the green data, and the blue data in the neighboring pixels is input to the Z-inversion liquid crystal display device, the swing width of the data voltage output from the source drive IC becomes large, Power consumption and heat generation increase.

The present invention provides a liquid crystal display device capable of reducing power consumption and heat generation of a source drive IC even when image data having a large gray-scale difference between data of different colors is displayed in neighboring pixels.

A liquid crystal display device of the present invention includes: a liquid crystal display panel including data lines, gate lines intersecting with the data lines, TFTs, and a plurality of pixels; A data driving circuit for supplying a data voltage of a first color having a first polarity to a first data line and a data voltage of a second color having a second polarity to a second data line during one frame period; And a gate driving circuit for sequentially supplying a gate pulse synchronized with the first and second data voltages to the gate lines. Each of the pixels includes a plurality of sub-pixels. The subpixels connected to the first data line in a zigzag manner are sequentially supplied with the data voltages of the first color having the first polarity through the first data lines during the one frame period. And the subpixels connected to the second data line in the jig jig form are sequentially supplied with the data voltage of the second color having the second polarity through the second data line during the one frame period.
The leftmost data line and the rightmost data line among the data lines are commonly connected to one output channel of the data driving circuit. A data voltage of the same color having the same polarity is supplied to the leftmost data line and the leftmost data line through one output channel in the data driving circuit.

Since the subpixels connected to one data line are arranged with subpixels of the same color and supply data voltages of the same color having the same polarity to the data lines during one frame period, Power consumption and heat generation of the data driving circuit can be minimized even when displaying image data having a large difference in gray scale between the data.

1 is a block diagram showing a liquid crystal display device according to an embodiment of the present invention.
FIG. 2 is a view showing a first embodiment of the pixel array shown in FIG. 1; FIG.
3 is a diagram showing an example in which the data line arranged at the leftmost end and the data line arranged at the rightmost end are connected in common to one output channel formed in the same source drive IC.
4 is a view showing a second embodiment of the pixel array shown in FIG.
5 is a waveform diagram showing the data voltages supplied to the data lines of the pixel array shown in Figs. 2 and 4. Fig.
FIG. 6 is a view showing a third embodiment of the pixel array shown in FIG. 1. FIG.
7 is a view showing a fourth embodiment of the pixel array shown in FIG.
8 is a waveform diagram showing data voltages supplied to the data lines of the pixel array shown in Figs. 6 and 7. Fig.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

Referring to FIG. 1, a liquid crystal display device according to an embodiment of the present invention includes a liquid crystal display panel, a source drive IC 12, a gate driving circuit 13, a timing controller 11, and the like. A backlight unit for uniformly irradiating light to the liquid crystal display panel may be disposed below the liquid crystal display panel.

The liquid crystal display panel includes an upper glass substrate and a lower glass substrate facing each other with a liquid crystal layer interposed therebetween. The liquid crystal display panel includes a pixel array 10 for displaying video data. The pixel array 10 includes liquid crystal cells arranged in a matrix form by an intersection structure of data lines and gate lines to display video data. The pixel array 10 includes TFTs formed at intersections of data lines and gate lines, and pixel electrodes connected to TFTs. The TFTs of the pixel array 10 are arranged in a zigzag form in the column direction (or the data line direction). Each of the liquid crystal cells of the pixel array 10 is driven by the voltage of the pixel electrode that charges the data voltage through the TFT and the voltage difference of the common electrode to which the common voltage is applied so as to adjust the transmission amount of light, Lt; / RTI > The subpixels of the same color arranged in the neighboring columns in the pixel array 10 are connected to the same data line. The pixel array 10 may be implemented in various forms as shown in FIGS. 2, 5, 6, 8, and the like.

On the upper glass substrate of the liquid crystal display panel, a black matrix, a color filter, and a common electrode are formed. The common electrode is formed on the upper glass substrate in the case of a vertical field driving method such as a TN (Twisted Nematic) mode and a VA (Vertical Alignment) mode. In the IPS (In-Plane Switching) mode and the FFS (Fringe Field Switching) And is formed on the lower glass substrate together with the pixel electrode in the case of the same horizontal electric field driving method.

An alignment film is formed on each of the upper glass substrate and the lower glass substrate of the liquid crystal display panel to attach a polarizing plate and set a pre-tilt angle of the liquid crystal.

The liquid crystal mode of the liquid crystal display panel applicable to the present invention can be implemented not only in the TN mode, the VA mode, the IPS mode, and the FFS mode, but also in any liquid crystal mode. Further, the liquid crystal display device of the present invention can be implemented in any form such as a transmissive liquid crystal display device, a transflective liquid crystal display device, a reflective liquid crystal display device, and the like. In a transmissive liquid crystal display device and a transflective liquid crystal display device, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The source drive ICs 12 are mounted on a TCP (Tape Carrier Package) 15 and bonded to a lower glass substrate of a liquid crystal display panel by a TAB (Tape Automated Bonding) process. A source PCB (Printed Circuit Board) Respectively. The source drive ICs 12 may be bonded on the lower glass substrate of the liquid crystal display panel by a COG (Chip On Glass) process. The data output channels of each of the source drive ICs 12 are connected 1: 1 to the data lines of the pixel array 10.

Each of the source drive ICs 12 receives digital video data from the timing controller 11. The source drive ICs 12 convert the digital video data to positive / negative analog data voltages in response to a source timing control signal from the timing controller 11 and output the data to the data lines . The source drive ICs 12 supply the data voltages of opposite polarities to the neighboring data lines under the control of the timing controller 11 and supply the polarities of the data voltages supplied to the respective data lines to the same . Each of the source drive ICs 12 successively supplies the same color subpixel data voltages that maintain the same polarity for one frame period to the same data line. And the source drive ICs 12 maintain the polarity of the data voltages in units of one frame period. Thus, the source drive ICs 12 may be implemented as a source drive IC of a version with a column type.

The gate drive circuit 13 sequentially supplies gate pulses (or scan pulses) to the gate lines of the pixel array in response to a gate timing control signal from the timing controller 11. [ The gate driver circuit 13 is mounted on a TCP (Tape Carrier Package) and bonded to a lower glass substrate of a liquid crystal display panel by a TAB process, or is formed on a lower glass substrate simultaneously with a pixel array by a GIP (Gate In Panel) Can be formed directly. The gate drive circuit 13 may be disposed on either side of the pixel array 10 or on one side of the pixel array 10. [

The timing controller 11 supplies the source drive ICs 12 with digital video data input from an external host system. The timing controller 11 generates a source timing control signal for controlling the operation timing of the source drive ICs 12 and a gate timing control signal for controlling the operation timing of the gate drive circuit 13. [ The timing controller 11 is mounted on the control PCB 16. The control PCB 16 and the source PCB 14 are connected through a flexible circuit board 17 such as a flexible flat cable (FFC) or a flexible printed circuit (FPC).

Fig. 2 is an equivalent circuit diagram showing a first embodiment of the pixel array 10. Fig.

2, the pixel array 10 includes m (m is a positive integer) data lines S1 to Sm, n (n is a positive integer) gate lines G1 to Gn, (PIX). Each of the pixels PIX includes a red subpixel R + / R-, a green subpixel G + / G-, and a blue subpixel B + / B-. The pixels PIX are arranged in the display line with the red subpixel R + / R-, the green subpixel G + / G-, and the blue subpixel B + / B- (R + / R-), a green subpixel (G + / G-), and a blue subpixel (G + / G-) disposed on two neighboring display lines such as two display lines located at the right center of FIG. Pixel (B + / B-). The liquid crystal cell of the sub pixel includes a pixel electrode and a TFT. In Fig. 2, "R" is a liquid crystal cell of a red subpixel filled with a red data voltage and "G" is a liquid crystal cell of a green subpixel filled with a green data voltage. And "B" is a liquid crystal cell of a blue subpixel filled with a blue data voltage. "+" Means a liquid crystal cell of a subpixel to which a positive data voltage is supplied, and "-" means a liquid crystal cell of a subpixel to which a negative data voltage is supplied.

2, each of the odd-numbered display lines LINE # 1 and LINE # n-1 includes first and second sub-pixels. The first sub-pixel includes a first TFT (T11) and a first pixel electrode (P11). The second sub-pixel includes a second TFT T12 and a second pixel electrode P12. Each of the even display lines LINE # 2 and LINE # n includes third and fourth sub-pixels. The third sub-pixel includes a third TFT T21 and a third pixel electrode P21. The fourth sub-pixel includes a fourth TFT (T22) and a fourth pixel electrode (P22). Each TFT supplies a data voltage from the data line to the pixel electrode in response to a gate pulse from the gate line. In Fig. 2, arrows indicate the charging sequence of the data voltage.

The first TFT T11 applies a data voltage supplied through the i-th (i is a positive integer equal to or less than m) data line in response to a gate pulse from the gate line of j (j is a positive integer of n or less) 1 pixel electrode P11. The first pixel electrode P11 is arranged on the left side of the i-th data line. The gate electrode of the first TFT (T11) is connected to the j-th gate line. The drain electrode of the first TFT T11 is connected to the i-th data line, and the source electrode thereof is connected to the first pixel electrode P11.

The second TFT T12 supplies the data voltage supplied through the (i + 1) th data line to the second pixel electrode P12 in response to the gate pulse from the j-th gate line. And the second pixel electrode P12 is disposed on the left side of the (i + 1) th data line. The gate electrode of the second TFT (T12) is connected to the j-th gate line. The drain electrode of the second TFT T12 is connected to the (i + 1) th data line, and the source electrode thereof is connected to the second pixel electrode P12.

The third TFT T21 supplies the data voltage supplied through the i-th data line to the third pixel electrode P21 in response to the gate pulse from the (j + 1) -th gate line. And the third pixel electrode P21 is disposed on the right side of the i-th data line. The gate electrode of the third TFT (T21) is connected to the (j + 1) -th gate line. The drain electrode of the third TFT (T21) is connected to the i-th data line, and the source electrode thereof is connected to the third pixel electrode (P21).

The fourth TFT T22 supplies the data voltage supplied through the (i + 1) th data line to the fourth pixel electrode P22 in response to the gate pulse from the (j + 1) th gate line. And the fourth pixel electrode P22 is arranged on the right side of the (i + 1) th data line. The gate electrode of the fourth TFT (T22) is connected to the (j + 1) -th gate line. The drain electrode of the fourth TFT T22 is connected to the (i + 1) th data line, and the source electrode thereof is connected to the fourth pixel electrode P22.

The third subpixel of the second display line LINE # 2 arranged in the diagonal direction on the lower right side of the first subpixel of the first display line LINE # 1, the third subpixel of the third subpixel The first subpixel of the third display line arranged in the lower left diagonal direction and the third subpixel of the fourth display line arranged in the diagonal direction on the lower right side of the first subpixel are arranged in one frame period The sub pixel data voltages of the first color having the same polarity are continuously charged. The first color is any one of red (R), green (G), and blue (B). The second sub-pixel of the first display line LINE # 1, the fourth sub-pixel of the second display line LINE # 2 arranged in the diagonal direction below the right of the second sub-pixel, The second subpixel of the third display line arranged in the lower left diagonal direction and the fourth subpixel of the fourth display line arranged in the diagonal direction on the lower right side of the second subpixel are arranged in one frame period Pixel data voltages of the second color having the same polarity. The second color is one color other than the first color among red (R), green (G), and blue (B). Therefore, the liquid crystal cells arranged in the jig jig shape in the two columns and sharing the same data line sequentially charge the same-color data voltages having the same polarity in one frame period.

Generally, in a single frame image, there is almost no difference in the gradation between red data in neighboring pixels that are not boundary portions. Likewise, in one frame image, there is almost no difference in gray level between green data in neighboring pixels other than the boundary, and there is little difference in gray level between blue data. In the pixel array 10 of the liquid crystal display panel as shown in Fig. 2, one data line is connected to subpixels of the same color. The source drive ICs 12 repeatedly output the same-color data voltage having the same polarity to one data line. Therefore, the liquid crystal display device of the present invention arranges the subpixels connected to one data line with the same color subpixels and supplies the same-color data voltages having the same polarity to the data line for one frame period, The power consumption and heat generation of the source drive ICs 12 can be minimized even when image data with a large gray-scale level difference between data of different colors is displayed.

2, the first data line S1 disposed on the leftmost side and the m th data line Sm disposed on the rightmost side of FIG. 2 are connected to one output channel And can be commonly connected. The present invention can prevent the increase of the number of output channels of the source drive IC by connecting the first and the mth data lines Sl and Sm in common to the same output channel in the same source drive IC, The load conditions of the arranged data lines S1 and Sn and the data lines of the other data lines can be made equal to each other, thereby preventing the luminance from varying at both ends of the pixel array.

3 shows an example in which the first data line S1 disposed at the leftmost end and the m th data line Sm disposed at the rightmost end are commonly connected to one output channel formed in the same source drive IC 12 Fig.

Referring to FIG. 3, the liquid crystal display of the present invention includes a connection line 111 connecting the first data line S1 and the m data line Sm. In this liquid crystal display device, other components except for the connection line 111 are substantially the same as those of the above-described embodiment, and therefore, the same reference numerals as in the above-described embodiments are attached, and a detailed description thereof will be omitted.

The connection line 111 is a metal wiring connected to the first output channel of the first source drive IC 12 for supplying the data voltage through the data pad formed at the end of the first data line S1 . The connection line 111 is electrically connected to the first data line S1 through the TCP 15 bonded to the upper left of the liquid crystal display panel, the source PCB 14, and the TCP 15 bonded to the upper right of the liquid crystal display panel. ) And the mth data line (Sm), and also commonly connects the data lines (S1, Sm) to the first output channel of the first source drive IC (12). Thus, the first source driver IC 12 can supply the data voltage to the first and the m-th data lines Sl and Sm through the first output channel.

Fig. 4 is an equivalent circuit diagram showing a second embodiment of the pixel array 10. Fig.

Referring to Fig. 4, the pixel array 10 includes m data lines S1 to Sm, n gate lines G1 to Gn, and a plurality of pixels PIX. Each of the pixels PIX includes a red subpixel R + / R-, a green subpixel G + / G-, and a blue subpixel B + / B-. The pixels PIX include red subpixels (R + / R-), green subpixels (G + / G-) and blue subpixels (B + / B-) arranged in one display line, (R + / R-), a green subpixel (G + / G-), and a blue subpixel (B + / B-) disposed on the display lines. The liquid crystal cell of the sub pixel includes a pixel electrode and a TFT. In Fig. 4, "R" is a liquid crystal cell of a red subpixel filled with a red data voltage and "G" is a liquid crystal cell of a green subpixel filled with a green data voltage. And "B" is a liquid crystal cell of a blue subpixel filled with a blue data voltage. "+" Means a liquid crystal cell of a subpixel to which a positive data voltage is supplied, and "-" means a liquid crystal cell of a subpixel to which a negative data voltage is supplied.

In Fig. 4, each of the odd-numbered display lines LINE # 1, LINE # n-1 includes first and second sub-pixels. The first sub-pixel includes a first TFT (T31) and a first pixel electrode (P31). The second sub-pixel includes a second TFT (T32) and a second pixel electrode (P32). Each of the even display lines LINE # 2 and LINE # n includes third and fourth sub-pixels. The third sub-pixel includes a third TFT T41 and a third pixel electrode P41. The fourth sub-pixel includes a fourth TFT (T42) and a fourth pixel electrode (P42). Each TFT supplies a data voltage from the data line to the pixel electrode in response to a gate pulse from the gate line. In Fig. 4, arrows indicate the charging sequence of the data voltage.

The first TFT T31 supplies the data voltage supplied through the i-th data line to the first pixel electrode P31 in response to the gate pulse from the j-th gate line. The first pixel electrode P31 is arranged on the right side of the i-th data line. The gate electrode of the first TFT (T31) is connected to the j-th gate line. The drain electrode of the first TFT (T31) is connected to the i-th data line, and the source electrode thereof is connected to the first pixel electrode (P31).

The second TFT T32 supplies the data voltage supplied through the (i + 1) th data line to the second pixel electrode P32 in response to the gate pulse from the j-th gate line. And the second pixel electrode P32 is disposed on the right side of the (i + 1) th data line. The gate electrode of the second TFT (T32) is connected to the j-th gate line. The drain electrode of the second TFT (T32) is connected to the i-th data line, and the source electrode thereof is connected to the second pixel electrode (P32).

The third TFT T41 supplies the data voltage supplied through the ith data line to the third pixel electrode P41 in response to the gate pulse from the (j + 1) th gate line. And the third pixel electrode P41 is disposed on the left side of the i-th data line. The gate electrode of the third TFT T41 is connected to the (j + 1) -th gate line. The drain electrode of the third TFT T41 is connected to the i-th data line, and the source electrode thereof is connected to the third pixel electrode P41.

The fourth TFT T42 supplies the data voltage supplied through the (i + 1) th data line to the fourth pixel electrode P42 in response to the gate pulse from the (j + 1) th gate line. And the fourth pixel electrode P42 is disposed on the left side of the (i + 1) th data line. The gate electrode of the fourth TFT (T42) is connected to the (j + 1) -th gate line. The drain electrode of the fourth TFT T42 is connected to the (i + 1) th data line, and the source electrode thereof is connected to the fourth pixel electrode P42.

The first sub-pixel of the first display line LINE # 1, the third sub-pixel of the second display line LINE # 2 disposed in the lower left-hand diagonal direction of the first sub-pixel, The first subpixel of the third display line arranged in the lower right diagonal direction and the third subpixel of the fourth display line arranged in the lower left diagonal direction of the first subpixel are arranged in a frame period The sub pixel data voltages of the first color having the same polarity are continuously charged. The first color is any one of red (R), green (G), and blue (B). The second subpixel of the first display line LINE # 1, the fourth subpixel of the second display line LINE # 2 arranged in the lower left diagonal direction of the second subpixel, The second subpixel of the third display line arranged in the lower right diagonal direction and the fourth subpixel of the fourth display line arranged in the lower left diagonal direction of the second subpixel are arranged in a frame period Pixel data voltages of the second color having the same polarity. The second color is one color other than the first color among red (R), green (G), and blue (B). Accordingly, the liquid crystal cells arranged in the jig jig shape in the neighboring two columns and sharing the same data line sequentially charge the same-color data voltages having the same polarity in one frame period.

Generally, in a single frame image, there is almost no difference in the gradation between red data in neighboring pixels that are not boundary portions. Likewise, in one frame image, there is almost no difference in gray level between green data in neighboring pixels other than the boundary, and there is little difference in gray level between blue data. In the pixel array 10 of the liquid crystal display panel as shown in Fig. 4, one data line is connected to subpixels of the same color. The source drive ICs 12 repeatedly output the same-color data voltage having the same polarity to one data line. Therefore, the liquid crystal display device of the present invention arranges the subpixels connected to one data line with the same color subpixels and supplies the same-color data voltages having the same polarity to the data line for one frame period, The power consumption and heat generation of the source drive ICs 12 can be minimized even when image data with a large gray-scale level difference between data of different colors is displayed.

5 is a waveform diagram showing data voltages supplied to the data lines S1 to Sm of the pixel array 10 shown in Figs. 2 and 4. Fig.

5, the source drive IC 12 supplies the negative polarity blue data voltage (B-) to the first and the m-th data (B-) during the Nth (N is a positive integer) frame period under the control of the timing controller 11. [ To the lines S1 and Sm. The source drive IC 12 supplies the positive red data voltage R + to the second data lines S2 during the N-th frame period under the control of the timing controller 11 and the negative green data voltage G- To the third data lines S3. Then, the source drive IC 12 supplies the positive green data voltage G + to the (m-1) th data lines Sm-1 for the N-th frame period under the control of the timing controller 11. [ Subsequently, the source drive IC 12 inverts the polarities of the data voltages R + / R-, G + / G-, and B + / B- in the (N + 1) -th frame period under the control of the timing controller 11, The polarity is maintained for one frame period.

The gate drive circuit 13 sequentially applies a gate pulse (or a scan pulse) synchronized with a data voltage supplied to the data lines S1 to Sm to the gate lines G1 to Gn under the control of the timing controller 11 Supply.

Meanwhile, the liquid crystal display of the present invention may or may not perform charge sharing among data voltages continuously supplied to the data lines S1 to Sm. Charge sharing short-circuits neighboring data lines during a horizontal blank period between data voltages to apply an average voltage of the positive and negative data voltages to the data lines as indicated by the dotted line . The present invention can continuously supply the data voltages of the same polarity and the same gray level to the data lines and minimize the number of transitions as indicated by the solid line when charge sharing is not performed. Therefore, the liquid crystal display device of the present invention can further reduce power consumption when charge sharing is not performed.

Fig. 6 is an equivalent circuit diagram showing a third embodiment of the pixel array 10. Fig.

Referring to FIG. 6, the pixel array 10 includes m data lines S1 to Sm, n gate lines G1 to Gn, and a plurality of pixels PIX. Each of the pixels PIX includes a red subpixel R + / R-, a green subpixel G + / G-, and a blue subpixel B + / B-. The pixels PIX include red subpixels (R + / R-), green subpixels (G + / G-) and blue subpixels (B + / B-) arranged in one display line, (R + / R-), a green subpixel (G + / G-), and a blue subpixel (B + / B-) disposed on the display lines. The liquid crystal cell of the sub pixel includes a pixel electrode and a TFT. 6, "R" is a liquid crystal cell of a red subpixel filled with a red data voltage, and "G" is a liquid crystal cell of a green subpixel filled with a green data voltage. And "B" is a liquid crystal cell of a blue subpixel filled with a blue data voltage. "+" Means a liquid crystal cell of a subpixel to which a positive data voltage is supplied, and "-" means a liquid crystal cell of a subpixel to which a negative data voltage is supplied.

6, each of the odd-numbered display lines LINE # 1 and LINE # n-1 includes first and second sub-pixels. The first sub-pixel includes a first TFT (T51) and a first pixel electrode (P51). The second sub-pixel includes a second TFT (T52) and a second pixel electrode (P52). Each of the even display lines LINE # 2 and LINE # n includes third and fourth sub-pixels. The third sub-pixel includes a third TFT (T61) and a third pixel electrode (P61). The fourth sub-pixel includes a fourth TFT (T62) and a fourth pixel electrode (P62). Each TFT supplies a data voltage from the data line to the pixel electrode in response to a gate pulse from the gate line. In Fig. 6, arrows indicate the charging sequence of the data voltage.

The first TFT T51 supplies the data voltage supplied through the i-th data line to the first pixel electrode P51 in response to the gate pulse from the j-th gate line. The first pixel electrode P51 is arranged on the right side of the i-th data line. The gate electrode of the first TFT (T51) is connected to the j-th gate line. The drain electrode of the first TFT (T51) is connected to the i-th data line, and its source electrode is connected to the first pixel electrode (P51).

The second TFT T52 supplies the data voltage supplied through the (i + 1) th data line to the second pixel electrode P52 in response to the gate pulse from the j-th gate line. And the second pixel electrode P52 is disposed on the right side of the (i + 1) th data line. The gate electrode of the second TFT (T52) is connected to the j-th gate line. The drain electrode of the second TFT T52 is connected to the (i + 1) th data line, and the source electrode thereof is connected to the second pixel electrode P52.

The third TFT T61 supplies a data voltage supplied through the ith data line to the third pixel electrode P61 in response to the gate pulse from the (j + 1) th gate line. And the third pixel electrode P61 is disposed on the left side of the i-th data line. The gate electrode of the third TFT (T61) is connected to the (j + 1) -th gate line. The drain electrode of the third TFT T61 is connected to the i-th data line, and the source electrode thereof is connected to the third pixel electrode P61.

The fourth TFT T62 supplies the data voltage supplied through the (i + 1) th data line to the fourth pixel electrode P62 in response to the gate pulse from the (j + 1) th gate line. And the fourth pixel electrode P62 is disposed on the left side of the (i + 1) th data line. The gate electrode of the fourth TFT (T62) is connected to the (j + 1) -th gate line. The drain electrode of the fourth TFT T62 is connected to the (i + 1) th data line, and the source electrode thereof is connected to the fourth pixel electrode P62.

The connection relationship between the data lines S1 to Sm, the gate lines G1 to Gn, the TFTs T51 to T62 and the pixel electrodes P51 to P62 in the pixel array 10 shown in Fig. Are substantially the same as those of the pixel array shown in Fig. 4, and the colors of the subpixels are different. Therefore, the driving method of the pixel array shown in FIG. 6 differs from the driving method of the pixel array shown in FIG. 4 only in the polarity of the data voltage and the color of the subpixel data supplied to the data lines Sl to Sm same.

Fig. 7 is an equivalent circuit diagram showing a fourth embodiment of the pixel array 10. Fig.

Referring to FIG. 7, the pixel array 10 includes m data lines S1 to Sm, n gate lines G1 to Gn, and a plurality of pixels PIX. Each of the pixels PIX includes a red subpixel R + / R-, a green subpixel G + / G-, and a blue subpixel B + / B-. The pixels PIX include red subpixels (R + / R-), green subpixels (G + / G-) and blue subpixels (B + / B-) arranged in one display line, (R + / R-), a green subpixel (G + / G-), and a blue subpixel (B + / B-) disposed on the display lines. The liquid crystal cell of the sub pixel includes a pixel electrode and a TFT. 7, "R" is a liquid crystal cell of a red subpixel filled with a red data voltage, and "G" is a liquid crystal cell of a green subpixel filled with a green data voltage. And "B" is a liquid crystal cell of a blue subpixel filled with a blue data voltage. "+" Means a liquid crystal cell of a subpixel to which a positive data voltage is supplied, and "-" means a liquid crystal cell of a subpixel to which a negative data voltage is supplied.

7, each of the odd-numbered display lines LINE # 1 and LINE # n-1 includes first and second sub-pixels. The first sub-pixel includes a first TFT (T71) and a first pixel electrode (P71). The second sub-pixel includes a second TFT (T72) and a second pixel electrode (P72). Each of the even display lines LINE # 2 and LINE # n includes third and fourth sub-pixels. The third sub-pixel includes a third TFT T81 and a third pixel electrode P81. The fourth sub-pixel includes a fourth TFT (T82) and a fourth pixel electrode (P82). Each TFT supplies a data voltage from the data line to the pixel electrode in response to a gate pulse from the gate line. In Fig. 7, arrows indicate the charging sequence of the data voltage.

The first TFT (T71) supplies the data voltage supplied through the i-th data line to the first pixel electrode (P71) in response to the gate pulse from the j-th gate line. The first pixel electrode P71 is arranged on the left side of the i-th data line. The gate electrode of the first TFT (T71) is connected to the j-th gate line. The drain electrode of the first TFT (T71) is connected to the i-th data line, and the source electrode thereof is connected to the first pixel electrode (P71).

The second TFT T72 supplies the data voltage supplied through the (i + 1) th data line to the second pixel electrode P72 in response to the gate pulse from the j-th gate line. And the second pixel electrode P72 is disposed on the left side of the (i + 1) th data line. The gate electrode of the second TFT (T72) is connected to the j-th gate line. The drain electrode of the second TFT T72 is connected to the (i + 1) th data line, and the source electrode thereof is connected to the second pixel electrode P72.

The third TFT T81 supplies a data voltage supplied through the ith data line to the third pixel electrode P81 in response to the gate pulse from the (j + 1) -th gate line. And the third pixel electrode P81 is disposed on the right side of the i-th data line. The gate electrode of the third TFT (T81) is connected to the (j + 1) -th gate line. The drain electrode of the third TFT (T81) is connected to the i-th data line, and the source electrode thereof is connected to the third pixel electrode (P81).

The fourth TFT T82 supplies the data voltage supplied through the (i + 1) th data line to the fourth pixel electrode P82 in response to the gate pulse from the (j + 1) th gate line. And the fourth pixel electrode P82 is disposed on the right side of the (i + 1) th data line. The gate electrode of the fourth TFT (T82) is connected to the (j + 1) -th gate line. The drain electrode of the fourth TFT T82 is connected to the (i + 1) th data line, and the source electrode thereof is connected to the fourth pixel electrode P82.

The connection relationship between the data lines S1 to Sm, the gate lines G1 to Gn, the TFTs T71 to T82, and the pixel electrodes P71 to P82 in the pixel array 10 shown in Fig. Are substantially the same as those of the pixel array shown in Fig. 2, and the colors of the subpixels are different. Therefore, the driving method of the pixel array shown in FIG. 7 differs from the driving method of the pixel array shown in FIG. 2 only in the polarity of the data voltage and the color of the subpixel data supplied to the data lines S1- same.

FIG. 8 is a waveform diagram showing data voltages supplied to the data lines S1 to Sm of the pixel array 10 shown in FIGS. 6 and 7. FIG.

8, the source drive IC 12 applies a positive red data voltage R + to the first and the m-th data lines S1 and Sm during the N-th frame period under the control of the timing controller 11, Supply. The source drive IC 12 supplies the negative data voltage G- to the second data lines S2 during the N frame period under the control of the timing controller 11 and the positive blue data voltage B + To the third data lines S3. Then, the source driver IC 12 supplies the negative polarity blue data voltage B- to the (m-1) th data lines Sm-1 for the N frame period under the control of the timing controller 11. [ Subsequently, the source drive IC 12 inverts the polarities of the data voltages R + / R-, G + / G-, and B + / B- in the (N + 1) -th frame period under the control of the timing controller 11, The polarity is maintained for one frame period.

The gate drive circuit 13 sequentially applies a gate pulse (or a scan pulse) synchronized with a data voltage supplied to the data lines S1 to Sm to the gate lines G1 to Gn under the control of the timing controller 11 Supply.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: Pixel array 11: Timing controller
12: Source drive IC 13: Gate drive circuit

Claims (7)

A liquid crystal display panel including data lines, gate lines crossing the data lines, TFTs, and a plurality of pixels;
A data driving circuit for supplying a data voltage of a first color having a first polarity to a first data line and a data voltage of a second color having a second polarity to a second data line during one frame period; And
And a gate driving circuit for sequentially supplying gate pulses synchronized with the first and second data voltages to the gate lines,
Each of the pixels comprising a plurality of subpixels,
The subpixels connected to the first data line in a zigzag manner are sequentially supplied with a data voltage of the first color having the first polarity through the first data line during the one frame period,
The subpixels connected to the second data line in a zigzag manner are sequentially supplied with a data voltage of the second color having the second polarity through the second data line during the one frame period,
The leftmost data line and the rightmost data line among the data lines are commonly connected to one output channel of the data driving circuit,
And a data voltage of the same color having the same polarity is supplied to the leftmost data line and the rightmost data line through one output channel in the data driving circuit.
The method according to claim 1,
The sub-
First and second sub-pixels arranged in a first display line of the liquid crystal display panel; And
And third and fourth sub-pixels arranged in a second display line of the liquid crystal display panel,
The TFTs,
A first TFT for connecting a pixel electrode of the first sub-pixel to the first data line in response to a first gate pulse from the first gate line;
A second TFT for connecting the pixel electrode of the second sub-pixel to the second data line in response to the first gate pulse;
A third TFT for connecting the pixel electrode of the third sub-pixel to the first data line in response to a second gate pulse from the second gate line; And
And a fourth TFT connected to the second data line in response to the second gate pulse.
3. The method of claim 2,
Pixel electrodes of the first TFT and the first sub-pixel are disposed on the left side of the first data line,
Pixel electrodes of the second TFT and the second sub-pixel are arranged on the left side of the second data line,
Pixel electrodes of the third TFT and the third sub-pixel are disposed on the right side of the first data line,
And the pixel electrodes of the fourth TFT and the fourth sub-pixel are arranged on the right side of the second data line.
3. The method of claim 2,
Pixel electrodes of the first TFT and the first sub-pixel are arranged on the right side of the first data line,
Pixel electrodes of the second TFT and the second sub-pixel are disposed on the right side of the second data line,
Pixel electrodes of the third TFT and the third sub-pixel are disposed on the left side of the first data line,
And the pixel electrodes of the fourth TFT and the fourth sub-pixel are disposed on the left side of the second data line.
delete The method according to claim 1,
A plurality of sub-pixels connected to the first data line are supplied with only the data voltages of the first color having the first polarity during the one frame period,
A plurality of subpixels connected to the second data line are supplied with only a data voltage of a second color having the second polarity during the one frame period,
Wherein only the data voltages of the same color having the same polarity are supplied to the leftmost data line and the rightmost data line through the one output channel during the one frame period.
The method according to claim 6,
Wherein the data driving circuit continuously supplies a data voltage to the data lines without charge sharing.

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