KR101789467B1 - Fast reset apparatus of pseudo random binary sequence generator - Google Patents

Abstract

The present invention relates to a high-speed reset device for a pseudo-random binary sequence generator, wherein a fast reset device of a pseudo-random binary sequence generator according to an embodiment of the present invention includes a first reset circuit portion connected to a first input of a CML latch; And a second reset circuit part connected to a second input terminal of the CML latch, wherein the first reset circuit part and the second reset circuit part are connected to the enable terminal of the enable Signals may be input to the first and second input terminals, respectively.

Description

[0001] FAST RESET APPARATUS OF PSEUDO RANDOM BINARY SEQUENCE GENERATOR [0002]

The present invention relates to a high-speed reset device for a pseudo-random binary sequence generator, and more particularly, to an input stage of a current mode logic (CML) latch included in a PSEUDO RANDOM BINARY SEQUENCE (PRBS) A high-speed reset device of a pseudo-random binary sequence generator for resetting the PRBS signal and the ADC to initialize the synchronization between them by switching the initial condition to a desired value of 0 or 1 by inputting an enable (EN) signal .

Generally, a sequence of two numbers (or two characters), 0 and 1, is called a binary sequence. Such a binary sequence is widely used in various fields of information communication, and one of the characteristics that is frequently required among the various characteristics of the binary sequence is the random characteristic. This means that it is impossible to predict whether the next term is 0 or 1.

A PRBS (hereinafter referred to as " PRBS ") is a bit string having a pattern randomly generated in a pseudo manner, and can be used for an information protection system, a communication system, and the like.

In addition, the high-speed PRBS generator is designed using a current mode logic (CML) circuit (hereinafter referred to as " CML ") which operates internally with a low input / output voltage. Since the swing of the output signal of the internal logic circuit is small, This is possible. Such a high speed PRBS generator can operate at several tens Gb / s or more.

However, in the ultra-high speed PRBS generator, the clock signal changes with time due to jitter or the like, and it is necessary to reset the high-speed PRBS signal at a desired timing.

Specifically, the PRBS signal is different from a PLL (Phase Locked Loop) generating a sampling frequency of an ADC (Analog-to-Digital Converter). That is, the PLL generating the clock signal (e.g., 18 GHz) used to generate the PRBS signal is different from the internal PLL generating the sampling frequency (e.g., 1.25 GHz) of the ADC.

As a result, asynchronism may occur between the PRBS signal and the ADC after a lapse of a predetermined time, so it is necessary to reset the PRBS signal and the ADC to initialize the synchronization between them.

Korean Registered Patent No. 10-1239524 (Registered on February 26, 2013)

SUMMARY OF THE INVENTION An object of the present invention is to provide an apparatus and a method for generating a current mode logic (CML) latch, which includes an enable (EN) signal input to a current mode logic (CML) latch included in a PSEUDO RANDOM BINARY SEQUENCE Random binary sequence generator for resetting the PRBS signal and the ADC to initialize the synchronization between the PRBS signal and the ADC.

A fast resetting device of a fast pseudo random binary sequence generator according to an embodiment of the present invention includes a first reset circuit part connected to a first input of a CML latch; And a second reset circuit part connected to a second input terminal of the CML latch, wherein the first reset circuit part and the second reset circuit part are connected to the enable terminal of the enable Signals may be input to the first and second input terminals, respectively.

Wherein the enable signal includes a first enable signal and a second enable signal, and the first enable signal and the second enable signal are signals having a voltage difference capable of discriminating between a high level and a low level have.

The first reset circuit section includes: a first bias resistor connected to the first input terminal; A first switching unit for connecting or disconnecting a connection between the first bias resistor and a terminal to which the first EN signal is applied; And a second switching unit for connecting or disconnecting a connection between the first bias resistor and the terminal to which the first bias voltage is applied.

The second reset circuit portion includes: a second bias resistor connected to the second input terminal; A third switching unit for connecting or disconnecting a connection between the second bias resistor and a terminal to which the second EN signal is applied; And a fourth switching unit for connecting or disconnecting a connection between the second bias resistor and a terminal to which the second bias voltage is applied.

The first and second switching units may be connected in parallel, and the third and fourth switching units may be connected in parallel.

The first to fourth switching units can be switched and controlled according to an enable signal input from the outside.

Wherein the first and third switching units are ON when the enable signal is in the high state and the second and fourth switching units are in the ON state when the enable signal is in the low state, Lt; / RTI >

The enable signal may be input through a serial peripheral interface (SPI) and a shift register according to a user input.

The CML latch may be set to an output signal of a desired value between 0 and 1 by changing the level of the first and second enable signals when the first and third switching units are on.

(EN) signal is input to an input terminal of a current mode logic (CML) latch included in a PSEUDO RANDOM BINARY SEQUENCE (PRBS) generator, an initial condition is set to 0 By switching to the desired value of 1 and 1, the PRBS signal and the ADC can be reset to initialize the synchronization between them.

In addition, the present invention can reset the high-speed PRBS signal at a desired time point by controlling the input terminal of the CML latch in accordance with a user's input to set the initial condition (i.e., output signal) of the CML latch to a desired value.

In addition, the present invention can quickly adjust the phase of the PRBS signal after reset by resetting the PRBS signal at a desired time point and separately controlling initial conditions of each CML latch.

In addition, the present invention resets the output signal of the PRBS generator irrespective of the current operation of the PRBS generator, thereby eliminating the influence of continuous operation such as frequency transition of the clock signal source over time.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a structure example of a PRBS generator,
FIG. 2 is a diagram illustrating an example of a signal output from the PRBS generator of FIG. 1,
FIG. 3 illustrates an example of implementing a D-latch, which is a component of the PRBS generator of FIG. 1, as a CML latch;
4 is a block diagram illustrating a fast resetting apparatus for a fast pseudo-random binary sequence generator according to an embodiment of the present invention.
5 is a diagram for explaining a process of inputting an EN signal to a PRBS generator according to an embodiment of the present invention,
6 is a graph illustrating a result of resetting an output signal of the PRBS generator according to an input of an EN signal according to an embodiment of the present invention.

For a better understanding of the present invention, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. The embodiments of the present invention may be modified into various forms, and the scope of the present invention should not be construed as being limited to the embodiments described in detail below. The present embodiments are provided to enable those skilled in the art to more fully understand the present invention. Therefore, the shapes and the like of the elements in the drawings can be exaggeratedly expressed to emphasize a clearer description. It should be noted that in the drawings, the same members are denoted by the same reference numerals. Detailed descriptions of well-known functions and constructions which may be unnecessarily obscured by the gist of the present invention are omitted.

1 is a diagram showing an example of the structure of a PRBS generator. FIG. 1 (a) is an example of a full-rate PRBS generator, and FIG. 1 (b) is an example of a Half-rate PRBS generator.

The PRBS generator is a module that outputs a bit stream having a pattern randomly generated in a pseudo-random fashion. For example, 1, 0, 0, 1, 1, 0, 1, 0, 0, 0, 1 ... Can generate random binary sequences such as < RTI ID = 0.0 >

As shown in FIG. 1 (a), a full-rate PRBS generator may have N D-flip-flops connected in series. At this time, one D-flip-flop is implemented with two D-latches. Also, the full-rate PRBS generator shown in FIG. 1 (a) can be implemented by the Half-rate PRBS generator shown in FIG. 1 (b), in which case the operation speed of the PRBS generator doubles.

2 is a diagram illustrating an example of a signal output from the PRBS generator of FIG. 2 (a) is a graph showing a spectrum of a signal output from a PRBS generator in a time domain, and FIG. 2 (b) is a graph showing a spectrum of a signal output from a PRBS generator in a frequency domain ).

로 반복된다. The signal output from the PRBS generator (i.e., the PRBS signal)

Lt; / RTI >

은 D-플립플롭의 개수이며,

는 클록 주파수(clock frequency)이다. 또한, PRBS 신호는 클록 주파수에서 NULL을 형성하게 된다. 즉, 클록 주파수는

이다. here,

Is the number of D-flip flops,

Is the clock frequency. Also, the PRBS signal will form NULL at the clock frequency. That is, the clock frequency is

to be.

Also, the PRBS generator can be implemented as a differential CML latch capable of operating with a low input / output voltage as shown in FIG. 3, which will be described later.

FIG. 3 is a diagram illustrating an example of implementing a D-latch, which is a component of the PRBS generator of FIG. 1, as a CML latch. In this embodiment, a CML latch is implemented using a BJT as a main switch and a MOSFET as a bias circuit, but a CML latch can be implemented using a MOSFET as a main switch.

The PRBS generator shown in FIG. 3 operates at a low input / output voltage and high-speed switching is possible because the swing of the output signal is small. Such a PRBS generator can operate at an extremely high speed of, for example, 30 Gb / s or more. In this case, N may be 7 to 11, for example.

Referring to FIG. 3, the PRBS generator 1 is implemented by connecting N D-flip-flops 2 in series and the D-flip-flop 2 is implemented by two D-latches 3. Again, the D-latch 3 can be implemented with the CML latch 4. [

The CML latch 4 has a first pair 4a and a second pair (a hold pair or a cross-coupled pair 4b). The first pair 4a is activated by a clock signal and functions as a CML buffer. That is, the transistors Q1 and Q2 form a differential amplifier, and performs a latch function by varying the direction of current flow according to the clock signal.

Specifically, when the level of the clock signal is high (that is, when CP is positive and CN is negative), the first pair 4a outputs the voltage input to the input terminal IP and the voltage input to the input terminal IM The level of the output signal is switched to 1 or 0 according to the difference.

As an example, when the level of the clock signal is High, the current I _SS flows through the branch on the side of the transistor Q 1 according to the differential voltage of the input terminals IP and IM, while the current I _SS does not flow through the Q 2 side branch . In this case, the voltage of OP is V _DD , the voltage of ON is V _DD -R _D I _SS , and the difference between the voltages (ie, the voltage of OP -ON) is R _D I _SS (> 0) And the output becomes 1.

As another example, when the level of the clock signal is High, the current I _SS flows through the branch on the side of the transistor Q 2 according to the differential voltage of the input terminals IP and IM, while the current I _SS does not flow on the side of the transistor Q 1 side. In this case, the voltage of the OP is a voltage of V _DD -R _D I _SS, ON is the V _DD, both the difference between the voltage across (i.e., the voltage of the voltage of -ON OP) is -R _D I _SS (<0) And the output becomes 0.

Further, when the level of the clock signal is Low (that is, when CP is negative and CN is positive), the second pair 4b maintains the level of the output signal output from the output terminals OP and ON . At this time, the difference between the voltage of OP and the voltage of ON (ie, the voltage of OP -ON of OP) is maintained at R _D I _SS (or -R _D I _SS ).

Such a CML latch has an advantage in that it can process data at a higher speed than a CMOS static structure. These CML latches are capable of high-speed switching while consuming more power than CMOS static structures because of the need for bias currents.

Hereinafter, a fast resetting apparatus of a PRBS generator according to an embodiment of the present invention will be described.

4 is a block diagram illustrating a fast resetting apparatus for a fast pseudo-random binary sequence generator according to an embodiment of the present invention. 4 (a) shows the high-speed reset device 300, and FIG. 4 (b) shows the CML latch 200. FIG. Here, the CML latch can implement the circuit using the BJT as the main switch, the MOSFET as the bias circuit, and the CML latch using the MOSFET as the main switch.

The PRBS generator 100 according to an embodiment of the present invention includes a CML latch 200 and a fast reset device 300. [

The CML latch 200 performs the same function as that of the CML latch 4 of FIG. 3. The CML latch 200 includes the CML latch 4 described above so that the user can reset the initial condition of the CML latch 200, There is a difference that the high-speed reset device 300 is connected to the input terminal of the CML latch 200. [ Here, the reset of the output signal means an operation of initializing the CML latch 200 by setting the output signal of the CML latch 200 to a desired value of 0 and 1.

Specifically, the CML latch 200 includes a first circuit portion 202, a second circuit portion 204, a first output 210, a second output 212, a current source 214, clock signal inputs 216 and 218, .

First, the first circuit unit 202 includes a plurality of transistors Q1 and Q2 as a part corresponding to the first pair 4a of the CML latch 4 described with reference to FIG. Here, the transistors Q1 and Q2 may be, for example, MOSFETs, BJTs, and the like. The plurality of transistors Q1 and Q2 may include a first input terminal 206 and a second input terminal 208, respectively. The first input 206 and the second input 208 may be, for example, a gate of a MOSFET, a base of a BJT, or the like.

The second circuit portion 204 includes a plurality of transistors Q3 and Q4 as a portion corresponding to the second pair 4b of the CML latch 4 described with reference to FIG. Here, the transistors Q3 and Q4 may be, for example, MOSFETs, BJTs, and the like.

The first output terminal 210 and the second output terminal 212 correspond to OP and ON of the CML latch 4 shown in FIG. The output signal of the CML latch 200 may be the voltage difference between the first output 210 and the second output 212.

The current source 214 corresponds to the current source I _SS of the CML latch 4 described with reference to FIG. Although the current source 214 includes a plurality of transistors M1 and M2 in FIG. 4, this is merely an example, and the embodiment of the current source 214 is not limited thereto.

The clock signal input terminals 216 and 218 correspond to the CP and CN of the CML latch 4 described in FIG. The clock signal inputs 216 and 218 may be connected to a clock pulse generator (not shown) to which a clock may be input. At this time, clock signals having different polarities may be input to the first clock signal input terminal 216, CP and the second clock signal input terminal 218, CM.

As an example, when the clock signal of the first clock signal input terminal 216 is (+) and the clock signal of the second clock signal input terminal 218 is (-), the level of the input clock signal is 'High' When the clock signal of the first clock signal input terminal 216 is (-) and the clock signal of the second clock signal input terminal 218 is (+), it can be seen that the level of the clock signal to be input is 'Low'.

The first circuit unit 202 switches the level of the output signal according to the difference in the voltage input to the plurality of input stages 206 and 208 when the level of the clock signal is High. As an example, when the level of the clock signal is High, the difference between the voltages of the first and second output terminals 210 and 212 (that is, the voltage of the OP voltage of -OM) is R I _{C SS} (> is a zero) the level of the output signal or the High (or 1), the first and second output terminals (210, 212) the voltage difference (i.e., the voltage of the OP - OM) becomes -R _C I _SS (<0) and the level of the output signal becomes Low (or 0). This is the same as that described in Fig.

Further, the second circuit unit 204 maintains the level of the output signal when the level of the clock signal is Low, which is lower than High. In this case, the difference between the voltages of the first and second output terminals 210 and 212 (that is, the voltage of the voltage -OM of OP) is maintained at R _C I _SS (or -R _C I _SS ). This is the same as that described in Fig.

The CML latch 200 shown in FIG. 4 is different from the CML latch 4 of FIG. 3 in that the high-speed reset device 300 is connected to the first and second input terminals 206 and 208.

Hereinafter, the high-speed reset device 300 will be described.

The fast reset device 300 controls the inputs 206 and 208 of the CML latch 200 according to the user's input such as the base of the transistors Q1 and Q2 The output signal can be reset to a desired value.

4, the fast reset device 300 includes a first reset circuit portion 302 and a second reset circuit portion 304 and is responsive to a user's input for inputting the inputs 206 and 208 of the CML latch 200 (EN) signal to reset the output signal of the CML latch 200.

First, the first reset circuit 302 is a part that is connected to the first input terminal (206, IP ₁₎ of CML latch 200, a first bias resistor 306, a first switching part 310 and the second switch (312).

The second reset circuit portion 304 includes a second bias resistor 308, a third switching portion 314 and a fourth switching portion 316 connected to the second input terminal 208 and IM ₁ .

Here, when the CML latch 200 is implemented as a MOSFET, the magnitudes of the first bias resistor 306 and the second bias resistor 308 are set so that the signal is not affected by the bias resistance, And may be connected to the first input terminal 206 and the second input terminal 208, respectively.

On the other hand, when the switching transistor is implemented as a BJT, an emitter follower (not shown) is included between the first and second input stages 206 and 208 and the first and second reset circuit sections 302 and 304, respectively The emitter follower supplies a base current required for operation to Q1 connected to the first input terminal 206 and Q2 connected to the second input terminal 208. [ At this time, the magnitude of the first bias resistor 306 and the second bias resistor 308 may be set such that the signal is not affected by the bias resistance and has a resistance value (for example, 2 to 3 k?) Of a magnitude necessary for operation of the emitter follower I have.

Further, the EN signal may include a first EN signal and a second EN signal. At this time, the voltage of the first EN signal may be different from the voltage of the second EN signal by a set value. In one example, the first EN signal may be a voltage having a magnitude of a high level, and the second EN signal may be a voltage having a magnitude of a low level.

The first switching unit 310 and the second switching unit 312 are connected in parallel and the third switching unit 314 and the fourth switching unit 316 are connected in parallel.

Here, the first switching unit 310 includes a switch for connecting or disconnecting the connection between the first bias resistor 306 and the terminal to which the first EN signal is applied, and the third switching unit 314 includes a second bias And a switch for connecting or disconnecting the connection between the resistor 308 and the terminal to which the second EN signal is applied.

In addition, the second switching unit 312 comprises a first bias resistor 306 and the first and the bias voltage (V _IP _ _BIAS), and a switch for connecting or blocking the connection to the terminal is to be applied, a fourth switching unit ( 316 may include a switch for connecting or disconnecting the connection between the second bias resistor 308 and the terminal to which the second bias voltage V _{IM - BIAS} is applied.

Here, the first bias voltage V _{IP - - BIAS} and the second bias voltage V _{IM - BIAS} are used to operate the transistors Q1 and Q2 in the forward active mode (in the case of MOS, saturated state) Voltage.

Hereinafter, an operation of the high-speed reset device 300 to input the EN signal to the CML latch 200 to adjust the output signal of the CML latch 200 to a desired timing will be described.

When the second switching unit 312 and the fourth switching unit 316 are turned on (i.e., closed), the CML latch 200 operates in the same manner as the CML latch 4 of FIG. 3 . That is, the second switching unit 312 and the fourth switching unit 316 are maintained in the ON state before the EN signal is input.

If the EN signal is applied in this state (for example, when the EN signal is High), the first switching unit 310 and the third switching unit 314 are turned on and the second switching unit 312 and the fourth switching unit 314 may be turned off.

Here, it is assumed that the EN signal is a signal for resetting the CML latch 200. In this case, the current I _SS flows through the branch of the transistor Q 1, while the current I _SS does not flow through the branch of the transistor Q 2.

As a result, the level of the output signal becomes High (or 1) level. At this time, the difference between the voltages output to the plurality of output terminals 210 and 212 of the CML latch 200 (that is, the voltage of the voltage OP of OP) is R _C I _SS (> 0).

In contrast, when the terminal to which the first switching unit 310 is connected and the terminal to which the third switching unit 314 are connected are interchanged (i.e., when the EN signal is input, the first switching unit 310 is turned on and the second EN Signal is applied and the third switching unit 314 is turned on to apply the first EN signal), the current I _SS flows through the branch on the side of the transistor Q 2, but the current I _SS does not flow through the branch on the side of the transistor Q 1.

As a result, the level of the output signal becomes Low (or 0) level. At this time, the difference between the voltages output to the plurality of output terminals 210 and 212 of the CML latch 200 (that is, the voltage of the voltage OP of OP) is -R _C I _SS (<0).

Thus, the fast reset device 300 can optionally apply an EN signal to the inputs 206 and 208 of the CML latch 200 instead of the bias voltage to adjust the output signal of the CML latch 200 to a desired point in time.

When the EN signal is not applied in this state (for example, when the EN signal is Low), the first switching unit 310 and the third switching unit 314 are turned off, The first switching unit 312 and the fourth switching unit 316 may be turned ON. In this case, the first bias voltage V _{IP - - BIAS} and the second bias voltage V _{IM - - BIAS} are applied, respectively, and the CML latch 200 operates normally as the CML latch 4 of FIG. 3 .

5 is a diagram for explaining a process of inputting an EN signal to a PRBS generator according to an embodiment of the present invention.

As shown in FIG. 5, the fast reset device 300 may receive an EN signal through a serial / parallel interface (SPI) and a shift register according to a user's input.

The serial / parallel interface (SPI) can be configured as an SPI master (SPI master) 500 and an SPI slave (SPI slave)

The SPI master 500 and the SPI slave 600 may communicate via the serial / parallel interface and the SPI slave 600 and the PRBS generator 100 may be implemented within the chip 10. A serial / parallel interface (SPI) is a synchronous communication method that supports 1: N communication. It must have one SPI master and one or more SPI slaves.

In addition, the serial / parallel interface (SPI) performs communication through at least four signal lines (MOSI, MISO, CLK, SS). Here, MOSI (Master Out, Slave In) is a signal line for outputting data from the SPI master 500 to the SPI slave 600 and MISO (Master In, Slave Out) is a signal line from the SPI slave 600 to the SPI master 500 ) For outputting data. In addition, CLK (or SCK) is a signal line through which a clock signal is transmitted, and SS (Slave Select) is a signal line for selecting a slave to transmit and receive data.

As described above, the serial / parallel interface (SPI) can transmit and receive data at the same time because the line for transmitting data and the line for receiving data are separately provided. That is, serial / parallel interface (SPI) has advantages of speed. In addition, since the serial / parallel interface (SPI) is synchronous, a clock signal is used, and the clock signal is output only from the SPI master 500.

In these embodiments, the SPI master 500 may be coupled to the user terminal 400. The user terminal 400 may be an electronic device such as a desktop, a notebook, a tablet PC, a smart phone, or the like as a terminal possessed by a user. The user may input a command for inputting the EN signal through the user terminal 400. [ The user terminal 400 may generate and transmit an EN signal to the SPI master 500 according to a user's input or may transmit an instruction for generating an EN signal to the SPI master 500. The SPI master 500 may receive the EN signal from the user terminal 400 or may receive a command for generation of the EN signal from the user terminal 400 to generate the EN signal.

The SPI master 500 may then forward the EN signal to the SPI slave 600 via the serial / parallel interface (SPI). The SPI master 500 and the SPI slave 600 each have a shift register (not shown). When the SPI master 500 and the SPI slave 600 are connected by the serial / parallel interface (SPI), both shift registers are connected to each other.

Accordingly, when a clock is generated, the EN signal in the shift register of the SPI master 500 is transferred to the shift register of the SPI slave 600 and the data in the shift register of the SPI slave 600 is simultaneously transferred to the shift register of the SPI master 500 do.

In this manner, the SPI slave 600 can receive the N EN signals sequentially (or serially) from the SPI master 500 and store the N bit EN signals in the Shift Register Memory Bank have. The SPI slave 600 may then transmit the N EN signals in parallel to the inputs 206 and 208 of the PRBS generator 100. The N EN signals transmitted in this way are 'EN1, EN2, ... , ENn, ... 'Can be.

6 is a graph illustrating a result of resetting an output signal of the PRBS generator according to an input of an EN signal according to an embodiment of the present invention.

Referring to FIG. 6, it can be seen that the output signal 610 of the PRBS generator 100 changes as the EN signal 620 is applied. In one example, if the EN signal 620 is a reset enable signal, the fast reset device 300 may reset the PRBS generator 100 by applying the same N EN signals according to the user's input. The fast reset device 300 may also apply the same or different EN signals to each CML latch 200 to change the phase of the PRBS signal.

As described above, according to the embodiments of the present invention, it is possible to control the input terminals 206 and 208 of the CML latch 200 according to the input of the user so that the initial condition of the CML latch 200 (i.e., the output signal) , It is possible to reset the high-speed PRBS signal at a desired point in time. Also, according to embodiments of the present invention, the phase of the PRBS signal after reset can be adjusted as quickly as desired by resetting the PRBS signal at a desired point in time and individually controlling initial conditions of each CML latch 200. [ Also, according to embodiments of the present invention, by resetting the output signal of the PRBS generator 100 regardless of the current operation of the PRBS generator 100, the operation such as the frequency shift of the clock signal source is continued It is possible to eliminate the influence that would otherwise occur.

It will be apparent to those skilled in the art that various modifications and equivalent arrangements may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Accordingly, it is to be understood that the present invention is not limited to the above-described embodiments. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims. It is also to be understood that the invention includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

10: chip 100: PRBS generator
200: CML latch 202: first circuit part
204: second circuit unit 206: first input stage
208: second input terminal 210: first output terminal
212: second output stage 214: current source
216, 218: Clock signal input terminal 300: High-speed reset device
302: first reset circuit part 304: second reset circuit part
306: first bias resistor 308: second bias resistor
310: first switching unit 312: second switching unit
314: third switching unit 316: fourth switching unit
400: User terminal 500: SPI master
600: SPI slave

Claims (9)

A first reset circuit portion coupled to a first input of the CML latch; And
And a second reset circuit portion coupled to a second input of the CML latch,
Wherein the first reset circuit part and the second reset circuit part comprise a high speed pseudo random binary sequence generator for inputting the enable signal to the first and second input stages respectively through switching control as the enable signal is inputted from the outside Fast reset device.
The method according to claim 1,
Wherein the enable signal includes a first enable signal and a second enable signal, and the first enable signal and the second enable signal are signals having a voltage difference capable of discriminating between a high level and a low level A fast reset device of a fast pseudorandom binary sequence generator.
3. The method of claim 2,
Wherein the first reset circuit part comprises:
A first bias resistor connected to the first input terminal;
A first switching unit for connecting or disconnecting a connection between the first bias resistor and a terminal to which the first EN signal is applied; And
A second switching unit for connecting or disconnecting a connection between the first bias resistor and a terminal to which the first bias voltage is applied;
And a high speed pseudo random binary sequence generator.
3. The method of claim 2,
Wherein the second reset circuit part comprises:
A second bias resistor connected to the second input terminal;
A third switching unit for connecting or disconnecting a connection between the second bias resistor and a terminal to which the second EN signal is applied; And
A fourth switching unit for connecting or disconnecting a connection between the second bias resistor and the terminal to which the second bias voltage is applied;
And a high speed pseudo random binary sequence generator.
The method according to claim 3 or 4,
Wherein the first and second switching units are connected in parallel and the third and fourth switching units are connected in parallel.
The method according to claim 3 or 4,
Wherein the first to fourth switching units comprise:
Wherein the high speed pseudo random binary sequence generator is switched according to an enable signal input from the outside.
The method according to claim 6,
Wherein the first and third switching units are ON when the enable signal is in the high state and the second and fourth switching units are in the ON state when the enable signal is in the low state, Speed pseudo-random binary sequence generator.
The method according to claim 1,
The enable signal,
A high-speed reset device of a fast pseudo-random binary sequence generator input through a serial / parallel interface (SPI) and a shift register according to a user's input.
The method according to claim 3 or 4,
The CML latch comprises:
Wherein an output signal is set to a desired value between 0 and 1 by changing the level of the first and second enable signals when the first and third switching units are on.

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