KR101788415B1 - Semiconductor Device and Fabricating Method thereof - Google Patents

Abstract

The present invention relates to a power semiconductor device, in which a gate electrode is formed of a split poly and a bottom gate electrode is formed to a depth of a drain region, thereby preventing an electric field from concentrating on a part of the gate electrode, This small semiconductor element can be provided.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor device and a fabrication method thereof,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly, to a trench gate semiconductor device in which a gate electrode is formed in a split poly such that the ON resistance is small.

In addition to the spread of mobile devices, technologies related to batteries that supply power to mobile devices are becoming more important. [0003] 2. Description of the Related Art [0004] In recent years, a secondary battery capable of discharging and charging according to usage has been the main type of battery, and a battery protection circuit for managing voltage and current required for discharging and charging according to battery specifications.

At this time, the battery protection circuit may perform functions such as a run time prediction as well as charge / discharge voltage and current control. In order to implement the above function, one or more cells may be connected in series or in parallel .

The battery protection circuit functions as a gate for passing and blocking the current due to the charging and discharging of the battery. Therefore, when the battery protection circuit is activated and the current passes, the battery protection circuit must have a low resistance value as much as possible. It is required to have a high withstand voltage performance so as not to cause a breakdown phenomenon even at a high voltage.

A battery protection circuit using a semiconductor device is generally configured with a control IC and a common drain MOSFET, and among them, a trench gate semiconductor device can realize a low on-resistance (Ron) through a high degree of integration, And is widely used as a device for

However, in the conventional trench gate semiconductor device formed with a single gate electrode, an electric field is concentrated at the gate electrode end, which lowers the breakdown voltage.

It is an object of the present invention to provide a trench gate semiconductor device with a small on-resistance.

According to an aspect of the present invention, there is provided a trench gate semiconductor device including a semiconductor substrate, an active region formed on the semiconductor substrate, a trench formed on both sides of the active region, an insulating film formed on the inner wall of the trench, A source region of a first conductivity type formed above the active region between the trenches, a drain region of a first conductivity type formed below the active region between the trenches, and a gate electrode formed between the source region and the drain region. 2 conductive type body region, and the gate electrode may include a bottom gate electrode formed under the trench and an upper gate electrode formed over the trench.

The drain region may include a heavily doped region of the first conductivity type formed in the lower portion,

And a low-concentration drift region of the first conductivity type formed on the upper portion.

The lower gate electrode may be formed at a depth where the drift region is formed.

In addition, the upper gate electrode may be wider than the lower gate electrode.

The insulating layer may include a lower insulating layer surrounding the bottom and side surfaces of the bottom gate electrode, and an upper insulating layer surrounding the bottom and side surfaces of the top gate electrode.

The lower insulating layer may be thicker than the upper insulating layer.

In addition, the upper and lower gate electrodes may be electrically connected.

The semiconductor device may further include a termination region formed at one end in the longitudinal direction of the trench and a gate metal electrically connecting the upper and lower gate electrodes to the termination region.

A trench gate semiconductor device according to an embodiment of the present invention includes a gate electrode formed in a split poly shape and a bottom gate electrode extending to a depth of a drain region to prevent the electric field from being concentrated on a portion of the gate electrode, It is possible to provide a semiconductor element having a small resistance.

1 is a cross-sectional view of a trench gate semiconductor device according to an embodiment of the present invention.
2 is a view showing a distribution of an electric field formed in a trench gate semiconductor device according to an embodiment of the present invention.
3 is a graph showing the relationship between the breakdown voltage according to the concentration of the mesa and the drift region of the trench gate semiconductor device according to the embodiment of the present invention.
4 is a view showing an active region and a termination region of a trench gate semiconductor device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention, parts not related to the description are omitted, and similar parts are denoted by like reference characters throughout the specification.

1 is a cross-sectional view of a trench gate semiconductor device 100 according to an embodiment of the present invention.

1, a trench gate semiconductor device 100 according to an embodiment of the present invention includes a semiconductor substrate, active regions 110 formed on the semiconductor substrate, trenches 120 formed on both sides of the active region 110, A gate electrode 140 formed on the protective film 130 and a source region 150 of a first conductivity type formed on the active region 110 between the trenches 120 A first conductive type drain region 170 formed under the active region 110 between the trenches 120 and a second conductive type body region 160 formed between the source region 150 and the drain region 170 ).

The gate electrode 140 includes a lower gate electrode 142 formed under the trench 120; And an upper gate electrode 141 formed on the trench 120. The upper and lower gate electrodes 141 and 142 may be electrically connected to each other.

The trench gate semiconductor device 100 according to an embodiment of the present invention may use various semiconductor substrates such as an epitaxial (EPI) wafer doped with an impurity of a first conductive type or a second conductive type. For example, as the epitaxial wafer, a Cz wafer manufactured by Czochralski (Cz) technique, which is advantageous for production of a large diameter wafer, a wafer in which an epitaxial layer is grown on a general wafer, or an epitaxial layer doped with a low concentration of impurities Can be used.

The active region 110 may be repeatedly formed adjacent to the semiconductor substrate. As the number of active regions 110 increases, the area of the trench gate semiconductor device increases and the amount of current that can be output increases.

When the active region 110 is repeatedly formed adjacent to the active region 110, a plurality of trenches 120 for separating the active region 110 may be formed with a predetermined spacing. At this time, the distance between the trenches 120 may be referred to as Mesa, and the value of Mesa may be determined according to the concentration of the drift region 171. Mesa will be described later with reference to Fig.

The source region 150 may be formed by doping impurities of the first conductivity type at a high concentration. The source region 150 may be formed over the entire region over the active region 110 between the trenches 120 and may be formed in a portion of the active region 110 adjacent to the trench 120, . In this case, when the source region 150 is formed in a portion of the active region 110 adjacent to the trench 120, a second conductivity type doping region 161).

The second conductive type doped region 161 can increase the threshold voltage of the trench gate semiconductor device 110 by forming a depletion region with the source region 150.

The source region 150 may be connected to the source metal 151 and electrically connected to the outside of the trench gate semiconductor device 100.

The drain region 170 may be formed under the active region 110 and may include a heavily doped region 172 of the first conductivity type formed in the lower portion of the drain region 170 and a first And may include a drift region 171 of a conductive type.

The drift region 171 has a structure for improving the breakdown voltage of the trench gate semiconductor device 100. The drift region 171 is lightly doped in accordance with the principle that the breakdown voltage becomes high when the doping concentration of the impurity in the PN junction is low It serves to increase the breakdown voltage. That is, the drift region 171 can improve the withstand performance of the trench gate semiconductor device 100, and the length of the drift region 171 and the impurity doping concentration are determined according to the specifications required for the trench gate semiconductor device 100 .

The body region 160 may be formed in the active region 110 between the source region 150 and the drain region 170 to form a channel. At this time, the body region 160 may be doped with impurities of the second conductivity type at a low concentration so as to enhance the breakdown voltage capability of the trench gate semiconductor device 100.

The trench 120 is formed at a predetermined depth from the upper surface of the semiconductor substrate. The trench 120 may form a depth from the source region 150 to the drain region 170 so as to sufficiently form or block the channel between the source region 150 and the drain region 170, May include a drift region 171 and a depth over the drift region 171.

A gate electrode 140 is formed in the trench 120. The gate electrode 140 includes a top gate electrode 141 formed on the trench and a bottom gate electrode 142 formed on the bottom of the trench.

The gate electrode 140 may be formed of a conductive material or polysilicon used as a general gate electrode material.

1, the width of the lower gate electrode 142 may be smaller than that of the upper gate electrode 141. Referring to FIG.

The gate electrode 140 is separated from the source region 150, the body region 160 and the drain region 170 by an insulating film 130 formed in the trench 120.

The insulating film 130 is formed in the trench 120 and includes a lower insulating film 132 surrounding the bottom and side surfaces of the bottom gate electrode 142 and an upper insulating film 131 surrounding the bottom and sides of the top gate electrode 141. [ ). At this time, the bottom surface of the upper insulating film 132 may function as an intermediate isolation layer for separating the upper gate electrode 141 and the lower gate electrode 142.

As shown in FIG. 1, the lower insulating layer 132 may be thicker than the upper insulating layer 131.

The upper insulating layer 131 is formed to have a small thickness so that an electric field caused by the upper gate electrode 141 can be transmitted to the body region 160 without loss and a channel is smoothly formed in the body region 160 through the upper insulating layer 131 .

The lower insulating layer 132 can prevent the electric field from concentrating on the end of the lower gate electrode 142 and prevent the electric field formed at the end of the upper gate electrode 141 from flowing along the lower gate electrode 142 It is possible to prevent the electric field from being concentrated in some areas.

The upper gate electrode 141 has a depth up to the drain region 170 so that a channel can be formed over the entire region of the body region 160 and the lower gate electrode 142 is connected to the upper gate electrode 141, May be formed at a depth where the drift region 171 is formed so that the electric field formed by the drift region 171 may smoothly continue.

The operation of the trench gate semiconductor device 100 according to the embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3. FIG.

2 is a view showing the distribution of the electric field formed in the trench gate semiconductor device 100 according to the embodiment of the present invention.

2A shows a distribution of an electric field formed in a conventional trench gate semiconductor device. Cut1 represents an electric field formed along a vertical line with respect to an insulating film, and Cut2 represents an electric field formed along a vertical line spaced apart from Cut1 by a certain distance. As shown in Cut1, in the conventional trench gate semiconductor device, the electric field is concentrated at the end of the gate electrode, and in particular, the largest electric field is formed at the bottom corner. In Cut2, since the gate electrode is spaced apart from the gate electrode at a constant distance, the electric field is reduced to show a gentle shape. However, it can be seen that the largest electric field is still formed at the bottom of the gate electrode.

In the conventional trench gate semiconductor device, the electric field is concentrated at the lower end of the gate electrode as described above, so that a yield phenomenon occurs even at a low voltage. Therefore, according to the experimental results, the breakdown voltage of the conventional trench gate semiconductor device is confirmed to be 36V.

2B, in the trench gate semiconductor device 100 according to the embodiment of the present invention, although a part of the electric field is concentrated on the lower end of the upper gate electrode 141, It can be seen that the electric field concentration phenomenon is alleviated. Therefore, according to the experimental results, the breakdown voltage of the trench gate semiconductor device 100 according to the embodiment of the present invention is confirmed to be 40V.

3 is a diagram showing the relationship of the breakdown voltage according to the concentration of the mesa and the drift region 171 of the trench gate semiconductor device 100 according to the embodiment of the present invention.

In FIG. 3, the graph marked with a fringe mark represents the breakdown voltage of the trench gate semiconductor device 100 according to an embodiment of the present invention, and the graph denoted by the hatched mark represents the breakdown voltage of the trench gate semiconductor device according to the prior art.

As shown in Figure 3, the trench gate semiconductor device 100 according to embodiments of the present invention appears to have an improved breakdown voltage compared to the prior art at the same drift region 171 concentration.

From another aspect of the improved characteristics of the breakdown voltage, the trench gate semiconductor device 100 according to an embodiment of the present invention may have a higher concentration doped drift region 171 in the same breakdown voltage requirements it means. When the doping concentration of the drift region 171 is high, the carrier concentration is improved and the resistance of the trench gate semiconductor device 100 in the active state is decreased.

That is, the trench gate semiconductor device 100 according to the embodiment of the present invention has a higher doping concentration in the drift region 171, thereby reducing on-resistance and reducing unnecessary power consumption due to on-resistance.

In FIG. 3, the shape of each mark is divided according to the value of Mesa. The square represents the case where Mesa is 1.2um, the circle represents when Mesa is 0.8um, and the triangle represents when Mesa is 0.4um.

As shown in FIG. 3, when the doping concentration of the drift region 171 is low, the breakdown voltage increases as the mesa becomes larger. However, when the doping concentration of the drift region 171 is high, Respectively.

Thus, the trench gate semiconductor device 100 according to embodiments of the present invention can be determined according to the requirements of the breakdown voltage, the spacing (Mesa) between the appropriate trenches 120, and the concentration of the drift region 171.

4 is a view showing an active region 110 and a termination region 111 of a trench gate semiconductor device 100 according to an embodiment of the present invention. FIG. 4A shows a plan view of a trench gate semiconductor device 100 according to an embodiment of the present invention, and FIG. 4B shows a cross section along line A-A '.

4A, the trench 120 is formed in the active region 110 and the termination region 111, and in the active region 110, the source region 150 and the source region 150 A source metal 151 is formed. In the termination region 111, a trench 120 is formed to extend and a gate electrode 140 formed in the trench 120 is formed and exposed on the semiconductor substrate. In the termination region 111, the gate electrode 140 exposed on the semiconductor substrate is electrically connected to the gate metal 145. The upper gate electrode 141 is connected to the gate metal 145 by the upper gate contact 143 And the bottom gate electrode 142 is connected to the gate metal 145 by the bottom gate contact 144.

The top gate electrode 141 and the bottom gate electrode 142 are formed in the trench 120 in the active region 110 and the termination region 111 in the active region, And is electrically separated from the source metal 151 by the oxide film 135 formed on the active region 110. [ In the termination region 111, a bottom gate electrode 142 is formed on the semiconductor substrate to be exposed to the outside of the trench 120, and a bottom gate contact 144 is formed on the exposed bottom gate electrode 142. The upper gate electrode 141 is also formed on the semiconductor substrate to be exposed to the outside of the trench 120 and the upper gate contact 143 is formed on the exposed upper gate electrode 141. The upper and lower gate electrodes 141 and 142 may be electrically connected by forming the gate metal 145 on the upper gate contact 143 and the lower gate contact 144.

As shown in FIG. 4, the gate metal 145 and the source metal 151 are spaced apart from each other by a predetermined distance, so that the gate electrode 140 and the source region 150 can be electrically separated from each other.

The features, structures, effects and the like described in the foregoing embodiments are included in at least one embodiment of the present invention and are not necessarily limited to one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the present invention. It can be seen that various modifications and applications are possible. For example, each component specifically shown in the embodiments may be modified and implemented. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

100: trench gate semiconductor element
110: active area
111: Termination area
120: trench
130: Insulating film
131: upper insulating film
132: Lower insulating film
140: gate electrode
141: upper gate electrode
142: lower gate electrode
150: source region
151: source metal
160: Body area
161: second conductivity type doping region
170: drain region
171: drift region
172: heavily doped region

Claims (8)

A semiconductor substrate;
An active region formed on the semiconductor substrate;
A trench formed on both sides of the active region;
An insulating film formed on the inner wall of the trench;
A gate electrode formed on the insulating film;
A source region of a first conductivity type formed over the active region between the trenches;
A drain region of a first conductivity type formed under the active region between the trenches; And
And a second conductive type body region formed between the source region and the drain region,
The gate electrode
A lower gate electrode formed under the trench; And
And an upper gate electrode formed on the trench,
A termination region formed at one end in the longitudinal direction of the trench; And
And a gate metal extending outside of the trench and electrically connecting the upper and lower gate electrodes formed on the same plane spaced apart from each other to the termination region through respective upper gate contacts and lower gate contacts, Gate semiconductor device.
The method according to claim 1,
The drain region
A heavily doped region of a first conductivity type formed in a lower portion; And
And a low-concentration drift region of the first conductivity type formed on the trench.
3. The method of claim 2,
And the bottom gate electrode is formed at a depth where the drift region is formed.
The method according to claim 1,
Wherein the upper gate electrode is wider than the lower gate electrode.
The method according to claim 1,
Wherein,
A bottom insulating film surrounding the bottom and side surfaces of the bottom gate electrode; And
And an upper insulating film surrounding the bottom and side surfaces of the upper gate electrode.
6. The method of claim 5,
Wherein the lower insulating film is thicker than the upper insulating film.
The method according to claim 1,
Wherein the upper and lower gate electrodes are electrically connected.
The method according to claim 1,
A termination region formed at one end in the longitudinal direction of the trench; And
And a gate metal electrically connecting the upper and lower gate electrodes to the termination region.

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