KR101773191B1 - Image display device - Google Patents

Abstract

The image display device includes a display device including a pixel array having a plurality of pixels to selectively implement a 2D image and a 3D image; And a pattern-type retarder for dividing the light from the display element into a first polarization component and a second polarization component; Each of the pixels including first and second main subpixels and first and second subpixels disposed between the main pixels; When the 2D image is implemented, the same 2D image data is displayed on the four subpixels; In the 3D image realization, the first and second main subpixels display 3D image data having different polarization directions, and black data is displayed on the first and second subpixels.

Description

IMAGE DISPLAY DEVICE [0002]

The present invention relates to an image display apparatus capable of implementing a two-dimensional plane image (hereinafter, referred to as a '2D image') and a three-dimensional stereoscopic image (hereinafter, referred to as a '3D image').

Due to various contents development and circuit technology development, recent image display apparatus can selectively implement 2D image as well as 3D image. The image display device implements a 3D image using a binocular stereoscopic technique or an autostereoscopic technique.

The binocular parallax method uses parallax images of right and left eyes with large stereoscopic effect, and both glasses and non-glasses are used, and both methods are practically used. In the non-eyeglass system, an optical plate such as a parallax barrier for separating the optical axis of left and right parallax images is installed in front of or behind the display screen. In the spectacle method, left and right parallax images having different polarization directions are displayed on a display panel, and stereoscopic images are implemented using polarized glasses or liquid crystal shutter glasses.

In the liquid crystal shutter glasses system, a left-eye image and a right-eye image are alternately displayed on a display unit in frame units, and a left-eye and right-eye shutter of the liquid crystal shutter glasses is opened and closed in synchronization with the display timing. The liquid crystal shutter glasses open the left eye shutter only during the odd frame period in which the left eye image is displayed and only the right eye shutter is opened during the excellent frame period in which the right eye image is displayed to produce binocular parallax in a time division manner. In such a liquid crystal shutter glasses system, the data on time of the liquid crystal shutter glasses is short, and the brightness of the 3D image is low, and the 3D crosstalk is very likely to occur depending on the synchronization of the display element and the liquid crystal shutter glasses and on / off switching response characteristics.

The polarizing glasses system includes a patterned retarder 2 attached on the display panel 1 as shown in Fig. The polarizing glasses system alternately displays the left eye image data L and the right eye image data R on a horizontal line basis in the display panel 1 and displays the polarized light 3 incident on the polarized glasses 3 through the patterned retarder 1. [ Switch the characteristics. As a result, the polarizing glasses system can realize a 3D image by spatially dividing the left eye image and the right eye image.

Such a polarizing glasses system has the following problems.

First, when source data having separate left / right image information is input, the source data is converted into a line by line type so as to conform to the stereoscopic image display device and is displayed on the display panel 1 It produces binocular parallax. A method of generating a 3D image by line-by-line type is a method of generating a 3D image from a left eye image to be displayed on the left eye of a person through down sampling (1080 --- > 540) Extract only the line information, extract only the excellent (or odd) line information from the right eye image displayed in the right eye of the person, and then mix the extracted left eye and right eye images alternately in line units. Here, '540' is a vertical axis of the left eye image data (L) or right eye image data (R) handled by the left eye image data (L) or the right eye image data (R) when the resolution of the 3D image is FHD (Full High Definition) Indicates the resolution.

However, in the process of extracting the 3D image from the original left and right images, the data loss of the original image is inevitable. "R1, L2, R3, L4 ..." in Fig. 2 represent data discarded in the 3D image extraction process. Such data loss due to downsampling causes image jagging and resolution decline, which degrades the display quality of the 3D image.

Second, since the left eye image and the right eye image are displayed adjacent to each other in a line unit in the polarizing glasses system, the upper and lower viewing angles in which no crosstalk occurs are narrow. Crosstalk occurs when the left eye and right eye images are superimposed at the upper / lower viewing angle position. 3, a method of forming a black stripe (BS) on the patterned retarder 2 to widen the upper / lower viewing angle of the 3D image has been proposed in Japanese Laid-Open Patent Publication No. 2002-185983. However, the black stripe (BS) used for improving the viewing angle causes a side effect which greatly reduces the luminance of the 2D image.

Accordingly, it is an object of the present invention to provide an image display device capable of preventing vertical resolution degradation of a 3D image and widening an upper / lower viewing angle of the 3D image without lowering the luminance of the 2D image.

According to an aspect of the present invention, there is provided an image display apparatus including a display device including a pixel array having a plurality of pixels to selectively implement a 2D image and a 3D image; And a pattern-type retarder for dividing the light from the display element into a first polarization component and a second polarization component; Each of the pixels including first and second main subpixels and first and second subpixels disposed between the main pixels; When the 2D image is implemented, the same 2D image data is displayed on the four subpixels; In the 3D image realization, the first and second main subpixels display 3D image data having different polarization directions, and black data is displayed on the first and second subpixels.

Each of the pixels is assigned three gate lines and one data line including a first gate line, a second gate line and a third gate line.

The first main sub-pixel is connected to the data line through a first TFT which is switched in response to a scan pulse from the first gate line; The first sub-pixel is connected to the data line via a second TFT which is switched in response to a scan pulse from the first gate line; The second sub-sub-pixel is connected to the data line through a third TFT which is switched in response to a scan pulse from the third gate line; The second main sub-pixel is connected to the data line through a fourth TFT which is switched in response to a scan pulse from the third gate line.

Pixel electrodes of the first and second sub-pixels are electrically connected to each other; The pixel electrodes of the first and second sub-pixels are connected to a common line through a discharge control TFT which is switched in response to a scan pulse from the second gate line.

A common voltage is applied to the common line.

In the 2D image realization, the first and third gate lines are simultaneously activated by scan pulses synchronized with each other within one horizontal period.

In the 2D image implementation, the first and third gate lines are simultaneously activated by scan pulses synchronized with each other within one horizontal period, and the 2D image data is applied to the data line in synchronization with the scan pulse.

Pixel and the first sub-pixel charge the 2D image data according to a scan pulse from the first gate line, and at the same time, the second sub-pixel and the second main sub- And charges the same 2D image data according to the scan pulse from the gate line.

In the 2D image implementation, the first and third gate lines are sequentially activated by scan pulses sequentially generated in one horizontal period, and the 2D image data is sequentially activated twice in synchronization with each scan pulse, .

The first sub-pixel and the first sub-pixel pre-charge the 2D image data according to a scan pulse from the first gate line, and the second sub-pixel and the second main sub- The same 2D image data is charged in accordance with the scan pulse from the scan pulse.

In implementing the 3D image, the first and third gate lines are sequentially activated within one horizontal period, and the second gate line is activated after a predetermined period elapses from the one horizontal period.

The first main subpixel and the first subpixel charge any one of left and right image data when the first gate line is activated; When the third gate line is activated, the second sub-pixel and the second main sub-pixel charge the remaining one of the left and right eye image data.

The first sub-pixel discharges any one of the precharged image data to a common voltage level when the second gate line is activated, and the second sub-pixel discharges the pre-charged remaining video data to the common And discharges at a voltage level.

Wherein the patterned retarder comprises a first retarder for transmitting the first polarized light component and a second retarder for transmitting the second polarized light component; The pattern reliader is aligned such that a boundary portion of the first and second retarders overlaps with a region where the first and second sub-pixels are formed.

Each of the first and second retarders corresponding to vertically neighboring first main subpixel and second main subpixel of different pixels; Left eye image data is displayed in first and second main subpixels corresponding to the first retarder, and right eye image data is displayed in first and second main subpixels corresponding to the second retarder.

The image display apparatus according to the present invention is configured such that one pixel is composed of four subpixels, that is, two main subpixels and two subpixels disposed therebetween, and in the 2D mode, 2D image data. In the 3D mode, 3D image data having different polarization directions are displayed on two main subpixels, and black data is displayed on two subpixels. Accordingly, the present invention can prevent vertical resolution degradation of the 3D image and widen the upper and lower viewing angles of the 3D image without lowering the luminance of the 2D image.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.
FIG. 2 is a view showing that the vertical resolution is lowered in the conventional polarizing glasses system. FIG.
3 is a view for explaining a decrease in luminance of a 2D image due to a black stripe used for improving a viewing angle in a conventional polarizing glasses system.
4 and 5 are views showing an image display apparatus according to an embodiment of the present invention.
6 is a view showing a [j, k] th pixel arranged in a pixel array;
FIG. 7A is a view showing 2D image data applied to a pixel in a 2D mode; FIG.
7B is a view showing 3D image data applied to a pixel in the 3D mode.
8 is a view showing an alignment position of the pattern reliader with respect to the pixel array of the display element.
9 is a view showing in detail the [1,1] th pixel arranged in the pixel array.
10A and 10B show drive waveforms in 2D mode.
11 is a diagram showing a drive waveform in the 3D mode.
12 is a diagram showing a state in which image data as shown in FIG. 11 is displayed on each horizontal line of the pixel array in the 3D mode.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 4 to 12. FIG.

4 and 5 show an image display apparatus according to an embodiment of the present invention.

3 and 4, the image display apparatus includes a display device 10, a pattern drifting device 20, a control unit 30, a panel driving unit 40, and polarizing glasses 50.

The display device 10 may include a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), an inorganic electroluminescent device, A flat panel display device such as an electroluminescence device (EL) including an organic light emitting diode (OLED), and an electrophoresis (EPD) device. Hereinafter, the display element 10 will be described mainly with reference to a liquid crystal display element.

The display element 10 includes a display panel 11, an upper polarizing film 11a, and a lower polarizing film 11b.

The display panel 11 includes two glass substrates and a liquid crystal layer formed therebetween. A plurality of data lines DL and a plurality of gate lines GL are disposed on the lower glass substrate of the display panel 11 so as to intersect with the data lines DL. A plurality of pixels P are arranged in a matrix form on the display panel 10 by the intersection structure of the signal lines DL and GL to constitute a pixel array.

On the upper glass substrate of the display panel 11, a black matrix, a color filter, and a common electrode are formed. The upper and lower polarizing films 11a and 11b are attached to the upper glass substrate and the lower glass substrate of the display panel 11 to form an alignment film for setting a pre-tilt angle of the liquid crystal. The common electrode to which the common voltage Vcom is supplied is formed on the upper glass substrate in a vertical electric field driving mode such as TN (Twisted Nematic) mode and VA (Vertical Alignment) Field switching mode) is formed on the lower glass substrate together with the pixel electrode. A column spacer for maintaining a cell gap of the liquid crystal cell may be formed between the glass substrates.

The display panel 11 may be implemented in any liquid crystal mode as well as a TN mode, a VA mode, an IPS mode, and an FFS mode. The liquid crystal display element of the present invention can be implemented in any form of a transmissive display element, a transflective display element, a reflective display element, and the like. In the transmissive display element and the semi-transmissive display element, the backlight unit 12 is required. The backlight unit 12 may be implemented as a direct type backlight unit or an edge type backlight unit.

The patterned retarder 20 is attached to the upper polarizing film 11a of the display panel 11. [ A first retarder is formed in the radial lines of the pattern reliader 20, and a second retarder is formed in the even lines of the patterned lithograph 20. The light absorption axis of the first retarder and the light absorption axis of the second retarder are orthogonal to each other. The pattern reliader 20 is arranged such that the boundary portion of the first and second retarders RT1 and RT2 is located at the middle portion of the pixels P arranged in the odd horizontal line of the pixel array or in the middle of the even horizontal line of the pixel array And can be aligned on the display panel 11 so as to be positioned at an intermediate portion of the arranged pixels P. The first retarder of the patterned retarder 20 transmits a first polarized light (e.g., left-handed circularly polarized light) of light incident from the pixel array. The second retarder of the patterned retarder 20 transmits the second polarized light (e.g., right circularly polarized light) of the light incident from the pixel array. The first retarder of the patterned retarder 20 may be implemented as a polarizing filter transmitting the left circularly polarized light and the second retarder of the patterned retarder 20 may be implemented as a polarizing filter transmitting the right circularly polarized light have.

The controller 30 controls the operation of the panel driver 40 in a 2D mode or a 3D mode according to a mode selection signal.

The controller 30 separates the 3D image data input from the system board (not shown) in the 3D mode into the left eye image data and the right eye image data without degrading the vertical resolution, and then supplies the separated 3D image data to the panel driver 40. [ The controller 30 supplies 2D image data input from the system board to the panel driver 40 under the 2D mode.

The control unit 30 receives timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE and a dot clock DCLK from the system board, And generates control signals GDC and DDC for controlling the operation timing of the gates. The control unit 30 multiplies the timing signals (Vsync, Hsync, DE, DCLK) synchronized with the input frame frequency to generate a frame signal having a frame frequency of Nxf (where N is a positive integer of 2 or more and f is an input frame frequency) The operation of the driving unit 40 can be controlled. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) system and 50 Hz in the PAL (Phase-Alternating Line) system.

The panel driving unit 40 includes a data driving unit 40A for driving the data lines DL of the display panel 11 and a gate driving unit 40B for driving the gate lines GL of the display panel 11, .

Each of the source driver ICs of the data driver 40A includes a shift register, a latch, a digital to analog converter (DAC), an output buffer, and the like. The data driver 40A latches the 2D / 3D image data according to the data control signal DDC. The data driver 40A converts the 2D / 3D image data into an analog positive gamma compensation voltage and a negative gamma compensation voltage in response to the polarity control signal to invert the polarity of the data voltage. The data driver 40A outputs the data voltage to the data lines DL in synchronization with the scan pulse output from the gate driver 40B. The source driver ICs of the data driver 40A may be mounted on a TCP (Tape Carrier Package) and bonded to a lower glass substrate of the display panel 11 by a TAB (Tape Automated Bonding) process.

The gate driver 40B includes a shift register, a multiplexer array, a level shifter, and the like. The gate driver 40B sequentially supplies scan pulses to the gate lines GL in accordance with the gate control signal GDC. The shift register of the gate driver 40B is mounted on the TCP and bonded to the lower glass substrate of the display panel 11 by the TAB process or is formed on the lower glass substrate by the GIP (Gate In Panel) Can be formed directly.

The polarizing glasses 50 include a left eye 50L having a left eye polarization filter (or a first polarization filter) and a right eye 50R having a right eye polarization filter (or a second polarization filter). The left eye polarizing filter has the same light absorption axis as the first retarder of the pattern retarder 20 and the right eye polarizing filter has the same light absorption axis as the second retarder of the pattern retarder 20. [ For example, the left eye polarizing filter of the polarizing glasses 50 may be selected as a left circular polarization filter, and the right eye polarizing filter of the polarizing glasses 50 may be selected as a right circular polarization filter. The user can view the 3D image data displayed on the display device 10 in a space division manner through the polarized glasses 50. [

Fig. 6 shows [j, k] (j, k is a positive integer) pixel (P) arranged in the pixel array. FIG. 7A shows 2D image data applied to the pixel P in the 2D mode, and FIG. 7B shows 3D image data applied to the pixel P in the 3D mode.

Referring to FIG. 6, the [j, k] th pixel P includes four subpixels defined by one data line Dj and three gate lines Gka, Gkb, and Gkc. The four subpixels include a first main subpixel MSP1, a first subpixel SSP1, a second subpixel SSP2, and a second main subpixel MSP2.

The first main subpixel MSP1, the first auxiliary subpixel SSP1, the second main subpixel SSP2, and the second subpixel SSP1 along the arrangement direction (Gka-> Gkb-> Gkc) of the first to third gate lines Gka, Gkb, The auxiliary subpixel SSP2 and the second main subpixel MSP2 are sequentially arranged.

In the 2D mode, the first and third gate lines (Gka, Gkc) are activated while the second gate line (Gkb) is deactivated. The first and third gate lines Gka and Gkc may be activated simultaneously in one horizontal period or sequentially in one horizontal period. In the 2D mode, the first main subpixel MSP1 and the first auxiliary subpixel SSP1 are charged in accordance with the scan pulse from the first gate line Gka, and the second auxiliary subpixel SSP2 and the second main The subpixel MSP2 is charged in accordance with the scan pulse from the third gate line Gkc. In the 2D mode, the first main subpixel MSP1, the first auxiliary subpixel SSP1, the second auxiliary subpixel SSP2, and the second main subpixel MSP2 all output the same 2D image data as shown in FIG. 7A Charge.

In the 3D mode, the first to third gate lines (Gka, Gkb, Gkc) are all activated. The first and third gate lines Gka and Gkc are sequentially activated within one horizontal period and the second gate line Gkb is activated after a predetermined period elapses from one horizontal period. In the 3D mode, when the first gate line Gka is activated, the first main subpixel MSP1 and the first auxiliary subpixel SSP1 are charged with either the left eye image or the right eye image data L / R DATA . When the third gate line Gkc is activated, the second sub-pixel SSP2 and the second main sub-pixel MSP2 charge the remaining one of the left and right eye image data R / L DATA. Subsequently, when the second gate line Gkb is activated after a predetermined period, the first sub-pixel SSP1 discharges any one of the precharged image data L / R DATA to the black gradation level, The pixel SSP2 discharges the previously charged image data R / L DATA to the black gradation level. As a result, as shown in FIG. 7B, in the 3D mode, the first main subpixel MSP1 transmits any one of the left and right image data L / R DATA to the first and second subpixels SSP1 and SSP2 And the second main sub-pixel MSP2 respectively charge the other of the left and right eye image data R / L DATA.

When the first main sub pixel MSP1 charges the left eye image data L DATA in the 3D mode, the second main sub pixel MSP2 charges the right eye image data R DATA, MSP1 charges the right eye image data (R DATA), the second main sub pixel MSP2 charges the left eye image data (L DATA). Accordingly, the present invention displays 2D image data without degrading the vertical resolution, thereby doubling the vertical resolution compared to the conventional technique.

The first and second auxiliary subpixels SSP1 and SSP2 fill black data in the 3D mode to widen the display interval between the left eye image data L DATA and the right eye image data R DATA to secure the vertical viewing angle, The same 2D image data is charged together with the first and second main subpixels MSP1 and MSP2 in the 2D mode to prevent the luminance of the 2D image from being lowered.

8 shows an alignment position of the pattern reliader 20 with respect to the pixel array of the display element 10. In Fig.

Referring to FIG. 8, the pattern-driven retarder 20 is a pattern-driven retarder 20 in which boundary portions of the first and second retarders RT1 and RT2 are arranged in the odd-numbered horizontal lines HL # 1 and HL # The subpixels SSP1 and SSP2 to be displayed in black in the 3D mode are formed in the middle portion of the first and second subpixels P1 and P3. The pattern reliader 20 is arranged so that the boundary portion of the first and second retarders RT1 and RT2 is located at the middle portion of the pixels P2 arranged in the even horizontal line HL # The subpixels SSP1 and SSP2 to be displayed in black in the 3D mode may be superimposed on the area where the subpixels SSP1 and SSP2 are formed.

When the first through third pixels P1, P2, and P3 arranged in the first through third horizontal lines HL # 1 through HL # 3 in the pixel array are vertically adjacent to each other, The first main subpixel MSP1 of the first pixel P3 and the second main subpixel MSP2 of the second pixel P2 and the first main subpixel MSP1 of the third pixel P3 are connected to the first and second retarders RT1 and RT2, And the second main sub-pixel MSP2 of the first pixel P1, the first main sub-pixel MSP1 of the second pixel P2 and the second main sub-pixel MSP2 of the third pixel P3, Respectively face the second retarder RT2. That is, the first main subpixel MSP1 of the pixel arranged on the odd horizontal line and the second main subpixel MSP2 of the pixel arranged on the even horizontal line are shifted from the left retarded image data L), and the second main subpixel MSP2 of the pixel arranged on the odd horizontal line and the first main subpixel MSP1 of the pixel arranged on the excellent horizontal line are opposed to the second retarder RT2 And displays the right-eye image data R.

FIG. 9 shows the [1,1] th pixel P arranged in the pixel array in detail.

Referring to FIG. 9, the pixel P includes a first main subpixel MSP1, a first auxiliary subpixel SSP1, a second auxiliary subpixel SSP2, and a second main subpixel MSP2.

The first main sub-pixel MSP1 includes a first pixel electrode Ep1 and a common electrode Ec opposite to each other. The first pixel electrode Ep1 is connected to the data line D1 through the first TFT ST1. The first TFT ST1 switches the current path between the data line D1 and the first pixel electrode Ep1 in response to the scan pulse SCAN from the first gate line G1a. To this end, the gate electrode of the first TFT ST1 is connected to the first gate line G1a, the source electrode thereof is connected to the data line D1, and the drain electrode thereof is connected to the first pixel electrode Ep1. The common electrode Ec is connected to the common line CL and receives the common voltage Vcom from the common line CL.

The first auxiliary sub-pixel SSP1 includes a second pixel electrode Ep2 and a common electrode Ec which are opposed to each other. And the second pixel electrode Ep2 is connected to the data line D1 through the second TFT ST2. The second TFT ST2 switches the current path between the data line D1 and the second pixel electrode Ep2 in response to the scan pulse SCAN from the first gate line G1a. To this end, the gate electrode of the second TFT ST2 is connected to the first gate line G1a, the source electrode thereof is connected to the data line D1, and the drain electrode thereof is connected to the second pixel electrode Ep2.

The second auxiliary sub-pixel SSP2 includes a third pixel electrode Ep3 and a common electrode Ec which are opposed to each other. And the third pixel electrode Ep3 is connected to the data line D1 through the third TFT ST3. The third TFT ST3 switches the current path between the data line D1 and the third pixel electrode Ep3 in response to the scan pulse SCAN from the third gate line G1c. To this end, the gate electrode of the third TFT ST3 is connected to the third gate line G1c, the source electrode thereof is connected to the data line D1, and the drain electrode thereof is connected to the third pixel electrode Ep3.

The second main sub-pixel MSP2 includes a fourth pixel electrode Ep4 and a common electrode Ec opposite to each other. And the fourth pixel electrode Ep4 is connected to the data line D1 through the fourth TFT ST4. The fourth TFT ST4 switches the current path between the data line D1 and the fourth pixel electrode Ep4 in response to the scan pulse SCAN from the third gate line G1c. To this end, the gate electrode of the fourth TFT ST4 is connected to the third gate line G1c, the source electrode thereof is connected to the data line D1, and the drain electrode thereof is connected to the fourth pixel electrode Ep4.

The second pixel electrode Ep2 of the first auxiliary subpixel SSP1 and the third pixel electrode Ep3 of the second auxiliary subpixel SSP2 are electrically connected to each other. The second and third pixel electrodes Ep2 and Ep3 are connected to the common line CL through the discharge control TFT DST. The discharge control TFT DST switches the current path between the common line CL and the second and third pixel electrodes Ep2 and Ep3 in response to the scan pulse SCAN from the second gate line Glb. To this end, the gate electrode of the discharge control TFT DST is connected to the second gate line G1b, the source electrode thereof is connected to the common line CL, and the drain electrode is connected to the second and third pixel electrodes Ep2 and Ep3 .

The operation of the pixel P in the 2D mode will be described with reference to the driving waveforms of FIGS. 10A and 10B together with the connection configuration of FIG.

The first and third gate lines G1a and G1c are activated simultaneously by a scan pulse SCAN synchronized with each other in one horizontal period 1H as shown in Fig. In this case, the 2D image data is applied once to the data line D1 in synchronization with the scan pulse SCAN. The first main subpixel MSP1 and the first auxiliary subpixel SSP1 are charged according to the scan pulse SCAN from the first gate line G1a and at the same time the second auxiliary subpixel SSP2 And the second main sub pixel MSP2 charge the same 2D image data according to the scan pulse SCAN from the third gate line G1c.

On the other hand, the first and third gate lines G1a and G1c are sequentially activated as shown in FIG. 10B by a scan pulse SCAN sequentially generated in one horizontal period (1H). In this case, the 2D image data is applied to the data line D1 twice in synchronization with each scan pulse SCAN. The first main subpixel MSP1 and the first auxiliary subpixel SSP1 are precharged 2D image data according to the scan pulse SCAN from the first gate line G1a and the second auxiliary subpixel SSP2 is pre- And the second main sub pixel MSP2 charge the same 2D image data according to the scan pulse SCAN from the third gate line G1c.

In the 2D mode, the first main subpixel MSP1, the first auxiliary subpixel SSP1, the second auxiliary subpixel SSP2, and the second main subpixel MSP2 all fill the same 2D image data.

The operation of the pixel P in the 3D mode will be described with reference to the driving waveform of FIG. 11 together with the connection configuration of FIG. 9 as follows.

The first and third gate lines G1a and G1c are sequentially activated by the scan pulse SCAN sequentially generated in one horizontal period 1H and the second gate line G1b is activated by one horizontal period 1H, By a scan pulse (SCAN) generated after a lapse of a predetermined period (Td). The first main subpixel MSP1 and the first subpixel SSP1 charge the first left eye image data L1 synchronized with the scan pulse SCAN when the first gate line G1a is activated. When the third gate line G1c is activated, the second sub-pixel SSP2 and the second main sub-pixel MSP2 are charged with the first right eye image data R1 synchronized with the scan pulse SCAN . Subsequently, when the second gate line G1b is activated after a predetermined period of time, the first sub-pixel SSP1 discharges the first left-eye image data L1 to the common voltage Vcom level and the second sub-pixel SSP2 ) Discharges the first right eye image data R1 to the common voltage (Vcom) level. In other words, the first and second sub-pixels SSP1 and SSP2 discharge the first left eye image data L1 and the first right eye image data R1 to the black gradation level, respectively.

In the 3D mode, the first main subpixel MSP1 serves as the first left eye image data L1, the first and second subpixels SSP1 and SSP2 serve as black data, the second main subpixel MSP2 serves as black data, And the first right eye image data R1.

12 shows a state in which the image data as shown in FIG. 11 is displayed on each horizontal line (HL # 1 to HL # 3) of the pixel array in the 3D mode.

Referring to FIG. 12, the 3D image data includes first left eye image data L1, first right eye image data R1, second right eye image data R2, second left eye image data L2, Data L3, and third right eye image data R3 in the order from top to bottom in the main sub-pixels of each pixel. According to the present invention, the 3D image data can be displayed as it is without degrading the vertical resolution.

As described above, in the image display apparatus according to the present invention, one pixel is composed of four subpixels, that is, two main subpixels and two subpixels disposed therebetween, and in the 2D mode, all Display the same 2D image data in subpixels, display 3D image data having different polarization directions in two main subpixels in the 3D mode, and simultaneously display black data in two subpixels. Accordingly, the present invention can prevent vertical resolution degradation of the 3D image and widen the upper and lower viewing angles of the 3D image without lowering the luminance of the 2D image.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

10: display element 20: pattern drift
30: Control section 40: Panel driving section
50: polarized glasses

Claims (15)

A display device including a pixel array having a plurality of pixels to selectively implement a 2D image and a 3D image; And
And a pattern-type retarder for dividing the light from the display element into a first polarization component and a second polarization component;
Each of the pixels including first and second main subpixels and first and second subpixels disposed between the main pixels;
When the 2D image is implemented, the same 2D image data is displayed on the four subpixels;
Wherein the first and second main subpixels display 3D image data having different polarization directions and the black data are displayed on the first and second subpixels when the 3D image is implemented. The method according to claim 1,
Wherein three pixels including a first gate line, a second gate line and a third gate line and one data line are allocated to each of the pixels. 3. The method of claim 2,
The first main sub-pixel is connected to the data line through a first TFT, and the first TFT is switched in response to a scan pulse from the first gate line;
The first sub-pixel is connected to the data line via a second TFT, and the second TFT is switched in response to a scan pulse from the first gate line;
The second sub-pixel is connected to the data line via a third TFT, and the third TFT is switched in response to a scan pulse from the third gate line;
The second main sub-pixel is connected to the data line via a fourth TFT, and the fourth TFT is switched in response to a scan pulse from the third gate line. The method of claim 3,
Pixel electrodes of the first and second sub-pixels are electrically connected to each other;
Pixel electrodes of the first and second sub-pixels are connected to a common line through a discharge control TFT, and the discharge control TFT is switched in response to a scan pulse from the second gate line. 5. The method of claim 4,
And a common voltage is applied to the common line. 5. The method of claim 4,
Wherein the first and third gate lines are simultaneously activated by scan pulses synchronized with each other within one horizontal period in the 2D image realization. 5. The method of claim 4,
In the 2D image implementation, the first and third gate lines are simultaneously activated by scan pulses synchronized with each other within one horizontal period, and the 2D image data is applied to the data lines in synchronization with the scan pulse, . 8. The method of claim 7,
Pixel and the first sub-pixel charge the 2D image data according to a scan pulse from the first gate line, and at the same time, the second sub-pixel and the second main sub- And charges the same 2D image data according to a scan pulse from the gate line. 5. The method of claim 4,
In the 2D image implementation, the first and third gate lines are sequentially activated by scan pulses sequentially generated in one horizontal period, and the 2D image data is sequentially activated twice in synchronization with each scan pulse, Is applied to the video display device. 10. The method of claim 9,
The first sub-pixel and the first sub-pixel pre-charge the 2D image data according to a scan pulse from the first gate line, and the second sub-pixel and the second main sub- And charges the same 2D image data in accordance with the scan pulse from the scan pulse generating circuit. 5. The method of claim 4,
Wherein the first and third gate lines are sequentially activated within one horizontal period and the second gate line is activated after a predetermined period of time from the one horizontal period. 12. The method of claim 11,
The first main subpixel and the first subpixel charge any one of left and right image data when the first gate line is activated;
And the second sub-pixel and the second main sub-pixel charge the remaining one of the left eye and the right eye when the third gate line is activated. 13. The method of claim 12,
The first sub-pixel discharges any one of the precharged image data to a common voltage level when the second gate line is activated, and the second sub-pixel discharges the pre-charged remaining video data to the common And discharges at a voltage level. The method according to claim 1,
Wherein the patterned retarder comprises a first retarder for transmitting the first polarized light component and a second retarder for transmitting the second polarized light component;
Wherein the pattern reliader is aligned such that a boundary portion of the first and second retarders overlaps with a region where the first and second sub-pixels are formed. 15. The method of claim 14,
Wherein each of the first and second retarders comprises:
Pixel corresponding to vertically adjacent first main subpixel and second main subpixel of different pixels;
Eye image data is displayed on the first and second main subpixels corresponding to the first retarder and the right eye image data is displayed on the first and second main subpixels corresponding to the second retarder, .

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