KR101768480B1 - Organic light emitting diode display device - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention is directed to an organic light emitting diode (OLED) display device capable of preventing an abnormal light emission phenomenon caused by application of a high potential driving voltage at the initial stage of driving, A display panel defining intersection pixels of the data lines; A gate driver for supplying a plurality of gate signals to the plurality of gate lines, a data driver for supplying a data voltage to the plurality of data lines, A timing controller for controlling the gate driver and the data driver; A plurality of gate turn-on switching elements corresponding one-to-one to the plurality of gate lines and supplying a gate high voltage to the plurality of gate lines in response to a first switching signal; And a plurality of data on / off switching elements corresponding in one-to-one correspondence with the plurality of data lines and supplying a data check signal to the plurality of data lines in response to a second switching signal.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an organic light emitting diode (OLED) display device capable of preventing an abnormal light emission phenomenon caused by application of a high-

2. Description of the Related Art [0002] Organic light emitting diodes (OLED) display devices for displaying images by controlling the amount of light emitted from an organic light emitting layer have been spotlighted by a flat panel display capable of reducing weight and volume, which are disadvantages of a cathode ray tube (CRT) .

In an OLED display device, a plurality of pixels are arranged in a matrix form to display an image. Each pixel includes an OLED and a pixel driver that adjusts the amount of current flowing through the OLED to adjust the brightness of each pixel. Here, the pixel driver includes a plurality of thin film transistors (TFTs) and at least one capacitor. The pixel driver is supplied with a data voltage, a plurality of control signals for driving a plurality of TFTs, a high potential driving voltage, and the like.

The pixel driving unit is driven by dividing the video display period into the initialization period, the threshold voltage sensing period, and the light emission period of the driving TFT in accordance with a plurality of control signals.

On the other hand, the nodes connected to the plurality of TFTs remain in a floating state until the OLED display starts to be driven and a plurality of control signals are supplied to the pixel driver. However, when the high-potential driving voltage is first supplied to the pixel driving unit at the initial stage of the driving in which the nodes connected to the plurality of TFTs are maintained in the floating state, since the majority of the TFTs are not in the definite turn- . Accordingly, in the conventional OLED display device, an undesired current is supplied to the OLED at the time of initial application of the high-potential driving voltage, resulting in an abnormal light emission phenomenon such as flickering.

It is an object of the present invention to provide an OLED display device capable of preventing an abnormal light emission phenomenon caused by application of a high potential driving voltage at the initial stage of driving.

According to an aspect of the present invention, there is provided an organic light emitting diode (OLED) display device including: a display panel defining intersection pixels of a plurality of gate lines and a plurality of data lines; A gate driver for supplying a plurality of gate signals to the plurality of gate lines; A data driver for supplying a data voltage to the plurality of data lines; A timing controller for controlling the gate driver and the data driver; A plurality of gate turn-on switching elements corresponding one-to-one to the plurality of gate lines and supplying a gate high voltage to the plurality of gate lines in response to a first switching signal; And a plurality of data on / off switching elements corresponding in one-to-one correspondence with the plurality of data lines and supplying a data check signal to the plurality of data lines in response to a second switching signal.

The first switching signal is outputted from the first time point to the third time point in a low state, and after the third time point is outputted in the gate high state, and the first time point is the ON time point of the organic light emitting diode display device And the third time point is a time point at which the gate driver starts supplying the plurality of gate signals to the plurality of gate lines and between the first time point and the third time point, And a second time point when the first time point is applied.

The pixel includes an organic light emitting diode and a plurality of switching elements for independently driving the organic light emitting diode, and the plurality of switching elements are turned off during a period from the first time point to the third time point. do.

And a plurality of gate signals are not output from the first time point to the third time point.

And the plurality of switching elements are P-type thin film transistors.

According to another aspect of the present invention, there is provided an organic light emitting diode (OLED) display device including: a display panel defining intersection pixels of a plurality of gate lines and a plurality of data lines; A timing controller for outputting a plurality of gate control signals and a plurality of data control signals; A shift register for outputting a shift register-out signal in response to the plurality of gate control signals; A gate signal output unit for generating a plurality of gate signals in response to the shift register-out signal and supplying the generated gate signals to the plurality of gate lines; And a light emission controller for supplying a gate high voltage to the plurality of gate lines until the gate signal output unit outputs the plurality of gate signals from a driving start time point. And a data driver for supplying a data voltage to the plurality of data lines in response to the plurality of data control signals.

Wherein the gate signal output unit comprises: a first switching device for supplying a gate low voltage to the first node in response to a kth clock pulse; A second switching device for supplying the gate high voltage to the first node in response to the shift register-out signal; A third switching element for supplying the gate-low voltage to the first node according to a potential of the second node; A fourth switching device for outputting the glow voltage to the plurality of gate lines according to a potential of the first node; A fifth switching device for outputting the gate high voltage to the plurality of gate lines in response to the shift register-out signal; A first capacitor coupled between the (k + 2) -th clock pulse supply line and the first node; And a second capacitor connected between the first node and the second node.

Wherein the light emission controller comprises: a sixth switching element for supplying the gate high voltage to the first node in response to a switching signal; And a seventh switching element for outputting the gate high voltage to the plurality of gate lines in response to the switching signal.

And the switching signal is output in a low state until the gate signal output unit outputs the gate signals from the driving start time point.

The first to seventh switching elements are P-type thin film transistors.

The embodiment of the present invention is provided in each pixel P and turns the plurality of TFTs connected to the plurality of gate lines GL into a turn-off state before the first application time point P2 of the high potential driving voltage. Accordingly, it is possible to prevent the abnormal light emission phenomenon caused by the application of the high potential driving voltage at the beginning of the driving.

1 is a configuration diagram of an OLED display according to a first embodiment of the present invention.
2 is a driving waveform diagram of the first and second switching signals G_EN and D_EN shown in FIG.
3 is a circuit diagram of the pixel P shown in Fig.
4 is a driving waveform diagram of the pixel P shown in Fig.
5 is a circuit diagram for explaining the cause of abnormal light emission.
6 is a circuit diagram for explaining the effect of the first embodiment of the present invention;
7 is a configuration diagram of the gate driver 4 according to the second embodiment of the present invention.
8 is a driving waveform diagram of the gate driving unit 4 shown in Fig.

Hereinafter, an OLED display according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

The embodiment of the present invention is provided in each pixel P and turns the plurality of TFTs connected to the plurality of gate lines GL into a turn-off state before the first application time point P2 of the high potential driving voltage. To this end, the embodiment of the present invention is characterized in that the gate high voltage VGH is supplied to a plurality of gate lines GL from the first application time point P2 of the high-potential driving voltage to the display start point P3.

On the other hand, in the embodiment of the present invention, the TFT may be composed of P type or N type, and will be described as a P type TFT for convenience of explanation. Therefore, the gate high voltage VGH is a voltage for turning off the TFT, and the gate low voltage VGL becomes a voltage for turning on the TFT. In describing a pulse-shaped signal, the gate high voltage VGH is defined as a high state VGH and the gate low voltage VGL is defined as a low state VGL.

Hereinafter, the embodiment of the present invention will be described as the first and second embodiments.

1 is a configuration diagram of an OLED display according to a first embodiment of the present invention.

The OLED display shown in Fig. 1 includes a display panel 2 defining pixels P at the intersection of a plurality of gate lines GL and a plurality of data lines DL; A gate driver 4 for driving a plurality of gate lines GL; A data driver 6 for driving a plurality of data lines DL; And a timing control unit 8 for controlling the driving timings of the gate driving unit 4 and the data driving unit 6.

The display panel 2 includes a data lighting inspection unit 10 and a gate lighting inspection unit 12 having a plurality of lighting control TFTs (TD, TG) for lighting inspection. (The data lighting inspection section 10 and the gate lighting inspection section 12 are shown separately from the display panel 2 in FIG. 1 for convenience of explanation), the data lighting inspection section 10 and the gate lighting inspection section 12 are not limited to the display panel 2).

Here, the data lighting-up inspection section 10 includes a plurality of data lighting inspection TFTs (TD). Here, the plurality of data on-state-check TFTs (TD) are connected in a one-to-one correspondence with a plurality of data lines (DL). The plurality of data turn-on TFTs TD supply the data check signal D_sig to the plurality of data lines DL in response to the second switching signal D_EN.

The gate lighting inspection section 12 includes a plurality of gate lighting inspection TFTs TG. Here, the plurality of gate turn-on TFTs (TD) are connected in a one-to-one correspondence with the plurality of gate lines GL. The plurality of gate lighting inspection TFTs TG supplies the gate high voltage VGH to the plurality of gate lines GL in response to the first switching signal G_EN.

In the related art, the data lighting inspection section 10 and the gate lighting inspection section 12 are provided for lighting inspection of the display panel 2, and remain in an unnecessary configuration in a display period for actually displaying an image. The first embodiment of the present invention is characterized in that a gate high voltage VGH is supplied to a plurality of gate lines GL by using a gate lighting check unit 12 which is not used in actual operation.

2 is a driving waveform diagram of the first and second switching signals G_EN and D_EN shown in FIG. In FIG. 2, P1 represents the power ON time point of the OLED display device (hereinafter referred to as a first power point), P2 represents the first power point of the high potential driving voltage (hereinafter referred to as a second power point) Start point (hereinafter referred to as " third point in time "). Here, the third time point P3 is a time point at which the gate driver 4 starts supplying a plurality of gate signals to the plurality of gate lines GL.

Referring to FIG. 2, it can be seen that the second time point P2 is between the first time point P1 and the third time point P3. At this time, the first switching signal G_EN is output to the low state VGL from the first time point P1 to the third time point P3, and is outputted to the high state VGH after the third time point P3. Accordingly, the plurality of gate lighting inspection TFTs TG are turned on from the first point of time P 1 to the third point of time P 3 to supply the gate high voltage VGH to the plurality of gate lines GL. The plurality of gate turn-on inspection TFTs TG are turned off after the third time point P3 to interrupt the interference with the plurality of gate lines GL.

On the other hand, the second switching signal D_EN is continuously outputted in the high state (VGH) after the first time point P1. Accordingly, the plurality of data on-state-check TFTs (TD) are turned off after the first time point (P1) to interrupt the interference with the plurality of data lines (DL).

Accordingly, the plurality of TFTs connected to the plurality of gate lines GL and provided in each pixel P maintains the turn-off state from the first time point P1 to the third time point P3, Thereby preventing the initial abnormal light emission phenomenon.

The configuration of the first embodiment of the present invention will be described in detail as follows.

Referring to FIG. 1, the timing controller 8 arranges image data (RGB) input from the outside in accordance with the size and resolution of the display panel 2, and supplies the image data to the data driver 6. The timing controller 8 controls the timing controller 8 using external synchronous signals such as a dot clock DCLK, a data enable signal DE, a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, And data control signals GCS and DCS to the gate driver 4 and the data driver 6, respectively.

The gate driving unit 4 generates a plurality of gate signals in response to a gate control signal GCS from a timing control unit 8, for example, a gate start pulse (GSP), a plurality of clock pulses CLK1 to CLK4, And supplies it to the gate line GL. Here, the plurality of gate signals include the light emission signal EM and the scan signal SCAN, and these will be described with reference to the pixel driver to be described later. On the other hand, the gate driver 4 may be embedded in at least one side of the display panel 2 in the form of a gate in panel.

The data driver 6 is connected to the timing controller 8 using a source start pulse SSP and a source shift clock SSC among data control signals DCS from the timing controller 8. [ To the data voltage Vdata. The data driver 4 supplies the converted data voltage Vdata to the plurality of data lines DL in response to a source output enable (SOE) signal.

3 is a circuit diagram of the pixel P shown in Fig. And Fig. 4 is a driving waveform diagram of the pixel P shown in Fig.

The pixel P shown in FIG. 3 includes a pixel driver that independently drives the OLED and the OLED. Here, the pixel driver includes first to fourth thin film transistors (TFTs) T1 to T4, a driving TFT DT, and a capacitor C. The OLED is connected between the pixel driving part and the low potential driving voltage (VSS) supply line and is equivalently represented by a diode.

The pixel driving section is supplied with a data voltage Vdata, a reference voltage Vref and a high potential driving voltage VDD supplied from the data line DL, A plurality of control signals SCAN and EM for controlling the plurality of control signals T1 to T4 are supplied. At this time, the high-potential driving voltage VDD has a relatively higher potential than the low-potential driving voltage VSS. The reference voltage Vref has a potential between the high potential driving voltage VDD and the low potential driving voltage VSS. Further, the low-potential driving voltage VSS is usually set to the ground voltage.

The first TFT T1 supplies the data voltage Vdata to the first node N1 in response to the scan signal SCAN. Here, the first node N1 is a node in which the output terminal of the first TFT (T1) and the output terminal of the second TFT (T2) are connected in common.

The second TFT T2 supplies the reference voltage Vref to the first node N1 in response to the emission signal EM.

The third TFT T3 connects the drain electrode d of the driving TFT DT and the second node to each other in response to the scan signal SCAN. Here, the second node N2 is a node connected to the gate electrode g of the driving TFT DT.

The fourth TFT T4 couples the drain electrode of the driving TFT DT and the anode electrode of the OLED to each other in response to the emission signal EM.

The driving TFT DT is supplied with the high potential driving voltage VDD to the source electrode s and controls the amount of light emitted from the OLED by controlling the amount of current supplied to the OLED according to the potential of the second node.

The capacitor C is connected between the first node N1 and the second node N2.

The OLED is composed of an anode electrode connected to the pixel driver, a cathode electrode supplied with a low potential driving voltage, and an organic layer formed between the anode electrode and the cathode electrode.

 4, the pixel driver outputs a first period (1) during which the scan signal (SCAN) and the emission signal EM are output to the low state (VGL), the emission signal EM is output to the high state (VGH) A second period (2) during which the scan signal SCAN is output to the low state VGL and a third period during which the scan signal SCAN is output to the high state VGH and the light emission signal EM is output to the low state, (③).

Specifically, the first period (1) is a period in which the first to fourth TFTs T1 to T4 are turned on to initialize the first and second nodes N1 and N2. The second period (2) is a period in which the first and third TFTs T1 and T3 are turned on to program the data voltage Vdata and sense the threshold voltage of the driving TFT DT. The third period (3) is a period in which the OLED emits light by supplying a driving current to the OLED according to the potential of the second node N2.

However, the scan signal SCAN and the emission signal EM are not supplied from the first point P1 to the third point P3. Therefore, each node of the pixel P between the first time point P1 and the third time point P3 maintains the floating state as shown in Fig. At this time, when the high potential driving voltage VDD is supplied to the pixel P at the second time point P2, since each of the TFTs T1 to T4 and DT of the pixel P is not in a definite turn-off state, And current is supplied to the OLED.

In order to prevent this, as shown in FIG. 6, the first embodiment of the present invention is a method for driving a gate high voltage VGH (VGH) from a plurality of gate lines GL in a period from a first time point P1 to a third time point P3 Is supplied. Accordingly, the first to fourth TFTs DT are turned off during the period from the first time point P1 to the third time point P3, and the current supply to the OLEDs is cut off.

As described above, in the first embodiment of the present invention, the gate on-state checking section 12 is used to control the gate high voltage (Vout) to the gate lines GL during the period from the first time point P1 to the third time point P3 VGH). Accordingly, it is possible to prevent the initial abnormal light emission phenomenon by cutting off the supply of the undesired current to the OLED. Further, since the first embodiment uses a plurality of gate turn-on TFTs TG when supplying the gate high voltage VGH to the plurality of gate lines GL, there is no need to provide a separate switching element have.

Hereinafter, an OLED display device according to a second embodiment of the present invention will be described. The second embodiment supplies the gate high voltage VGH to the plurality of gate lines GL in the period from the first time point P1 to the third time point P3 as in the first embodiment. For this, the first embodiment uses the gate lighting inspection unit 12, but the second embodiment differs from the first embodiment in that the gate driving unit 4 applies a plurality of gate lines GL to the gate high voltage VGH.

Basically, the second embodiment has the same configuration as the first embodiment, and the gate driver 4 will be described in detail below.

7 is a configuration diagram of the gate driver 4 according to the second embodiment of the present invention. 8 is a driving waveform diagram of the gate driver 4 shown in FIG.

The gate driver 4 shown in FIG. 7 includes a gate signal output unit 14 and a light emission control unit 16.

The gate signal output unit 14 generates a plurality of gate signals SCAN and EM during the video display period (after the third time point P3) and supplies the generated gate signals SCAN and EM to the plurality of gate lines GL.

The light emission control unit 16 supplies the gate high voltage VGH to the plurality of gate lines GL during the initial period of the drive, that is, from the first time point P1 to the third time point P3.

Specifically, the gate signal output section 14 includes the fifth to ninth TFTs T5 to T9 and the second and third capacitors C2 and C3.

The fifth TFT T5 supplies the gate-low voltage VGL to the third node N3 in response to the second clock pulse CLK2.

The sixth TFT T6 supplies the gate high voltage VGH to the third node N3 in response to the shift register-out signal SRO. Here, the shift register-out signal SRO is a signal provided from a shift register (not shown). The shift register is included in the gate driver 4 and sequentially outputs the shift register-out signal SRO in response to a plurality of gate control signals GCS.

The seventh TFT T7 supplies the gate-low voltage VGL to the third node N3 in accordance with the potential of the fourth node N4. Here, the fourth node N4 is an output terminal, and is a node connected to the gate line GL.

The eighth TFT T8 outputs the gate-low voltage VGL to the gate line GL in accordance with the potential of the third node N3.

The ninth TFT T9 outputs the gate high voltage VGH to the gate line GL in response to the shift register-out signal SRO.

The second capacitor C2 is connected between the fourth clock pulse CLK4 supply line and the third node N3.

The third capacitor C3 is connected between the third node N3 and the fourth node N4.

On the other hand, the emission control section 16 includes the tenth and eleventh TFTs T10 and T11.

The tenth TFT T10 supplies the gate high voltage VGH to the third node N3 in response to the third switching signal SOC.

The eleventh TFT T11 outputs the gate high voltage VGH to the gate line GL in response to the third switching signal SOC.

The third switching signal SOC for controlling the light emission control unit 16 is output from the first time point P1 to the third time point P3 to the low state VGL and after the third time point P3, State (VGH). Accordingly, the tenth and eleventh TFTs T10 and T11 are turned on from the first time point P1 to the third time point P3. Then, the tenth TFT T10 supplies the gate high voltage VGH to the third node N3 to turn off the eighth TFT T8. The eleventh TFT T11 outputs the gate high voltage VGH to the gate line GL.

As described above, in the second embodiment of the present invention, by using the light emission control section 16 of the gate driver 4 during the period from the first time point P1 to the third time point P3, a plurality of gate lines GL The gate high voltage VGH is supplied. Accordingly, it is possible to prevent the initial abnormal light emission phenomenon by cutting off the supply of the undesired current to the OLED.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

10: Data lighting inspection part 12: Gate lighting inspection part

Claims (10)

A display panel defining intersection pixels of a plurality of gate lines and a plurality of data lines;
A gate driver for supplying a plurality of gate signals to the plurality of gate lines;
A data driver for supplying a data voltage to the plurality of data lines;
A timing controller for controlling the gate driver and the data driver;
A plurality of gate turn-on switching elements corresponding one-to-one to the plurality of gate lines and supplying a gate high voltage to the plurality of gate lines in response to a first switching signal; And
And a plurality of data on / off switching elements corresponding to the plurality of data lines in one-to-one correspondence and supplying data inspection signals to the plurality of data lines in response to a second switching signal. The method according to claim 1,
The first switching signal is outputted in a low state from a first time point to a third time point and is output in the gate high state after the third time point,
Wherein the first time point indicates a power-on time point of the organic light emitting diode display device, the third time point is a time point at which the gate driver starts supplying the plurality of gate signals to the plurality of gate lines, And a second time point at which a high potential driving voltage is first applied to the display panel is present between the time point and the third time point. 3. The method of claim 2,
The pixel includes an organic light emitting diode and a plurality of switching elements for independently driving the organic light emitting diode,
And the plurality of switching elements are turned off in a period from the first time point to the third time point. The method of claim 3,
Wherein a plurality of gate signals are not output from the first time point to the third time point. The method of claim 3,
Wherein the plurality of switching elements are P-type thin film transistors. A display panel defining intersection pixels of a plurality of gate lines and a plurality of data lines;
A timing controller for outputting a plurality of gate control signals and a plurality of data control signals;
A shift register for outputting a shift register-out signal in response to the plurality of gate control signals; A gate signal output unit for generating a plurality of gate signals in response to the shift register-out signal and supplying the generated gate signals to the plurality of gate lines; And a light emission controller for supplying a gate high voltage to the plurality of gate lines until the gate signal output unit outputs the plurality of gate signals from a driving start time point. And
And a data driver for supplying a data voltage to the plurality of data lines in response to the plurality of data control signals,
The gate signal output section
A first switching device for supplying a gate-low voltage to the first node in response to a k-th clock pulse;
A second switching device for supplying the gate high voltage to the first node in response to the shift register-out signal;
A third switching element for supplying the gate-low voltage to the first node according to a potential of the second node;
A fourth switching device for outputting the gate-low voltage to the plurality of gate lines according to a potential of the first node;
A fifth switching device for outputting the gate high voltage to the plurality of gate lines in response to the shift register-out signal;
A first capacitor coupled between the (k + 2) -th clock pulse supply line and the first node; And
And a second capacitor connected between the first node and the second node. delete The method according to claim 6,
The light-
A sixth switching element for supplying the gate high voltage to the first node in response to the switching signal; And
And a seventh switching element for outputting the gate high voltage to the plurality of gate lines in response to the switching signal. 9. The method of claim 8,
The switching signal
Wherein the gate signal output unit is output in a low state until the gate signal output unit outputs the gate signals from the driving start time point. 10. The method of claim 9,
Wherein the first to seventh switching elements are P-type thin film transistors.

Images