KR101736393B1 - Low Power C2MOS Based Double Data Rate CDS Counter and Analog-Digital Convertin Apparatus Thereof Using That - Google Patents

Abstract

In the present invention, a double data rate (DDR) operation is enabled by XORing a first node and a second node of a counter of a C2MOS structure with low power consumption, The present invention relates to a low-power C2MOS-based DDR CDS counter and an analog-to-digital converter using the same, and more particularly, to a complementary relationship between two transistors by adding a transistor operated in accordance with a complementary clock to a transistor receiving a clock A TSPC flip-flop operating as a TSPC flip-flop and an embedded BWI cell providing a correlated double sampling (CDS) operation coupled to the TSPC flip-flop; Including an XOR gate that implements a counter with DDR (Double Data Rate) operation by performing an XOR logical expression with two node outputs as input .

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a low power C2MOS based DDR CDS counter and an analog-to-

The present invention relates to a correlated double sampling (CDS) counter capable of DDR (Double Data Rate) operation only by a C2MOS structure, and more particularly to a counter capable of counting by DDR, BWI (Bitwise Inversion) To an analog-to-digital conversion apparatus using the same.

Generally, counters can be used in various electronic devices to convert effective physical quantities such as light intensity, sound intensity, and time into digital signals.

For example, an image sensor is an apparatus for acquiring an image using the property of a semiconductor that reacts with incident light, and includes an analog-to-digital converter for converting an analog signal output from the pixel array into a digital signal. The analog-to-digital conversion device may be implemented using a counter that performs a counting operation using a clock.

At this time, the operating speed and power consumption of the counter directly affect the performance of the device or system including it. In particular, the CMOS image sensor may include a plurality of counters for converting the analog signals output from the active pixel sensor array into the digital signals according to the configuration. The number of such counters increases with the resolution of the CMOS image sensor. As the number of counters increases, the operation speed and power consumption of the counter can be an important factor for determining the overall performance of the image sensor.

Accordingly, in order to reduce power consumption in a CMOS image sensor using a single slope analog-to-digital converter, a dual data rate (DDR) capable of realizing the same resolution while lowering the counter speed by half, ) Counter. In addition, this conventional double data rate counter has been proposed to be applicable to digital double sampling (DDS), which eliminates offsets using output codes of respective reset voltage and signal voltage.

However, in order to implement a conventional double data rate (DDR) counter, it is required to increase the number of peripheral circuits such as a multiplexer in addition to a flip-flop as shown in FIG. 1, There is still a problem such as an increase in the counter consumption power and a decrease in the operating speed as the number of circuits increases and the circuit complexity increases accordingly.

Japanese Patent Application Laid-Open No. 10-2014-0145812 (published on December 24, 2014) Published Patent Application No. 10-2008-0019376 (Published Mar. 2008.04.04)

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above problems, and it is an object of the present invention to provide a dual-data rate (DDR) Power DDR CDS counter based on a low power C2MOS that can operate at the same level with low power consumption at a frequency of only one-half of a frequency, and an analog-to-digital converter using the same.

Another object of the present invention is to provide a low power C2MOS-based DDR CDS counter which enables a correlated double sampling (CDS) operation by embedding a BWI (Bitwise Inversion) cell, And to provide a conversion device.

Other objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

According to another aspect of the present invention, there is provided a low-power C2MOS-based DDR CDS counter according to the present invention, in which a transistor receiving a clock is operated in a complementary relation between two transistors by adding transistors operated in accordance with a complementary clock A TSPC flip-flop and an embedded BWI cell coupled to the TSPC flip-flop to provide a correlated double sampling (CDS) operation; and a first node output and a second node output of the TSPC flip- And an XOR gate for implementing a counter by DDR (Double Data Rate) operation by performing an XOR logical expression with an input.

)을 입력받는 제 3 p형 트랜지스터(MP203)와, 제 3 p형 트랜지스터(MP203)와 직렬로 연결되어 드레인단이 제 2 노드(제 2 p형 트랜지스터(MP202)의 게이트단 및 제 2 n형 트랜지스터(MN202)의 게이트단)와 연결되며, 게이트를 통해 제 2 클럭(

)을 입력받는 제 3 n형 트랜지스터(MN203)와, 전원전압 및 제 2 노드 간에 접속되며 게이트를 통해 상기 제 1 노드의 출력 데이터를 입력받는 제 2 p형 트랜지스터(MP202)와, 제 2 p형 트랜지스터(MP202)와 직렬로 연결되어 제 2 노드 및 접지 간에 접속되며 게이트를 통해 상기 제 1 노드의 출력 데이터를 입력받는 제 2 n형 트랜지스터(MN202)와, 제 2 p형 트랜지스터(MP202) 및 제 2 n형 트랜지스터(MN202) 사이에 직렬로 연결되어 게이트를 통해 제 2 클럭(

)을 입력받는 제 4 p형 트랜지스터(MP204)와, 제 4 p형 트랜지스터(MP204)와 직렬로 연결되어 게이트를 통해 제 1 클럭(

)을 입력받는 제 4 n형 트랜지스터(MN204)로 구성되는 것을 특징으로 한다.Preferably, the TSPC flip-flop comprises a first p-type transistor (MP201) composed of a first node and a second node which are different from each other and connected between a power supply voltage and a first node and receives data through a gate, A first n-type transistor MN201 connected in series with the transistor MP201 and connected between the first node and the ground and receiving data through a gate thereof, a first p-type transistor MP201 and a first n-type transistor MN201 And a drain terminal thereof is connected to a second node (a gate terminal of the second p-type transistor MP202 and a gate terminal of the second n-type transistor MN202), and a first clock

Type transistor MP203 and a third p-type transistor MP203. The third p-type transistor MP203 is connected in series with the third p-type transistor MP203 and has its drain terminal connected to the gate terminal of the second p-type transistor MP202 and the second n- The gate of the transistor MN202), and a second clock

A second p-type transistor (MP202) connected between the power supply voltage and the second node and receiving output data of the first node through a gate, and a second p-type transistor A second n-type transistor MN202 connected in series with the transistor MP202 and connected between the second node and the ground and receiving output data of the first node through a gate, 2 < / RTI > n-type transistors MN202, The second clock (

A fourth p-type transistor MP204 receiving the first p-type transistor MP204 in series with the fourth p-type transistor MP204,

And a fourth n-type transistor MN204 receiving the input signal.

) 및 제 2 클럭(

)은 위상이 서로 반대로 이루어지는 것을 특징으로 한다.Preferably, the first clock (

) And the second clock (

Are characterized in that their phases are opposite to each other.

Preferably, the BWI cell includes a fifth p-type transistor MP101 having a source terminal connected to a power supply voltage and receiving an output signal of the TSPC flip-flop 200 through a gate, a source terminal connected to the power supply voltage, A sixth p-type transistor MP102 receiving the BWIN signal and connected to a drain terminal of the fifth p-type transistor MP101 and a sixth p-type transistor MP102 connected to the drain terminal of the fifth p-type transistor MP101 and the sixth p- A seventh p-type transistor (MP103) connected to the source terminal and receiving the BWI signal through a gate; and a seventh p-type transistor (MP103) connected to the drain terminal of the seventh p-type transistor A sixth n-type transistor MN103 for outputting an output signal of the source stage to the input data of the TSPC flip flop 200, and a sixth n-type transistor MN103 for connecting the source terminal of the sixth n-type transistor MN103 to the drain terminal, And through the gate to the TSPC A fifth n-type transistor MN101 receiving the output signal of the flip-flop, and a fifth n-type transistor MN101 having a drain terminal connected to the drain terminal of the seventh p-type transistor MP103 and a source terminal connected to the ground, 7 n-type transistor MN102.

According to an aspect of the present invention, there is provided an analog-to-digital converter using a low-power C2MOS-based DDR CDS counter according to the present invention includes a comparator for comparing an analog signal and a reference signal to generate a comparator output signal, Power C2MOS-based DDR CDS counter for counting and generating a digital signal corresponding to the analog signal, wherein the low power C2MOS-based DDR CDS counter includes a transistor for receiving a clock and a transistor operated in accordance with a complementary clock, An embedded BWI cell that provides a correlated double sampling (CDS) operation coupled to the TSPC flip-flop and a TSPC flip-flop that operates in a complementary relationship between the two transistors by adding the TSPC The first node output of the flip-flop and the second node output are input to perform an XOR logical expression And an XOR gate for implementing a counter by DDR (Double Data Rate) operation.

The low-power C2MOS-based DDR CDS counter and the analog-to-digital converter using the same according to the present invention have the following effects.

First, in the case of the conventional counter, a state transition occurs in one of the rising and falling edges. In the present invention, the state transition occurs in both the rising edge and the falling edge, It has the effect of operating with the same performance.

Second, unlike conventional DDR counters, it is possible to perform DDR operation only with C2MOS structure without using additional flip-flops.

1 is a circuit diagram showing a structure of a conventional DDR counter
2 is a circuit diagram illustrating a structure of a low power C2MOS-based DDR CDS counter according to an embodiment of the present invention.
FIG. 3 is a graph showing the power consumption results of the low power C2MOS-based DDR CDS counter of FIG. 2
4 is a diagram for explaining a problem of using a dual clock in the low power C2MOS based DDR CDS counter structure
5 is a circuit diagram illustrating a structure of a low power C2MOS-based DDR CDS counter according to a second embodiment of the present invention.
6 is a graph showing the power consumption results of the low power C2MOS based DDR CDS counter of FIG.

Other objects, features and advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the accompanying drawings.

A low-power C2MOS-based DDR CDS counter according to the present invention and an analog-digital converter using the same will be described with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. It is provided to let you know. Therefore, the embodiments described in the present specification and the configurations shown in the drawings are merely the most preferred embodiments of the present invention and are not intended to represent all of the technical ideas of the present invention. Therefore, various equivalents It should be understood that water and variations may be present.

2 is a circuit diagram showing the structure of a low-power C2MOS-based DDR CDS counter according to the first embodiment of the present invention.

As shown in FIG. 2, the low power C2MOS-based DDR CDS counter of the present invention has a complementary relationship between two transistors by adding a transistor operated in accordance with a complementary clock to a transistor receiving a clock, A TSPC flip-flop 200 for reducing noise and an embedded BWI cell 200 for enabling a correlated double sampling (CDS) operation connected to the TSPC flip- 100).

)을 입력받는 제 3 p형 트랜지스터(MP203)와, 제 3 p형 트랜지스터(MP203)와 직렬로 연결되어 드레인단이 제 2 노드(제 2 p형 트랜지스터(MP202)의 게이트단 및 제 2 n형 트랜지스터(MN202)의 게이트단)와 연결되며, 게이트를 통해 제 2 클럭(

)을 입력받는 제 3 n형 트랜지스터(MN203)와, 전원전압 및 제 2 노드 간에 접속되며 게이트를 통해 상기 제 1 노드의 출력 데이터를 입력받는 제 2 p형 트랜지스터(MP202)와, 제 2 p형 트랜지스터(MP202)와 직렬로 연결되어 제 2 노드 및 접지 간에 접속되며 게이트를 통해 상기 제 1 노드의 출력 데이터를 입력받는 제 2 n형 트랜지스터(MN202)와, 제 2 p형 트랜지스터(MP202) 및 제 2 n형 트랜지스터(MN202) 사이에 직렬로 연결되어 게이트를 통해 제 2 클럭(

)을 입력받는 제 4 p형 트랜지스터(MP204)와, 제 4 p형 트랜지스터(MP204)와 직렬로 연결되어 게이트를 통해 제 1 클럭(

)을 입력받는 제 4 n형 트랜지스터(MN204)로 구성된다. At this time, the TSPC flip-flop 200 includes a first p-type transistor MP201 including a first node and a second node which are different from each other and connected between the power supply voltage and the first node and receives data through a gate, A first n-type transistor MN201 connected in series with the first p-type transistor MP201 and connected between the first node and the ground and receiving data through a gate, a first n-type transistor MN201 connected between the first n-type transistor MP201 and the first n- And a drain terminal connected to the gate of the second p-type transistor MP202 and a gate terminal of the second n-type transistor MN202, Clock (

Type transistor MP203 and a third p-type transistor MP203. The third p-type transistor MP203 is connected in series with the third p-type transistor MP203 and has its drain terminal connected to the gate terminal of the second p-type transistor MP202 and the second n- The gate of the transistor MN202), and a second clock

A second p-type transistor (MP202) connected between the power supply voltage and the second node and receiving output data of the first node through a gate, and a second p-type transistor A second n-type transistor MN202 connected in series with the transistor MP202 and connected between the second node and the ground and receiving output data of the first node through a gate, 2 < / RTI > n-type transistors MN202, The second clock (

A fourth p-type transistor MP204 receiving the first p-type transistor MP204 in series with the fourth p-type transistor MP204,

And a fourth n-type transistor MN204 receiving the input signal.

) 및 제 2 클럭(

)은 위상이 서로 반대로 이루어진다.At this time, the first clock (

) And the second clock (

) Are opposite in phase.

With such a configuration, the TSPC flip-flop 200 can operate at a high speed with low power consumption.

The BWI cell 100 includes a fifth p-type transistor MP101 having a source terminal connected to a power supply voltage and receiving an output signal of the TSPC flip-flop 200 through a gate, a source terminal connected to a power supply voltage, A sixth p-type transistor MP102 receiving the BWIN signal through the fifth p-type transistor MP101 and a drain terminal connected to the fifth p-type transistor MP101, A seventh p-type transistor MP103 having a drain terminal connected to the source terminal and receiving a BWI signal through a gate thereof, a drain terminal connected to the drain terminal of the seventh p-type transistor MP103, and a BWD signal A sixth n-type transistor MN103 for receiving the output signal of the sixth n-type transistor MN103 and for outputting the output signal of the source stage to the input data of the TSPC flip flop 200, Connected to this ground and through the gate TSPC A fifth n-type transistor MN101 receiving the output signal of the rip-flop, and a fifth n-type transistor MN101 having a drain terminal connected to the drain terminal of the seventh p-type transistor MP103 and a source terminal connected to the ground, 7 n-type transistor MN102.

According to such a configuration, the BWI cell 100 is located between the TSPC flip-flops 200 and receives data. When the BWI (bitwise inversion) is performed, 0- > 1 And the value of each bit except LSB is reversed.

Referring to the operation of the BWI cell 100 shown in FIG. 2, the BWI and BWIN are 0 and 1, respectively, and the fifth p-type transistor MP101 and the fifth p- 5 n-type transistor MN101 inverts the output of the TSPC flip-flop 200. [

The BWI cell 100 starts with BWI changed to 1 to output 0 (zero) first to the input of the next TSPC flip-flop. At this time, the seventh p-type transistor MP103 cuts off the voltage between VDD and the output to prevent the output path 1 from being applied by the fifth p-type transistor MP101, and opens the seventh n-type transistor MN102 Apply zero to the output. Then, the sixth p-type transistor MP103 and the seventh n-type transistor MN102 are simultaneously turned off while BWIN becomes zero, and the sixth p-type transistor MP102 and the sixth p- 7 is applied to the output through the n-type transistor MN102. When the BWI finishes, BWIN changes back to 1 and returns to the initial state.

In the BWI method, digital CDS can be performed at a higher speed and lower power consumption than the conventional MUX method in view of the total power by frequency shown in FIG. 3 even with only six small transistors.

However, in the case where the BWI cell 100 is attached to the TSP flip-flop 200, the Q_output of the TSPC flip-flop is overlapped and converted by the inverter and the BWI cell 100. [ This would require additional power dissipation and delays to eliminate this portion in order to improve the performance of the CDS counter.

FIG. 5 is a circuit diagram showing a structure of a low power C2MOS-based DDR CDS counter according to a second embodiment of the present invention.

As shown in FIG. 5, the low power C2MOS-based DDR CDS counter of the present invention has a complementary relationship between two transistors by adding a transistor operated in accordance with a complementary clock to a transistor receiving a clock, A TSPC flip-flop 200 for reducing noise and an embedded BWI cell 200 for enabling a correlated double sampling (CDS) operation connected to the TSPC flip- And an XOR gate (XOR) that implements a counter by a double data rate (DDR) operation by performing an XOR logical expression with the first node output and the second node output of the TSPC flip-flop 200 being input.

As shown in FIG. 5, the structure in which the BWI cell 100 and the XOR gate XOR are combined (hereinafter referred to as a 'C2MOS structure') requires less power than the TSPC but uses a dual clock There was a problem and it was not used much in the existing counter.

However, in the present invention, since the inverter is essentially necessary for each flip-flop by coupling the BWI cell 100 to the C2MOS structure, the penalty due to the dual clock is actually only one inverter used for the input of the LSB flip-flop, The problem of the counter can be solved.

For reference, the CDS counters based on the actual implementation of the C2MOS structure are composed of a total of 16, and a maximum of four branches are connected to the output.

The CDS counter based on the C2MOS structure implemented as described above has a higher rate and lower power consumption than the CDS counter according to the first embodiment, as in the total power by frequency shown in FIG. 6, .

In addition, the analog-to-digital converter includes a comparator for generating an output signal of the comparator by comparing an analog signal with a reference signal, a low-power C2MOS-based circuit for counting the selected clock to generate a digital signal corresponding to the analog signal Of the DDR CDS counter.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications may be made without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (5)

A TSPC flip-flop consisting of a first node and a second node which are different from each other and operating in a complementary relation between the two transistors by adding transistors operated in accordance with complementary clocks in parallel to a transistor receiving a clock;
An embedded BWI cell coupled to the TSPC flip-flop to provide correlated double sampling (CDS) operation,
And an XOR gate for implementing a counter by a double data rate (DDR) operation by performing an XOR logical expression with an input of a first node output and a second node output of the TSPC flip-flop as inputs. CDS counter. The method of claim 1, wherein the TSPC flip-
A first node and a second node,
A first p-type transistor (MP201) connected between the power supply voltage and the first node and receiving data through a gate,
A first n-type transistor MN201 connected in series with the first p-type transistor MP201 and connected between the first node and the ground and receiving data through a gate,
A second end of the second n-type transistor MN202 is connected in series between the first p-type transistor MP201 and the first n-type transistor MN201, And is connected to a first clock ("

A third p-type transistor MP203 receiving the first p-
And a drain terminal thereof is connected in series with the third p-type transistor MP203 and connected to the second node (the gate terminal of the second p-type transistor MP202 and the gate terminal of the second n-type transistor MN202) Through the second clock (

A third n-type transistor MN203 for receiving the first n-
A second p-type transistor (MP202) connected between a power supply voltage and a second node and receiving output data of the first node through a gate,
A second n-type transistor MN202 connected in series with the second p-type transistor MP202 and connected between a second node and the ground and receiving output data of the first node through a gate,
Connected in series between the second p-type transistor MP202 and the second n-type transistor MN202 The second clock (

A fourth p-type transistor MP204 for receiving the fourth p-
Connected in series with a fourth p-type transistor (MP204) and connected to a first clock (

And a fourth n-type transistor (MN204) receiving an input of the fourth n-type transistor (MN204). 3. The method of claim 2,
The first clock (

) And the second clock (

) Of the low-power C2MOS-based DDR CDS counter. The method of claim 1, wherein the BWI cell
A fifth p-type transistor (MP101) having a source terminal connected to the power supply voltage and receiving an output signal of the TSPC flip-flop through a gate,
A sixth p-type transistor (MP102) having a source terminal connected to the power supply voltage, a BWIN signal input through a gate, and a fifth p-type transistor (MP101)
A seventh p-type transistor MP103 having a drain terminal connected to a source terminal of the fifth p-type transistor MP101 and a sixth p-type transistor MP102 and receiving a BWI signal through a gate thereof,
A sixth n-type transistor MP103 having a drain terminal connected to the drain terminal of the seventh p-type transistor MP103 and receiving a BWD signal through a gate thereof and outputting an output signal of the source terminal thereof as input data to the TSPC flip- MN 103,
A fifth n-type transistor MN101 having a source terminal connected to the drain terminal of the sixth n-type transistor MN103, a source terminal connected to the ground and receiving an output signal of the TSPC flip-flop through a gate,
And a seventh n-type transistor MN102 having a drain terminal connected to the drain terminal of the seventh p-type transistor MP103 and a source terminal connected to the ground and receiving a BWI signal through a gate thereof. DDR CDS counter. In the analog-to-digital converter,
A comparator for comparing the analog signal with a reference signal to generate a comparator output signal,
And a low power C2MOS based DDR CDS counter for counting the selected clock to generate a digital signal corresponding to the analog signal,
At this time, the low-power C2MOS-based DDR CDS counter
A TSPC flip-flop consisting of a first node and a second node which are different from each other and operating in a complementary relation between the two transistors by adding transistors operated in accordance with complementary clocks in parallel to a transistor receiving a clock;
An embedded BWI cell coupled to the TSPC flip-flop to provide correlated double sampling (CDS) operation,
And an XOR gate for implementing a counter by a double data rate (DDR) operation by performing an XOR logical expression with an input of a first node output and a second node output of the TSPC flip-flop as inputs. .

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