KR101709821B1 - Cloc recovery in a battery powered device - Google Patents

Abstract

It is possible for a battery-powered device to maintain a clock value when the battery is removed for a short period of time. During the first period, while the battery is in the device, the clock pulses derived from the first oscillator are counted at a first rate within a first counter representing the clock value. During the second period following the first period, while the battery is removed, the value of the first counter is kept independent of any clock pulses derived from the first oscillator, and the clock pulses derived from the second low power oscillator are And counted at the second counter. During the restoration period subsequent to the second period, the clock pulses derived from the second oscillator are counted again in the second counter, and the clock pulses derived from the first oscillator are multiplied by the number of pulses counted in the second counter during the second period .

Description

CLOCK RECOVERY IN A BATTERY POWERED DEVICE < RTI ID = 0.0 >

The present invention relates to clock recovery of battery powered devices, and more particularly to a method for recovering a visual count when a battery is removed from the device.

It is known from US-6,603,365 to provide a battery backup circuit in a wireless communication device. The oscillator is powered by the battery, and the counter counts the pulses generated by the battery. When the battery is replaced, a backup energy storage device, such as a capacitor, provides power to the counter so that the stored time can be saved.

However, this has the disadvantage that power is not supplied to the oscillator while the battery is being removed and therefore the time during this period is not counted.

US-6,124,764 discloses a device having a second oscillator operable at low power during a sleep period. The low power oscillator is calibrated to the main oscillator of the device during the wake-up period.

According to a first embodiment of the present invention, there is provided a method of updating a value of a first counter-first counter in an electronic device,

Counting clock pulses derived from the first oscillator from a first counter to a first rate during a first period,

Maintaining a value of a first counter independently of a clock pulse derived from a first oscillator during a second period during a second period after the first period,

Counting a clock pulse derived from a second oscillator in a second counter during a second period,

Counting a clock pulse derived from a second oscillator in a second counter during a restoration period after the second period,

Counting the clock pulses derived from the first oscillator at a second rate higher than the first rate at a first counter during a recovery period, the duration of the recovery period being equal to the number of pulses counted at the second counter during the second period, - < / RTI >

According to the second embodiment of the present invention,

A first oscillator for generating a clock pulse,

The value of the first counter - the first counter represents time -

A second oscillator for generating a clock pulse,

And a second counter,

The first counter is connected to the first oscillator such that the clock pulses derived from the first oscillator during the first period are counted at the first counter at the first rate and during the second period after the first period the value of the first counter is To be kept independent of the clock pulse derived from the first oscillator,

The second counter is connected to the second oscillator such that the clock pulses derived from the second oscillator during the second period are counted at the second counter and during the recovery period after the second period the clock pulses derived from the second oscillator are at the second To be counted at the counter,

The first counter is also connected to the first oscillator such that the clock pulses derived from the first oscillator during the recovery period are counted in the first counter at a second rate higher than the first rate, Is determined based on the number of pulses counted in the second counter.

Thus, the second oscillator can be effectively calibrated to the first oscillator, so that the restoration period can be accurately controlled even though the characteristics of the second oscillator can not be grasped well.

This has the advantage that the period of the recovery period can be matched to the period of the second period without having to know the frequency of the clock pulse derived from the second oscillator.

1 is a schematic block diagram of a system according to an embodiment of the present invention;
2 is a circuit diagram showing a first timing recovery circuit;
3 is a flow chart illustrating a method of operation of a first timing recovery circuit;
4 is a timing diagram illustrating signals generated during operation of the circuit of FIG. 2;
5 is a circuit diagram showing a second timing recovery circuit;
Figure 6 is a timing diagram showing signals generated during operation of the circuit of Figure 5;
7 is a circuit diagram showing a third timing recovery circuit;
8 is a flow chart illustrating a method of operation of a third timing recovery circuit;
9 is a timing diagram showing signals generated during operation of the circuit of Fig. 7; Fig.
10 is a circuit diagram showing a fourth timing recovery circuit;
11 is a timing diagram showing signals generated during operation of the circuit of Fig. 10; Fig.

1 illustrates a portion of a wireless communication device 10 in accordance with an embodiment of the present invention. The wireless communication device 10 is powered by the battery 12 and is generally conventional and will be described only when necessary for an understanding of the present invention. Specifically, FIG. 1 illustrates a state in which the battery 12 is removed from the device 10 for a short period of time, for example, for replacement of the battery itself or replacement of a SIM card physically covered by the battery 12. [ And a clock recovery circuit 14 used for counting the time included.

Thus, the clock recovery circuit 14 includes a main oscillator 16 that can also be used to generate signals at a particular frequency for radio frequency communication. However, in this specification, the use of the main oscillator 16 is to generate a pulse at a known frequency. These pulses are supplied to the main oscillator pulse counter 18 which counts pulses from the main oscillator 16. [ The number of counted pulses is used as a beacon of time, which can be used by various applications running on the device 10, such as an alarm.

When the battery is removed from the device 10 for a short period of time, it is necessary to keep the time. Thus, when the battery 12 is present, energy is stored in the charge storage 20. The power consumption of the main oscillator 16 can not be satisfied only by the charge storage section 20. [ Thus, when the battery is removed from the device 10 for a short period of time, the power to be sent to the main oscillator 16 is lost. When the battery 12 is removed from the device 10, it is detected by the control block 22 so that the energy from the charge storage 20 provides power to the low power (and relatively low precision) To be used for supplying. The pulses generated by the secondary oscillator 24 are counted by the secondary oscillator pulse counter 26.

When the battery 12 is reinserted, power is supplied back to the main oscillator 16. At this time, the count of pulses generated by the secondary oscillator 24 is reduced. Although the frequency of the secondary oscillator 24 is not very accurately known, it can be assumed that this frequency is constant between the period of time when the battery is removed and the time immediately after the battery is reinserted. Thus, a restoration period may be created, during which the secondary oscillator 24 may be used to ensure a known relationship between the restoration period and the power cancellation period.

At this time, the pulses generated by the main oscillator 16 are counted by the main oscillator pulse counter 18 at an increased rate for the recovery period. This increased rate is set at the end of the recovery period to restore the count of pulses generated by the main oscillator to a value that would have been reached if the battery had not been removed.

2 is a more detailed schematic diagram of the clock recovery circuit 14 and associated circuitry.

2, the battery 12 is connected to a pin 30 connected to the oscillator circuit 16 via a low power (LP) low dropout (LDO) regulator 28 to provide power do. The oscillator circuit 16 is connected to a crystal oscillator 32 and is capable of generating pulses at a frequency of 32.768 kHz.

The oscillator 16 is connected to the main oscillator counter 18 via a switch 34. The pulse from the oscillator 16 is delivered to the first input of the switch 34 via divide-by-2 block 36 and delivered without division to the second input of the switch 34 .

The regulator 28 is also connected to a charge storage section 20 comprising a small back-up capacitor 37 and a resistor 38 for storing the charge. The charge storage 20 is also connected to a pin 40 that is connected to the secondary low power oscillator circuit 24 to provide power. The secondary oscillator 24 can be of relatively low precision, and its frequency can not be known very precisely due to initial tolerances and temperature drift, but can be in the range of, for example, 26 to 56 kHz. For example, the secondary oscillator 24 may be a very low power simple oscillator, such as an RC circuit, which may be implemented entirely in an ASIC that includes a clock recovery circuit 14. As described below, the secondary oscillator 24 does not require any factory calibration or calibration prior to use.

The secondary oscillator (24) is connected to the secondary counter (26). In addition, the secondary oscillator 24 is connected to a stability counter 42, which also receives an enable input from the critical circuit 44, which allows the voltage from the battery 12 to fall below a threshold value That is, when the battery 12 is removed, a signal is provided.

The outputs from the critical circuit 44 and the stability counter 42 are also passed to the OR gate 46. The output from the OR gate 46 is passed through the inverter 48 to the enable input of the first counter 18. The output from the OR gate 46 is also passed to the up / down control input of the second counter 26. The second counter 26 provides an output to its output terminal 50 when its count value exceeds zero. The output from the OR gate 46 and the signal on the output terminal 50 of the second counter 26 are combined in another OR gate 52 and are then transferred to the enable input of the second counter 26 .

The circuit shown in Fig. 2 also allows an alarm value, i. E. A time value when the user has requested an alarm, to be set in the alarm register 54, and when the count value in the main counter 18 reaches the set alarm value, And a comparator 56 for determining when it can be generated.

The operation of the circuit shown in Fig. 2 will now be described in more detail with reference to the flow chart of Fig. 3 and the signal timing diagram of Fig.

Figure 3 shows the process performed by the circuit of Figure 2 in this embodiment.

The process begins at step 70 when the device 10 is in operation. In step 72, it is determined whether or not the battery 12 is present. If a battery is present, the voltage V _BATT is greater than the threshold voltage V _TH as shown by line 90 in FIG. During this period, a pulse is generated by the main oscillator 16 and the main counter 18 is enabled so that the pulse is counted as shown in step 74 in FIG. 3, Lt; RTI ID = 0.0 > 96 < / RTI > During this period, since the secondary counter 26 is not enabled, the secondary count value is not greater than zero, and thus the switch 34 is turned on when the pulse generated by the main oscillator 16 is divided into two blocks 36 ) So that the pulses are counted at a first rate that is a predetermined rate (1/2 in this embodiment) of the rate at which they are generated.

When the battery 12 is removed from the device, it drops below the voltage V _BA threshold voltage V _TH at time T _{1 shown} in Figure 4. At this time, it is determined that the battery 12 is not present. At this point, it is still possible to generate some pulses, but depending on the oscillator 16 it is no longer possible to provide pulses at the desired frequency.

When the voltage V _BATT drops below the threshold voltage V _TH , the critical block 44 outputs a positive signal V _A as shown by line 92 in FIG. As a result, the OR gate 46 provides a positive output inverted by the inverter 48 so that the positive signal is removed from the enable input of the main counter 18, The counter of the oscillator pulse is disabling. As a result, the main count value 96 is fixed and remains constant after T ₁ as shown in FIG.

The positive output of the OR gate 46 also causes the OR gate 52 to generate a positive input for the enable input of the second counter 26 and also to the up / down input of the second counter. As a result, the pulse generated by the secondary oscillator 24 receiving power from the backup charge storage unit 20 is counted up in the secondary oscillator 24 as shown in step 78 of FIG. The secondary count value 98 therefore increases after T ₁ .

During this battery removal period, it is continuously tested whether the battery is reinserted, as shown in step 80 of FIG. 3, by determining whether the voltage V _BATT is maintained below the threshold voltage V _TH .

When the battery is reinserted, the voltage V _BATT rises quickly exceeding the threshold voltage V _TH . As shown by line 90 in Figure 4, the voltage V _A falls to zero. However, the counter 42 continues to count pulses from the secondary oscillator 24 during the stabilization period until the main oscillator 16 restarts stable operation. After the stabilization period has expired, at time T ₂ shown in FIG. 4, voltage V _B drops to zero as shown by line 94 in FIG. 4, as determined in step 82 of FIG. 3 do.

Thus, the stabilization period set by the counter 42 effectively forms part of the battery removal period in this embodiment.

During the subsequent recovery period, the secondary count value is positive so that the switch 34 is controlled such that the pulse generated by the main oscillator 16 is not passed through the divide by two block 36, At a second rate equal to the rate at which they are generated. At the same time, the voltages (V _A , V _B ) are all zero, and therefore there is no positive output from the OR gate 46. Thus, inverter 48 causes the signal to pass to the enable input of main counter 18, so that the main oscillator pulse is counted at a second rate, as shown in step 84 of FIG. As a result, the main count value 96 increases after a time T ₂ at a rate that is twice the rate that is increased before T ₁ .

At the same time, the 0 output from the OR gate 46 is transferred to the up / down input of the secondary counter, and thus the pulse received at the secondary counter 26 is now counted as shown in step 86 of FIG. It is used to reduce the value.

This situation continues until time T ₃ , which is determined in step 88 of FIG. 3, as the count value of the secondary counter 26 falls to zero. At this time, the two inputs to the OR gate 52 are all zero, so the enable input to the secondary counter 26 is removed and the count value is fixed to zero. In addition, the second count value is therefore no longer greater than zero, switch 34 is again controlled to be transmitted through the pulse is divided into two blocks (36) generated by the main oscillator 16, so that the time T ₃ after , Pulses are counted again at the first rate, i.e., one-half the rate at which they are generated.

Thus, the secondary oscillator 24 has a relatively large tolerance and its frequency can drift considerably with temperature, but the frequency can be assumed to be constant over a relatively short period of time when the battery 12 is removed. As a result of this process, although it can not be guaranteed that the maximum value of the secondary count that reaches time T ₂ has any specific meaning, it is not guaranteed that the battery removal period (including the stabilization period in this embodiment) (T ₁ to T ₂ ) And the lengths of the restoration periods (T ₂ to T ₃ ) are assumed to be the same. Since the main count value does not increase during the battery removal period but increases twice as much as the normal rate during the restoration period, until the time T ₃ , the main count value reaches the reached value Lt; / RTI >

Therefore, the count value can be used as a measure of time. For example, it can be compared with a set alarm time and an alarm can be generated when the comparator 56 determines that the count value is equal to the value stored in the register 54. [ Alarms that are scheduled to occur during or during the battery removal period may now occur later during the recovery period, but the difference may be small if the battery removal period is short. An alarm scheduled to occur during the restoration period may occur at an intended time.

If the battery is still being removed at the second time while in the recovery period, the operation should be resumed as described above and the secondary count 26 resumes the upward count from the value reached during the down count. When the battery is reinserted, an extended restoration period occurs. When the secondary counter reaches zero, the main counter 18 can reach the correct value.

Thus, the circuit shown in FIG. 2 compensates for the battery removal period by the recovery period, which is the same period as the pulses from the main oscillator are counted at twice the normal rate. More generally, if the battery removal period is X = Y-1, it can be compensated by a recovery period during which the pulse is counted at Y times the normal rate and at the same time the battery removal period is divided by X. [ In the circuit shown in Fig. 1, X = 1 and Y = 2.

More generally, Y is preferably a power of 2, so that block 36 can be replaced with any Y divide-by-Y block so that it can be relatively simply implemented by a binary counter . Figure 5 shows another embodiment with X = 3 and Y = 4.

The circuit shown in Fig. 5 is generally similar to that shown in Fig. 2, and components having the same function are indicated by the same reference numerals, and will not be further described herein.

5, the pulses from the main oscillator 16 are transferred to the first input of the switch 34 via the divide by four block 110 and to the second input of the switch 34 without division . In addition, the pulse from the secondary oscillator 24 is passed through the divide by three block 114 to the first input of the switch 112 and to the second input of the switch 112 without division. The output of the switch 112 is connected to the input of the secondary counter 26 and the switch 112 is controlled by the output of the OR gate 46.

Fig. 6 shows the operation of the circuit of Fig. During the battery removal period T ₁ to T _{2 the} switch 112 is controlled so that the pulse from the secondary oscillator 24 delivered via the dividing block 114 to 3 is transferred to the input of the secondary counter 26 do. As a result, the secondary count value is increased to 1/3 of the rate that is increased in Fig. 4 (the vertical scale of Figs. 4 and 6 is not the same, and thus this difference is not evident in the figure).

During the recovery period (T ₂ to T ₄ ), the switch 112 is controlled so that a pulse from the secondary oscillator 24, which is not passed through the dividing block 114, is transferred to the input of the secondary counter 26 do. As a result, the secondary count value is reduced to three times the rate that is increased during the battery removal period, so that the length of the restoration period (T ₂ to T ₄ ) is 1/3 of the length of the battery removal period (T ₁ to T ₂ ) do.

At the same time, the pulse from the main oscillator 16 being counted is transmitted to the main counter 18 through the divide by 4 block 110 before the time T ₁ , and not through the divide by 110 block 110 during the restoration period The fact that the main count value increases at the second rate which is four times the normal rate during the recovery period.

The result of combining these features is that until time T ₄ , the main count value is restored to its reached value if it had been increased at a first rate throughout the battery removal period and the restoration period.

The embodiments described so far are particularly suitable for situations where the battery is reinserted into the device but the device is powered down. If the device is powered on during the restoration period, it may be advantageous to be able to immediately restore the main count value.

Fig. 7 is a circuit diagram of another embodiment in which this is possible. The circuit shown in FIG. 7 is generally similar to that shown in FIG. 2, wherein components having the same function are denoted by the same reference numerals and will not be further described herein.

Figure 8 is a flow chart illustrating a method of operation of the circuit of Figure 7; The method of FIG. 8 is generally similar to that shown in FIG. 3, so that corresponding steps are designated by the same reference numerals and will not be further described herein.

7, the main count latch 120 is connected to the main counter 18, and the secondary count latch 122 is connected to the secondary counter 26. In the circuit of Fig.

As shown in FIG. 8, at time T ₂ , the main count value is latched at step 130, and the secondary count value is latched at step 132. Next, while the secondary count value is decreasing during the recovery period, in step 134, it is determined whether or not the device is powered on. If there is power-on, in step 136, the time T _5, is calculated the main count correction value (C _1), the main count correction value (C ₁₎ is the main throughout the removed battery duration and recovery period count value claim 1 < / RTI > rate, it is the value that needs to be added to the main count value to make it reach the reached value. The process then returns to "START ".

If the rate at which the first rate, i.e., the rate at which the main count is increased during the battery removal period is R ₁ , and the rate at which the second rate, the main count, is increased during the recovery period is R _2, then the correction value C ₁ is Given.

Of course, any of these parameters can immediately know it is not, the correction value (C ₁₎ is a time when the main count value latched in step 130 from the T ₂ (MC _L), the time T ₂ of the second count latched in step 132. In the Knowing the value (SC _L ), the main count value at time T ₅ (MC _F ), the secondary count value at time T ₅ (SC _F ), and the perceived ratio (Y) of R ₂ and R ₁ , Y, of course, has a value of 2 in the embodiment shown in Fig. Specifically,

이다.

to be.

delete

(SC _L -SC _F ), this correction value can be calculated quite accurately if the restoration period is long enough so that the error produced is not large. Thus, it is possible to quickly recover lost counts during the restoration process by measuring how many corrections are provided in advance and by calculating what other corrections should be added.

As before, this calculation may be performed using a Y value that is a value greater than 2, also to shorten the normal recovery period. A suitable circuit is shown in FIG. 10, which is generally similar to that shown in FIG. 7, so that components having the same function are represented by the same reference numerals and are not further described herein.

10, the pulses from the main oscillator 16 are transferred to the first input of the switch 34 through the divide by four block 150, and to the second input of the switch 34 without division . The pulse from the secondary oscillator 24 is also passed through the divide by three block 154 to the first input of the switch 152 and to the second input of the switch 152 without division. The output of the switch 152 is connected to the input of the secondary counter 26 and the switch 152 is controlled by the output of the OR gate 46.

11 shows the operation of the circuit of Fig. During the battery removal period T ₁ to T _{2 the} switch 152 is controlled so that the pulse from the secondary oscillator 24 delivered via the division block 154 to 3 is transferred to the input of the secondary counter 26 do. As a result, the secondary count value is increased by one-third of the rate at which it is increased in FIG. 9 (the vertical scale of FIGS. 9 and 11 is not the same, and thus this difference is not evident in the figure).

In the recovery period (T ₂ to T ₆ ), the switch 152 is controlled so that a pulse from the secondary oscillator 24, which is not passed through the divide by three block 154, is passed to the input of the secondary counter 26 do. As a result, the secondary count value is reduced to three times the rate increased during the battery removal period, and thus the maximum period of the recovery period is one third of the cycle of the battery removal period (T ₁ to T ₂ ).

At the same time, the pulse from the main oscillator 16 counted before the time T ₁ is transmitted to the main counter 18 through the dividing block 150 in four, and is not transmitted through the dividing block 150 in four during the restoring period The fact that the main count value is increased to four times the normal rate, i.e., the second rate Y = 4, during the restoration period.

This circuit follows the process schematically shown in Fig. 8 and the required additional correction value C ₁ can be calculated as described above if the device is powered up at time T ₆ before the restoration period is ended.

Thus, even when the battery supplying power to the main oscillator is temporarily removed from the circuit, a method and circuit for counting pulses in a manner that can be used to indicate time is described.

12: Battery 14: Clock recovery circuit
16: main oscillator 18: main oscillator pulse counter
20: charge storage unit 22: control unit
24: Secondary Oscillator 26: Secondary Oscillator Pulse Counter

Claims (15)

CLAIMS What is claimed is: 1. A method for updating a first counter in an electronic device, the value of the first counter representing a time,
Counting clock pulses derived from a first oscillator from the first counter to a first rate during a first period,
Maintaining a value of the first counter independently of a clock pulse derived from the first oscillator during the second period during a second period following the first period;
Counting the clock pulses derived from the second oscillator in the second counter during the second period,
Counting a clock pulse derived from the second oscillator in the second counter during a recovery period subsequent to the second period,
Counting a clock pulse derived from the first oscillator at a second rate higher than the first rate in the first counter during the restoration period, the duration of the restoration period being shorter than the duration of the restoration period during the second period Determined based on the number of pulses counted in the second counter
Way.
The method according to claim 1,
And starting said second period if it is determined that power is removed from said first oscillator
Way.
The method according to claim 1,
If the number of clock pulses derived from the second oscillator counted by the second counter during the recovery period is equal to the number of clock pulses derived from the second oscillator counted by the second counter during the second period, End of period
Way.
The method according to claim 1,
The restoration period is the same as the second period
Way.
5. The method according to any one of claims 1 to 4,
During the second period, the second counter increases from a first value to a second value for each clock pulse derived from the second oscillator during the second period,
During the recovery period, the second counter is decremented for each clock pulse derived from the second oscillator during the recovery period until the second counter reaches a third value,
After the recovery period, a clock pulse derived from the first oscillator is counted at the first rate in the first counter
Way.
6. The method of claim 5,
Wherein the first value and the third value are the same
Way.
The method according to claim 6,
Wherein the first value and the third value are zero
Way.
5. The method according to any one of claims 1 to 4,
Wherein at a point within the recovery period the first counter continues to count pulses generated and derived from the first oscillator at the first rate up to the point in time over the second period, Estimating the recovered value of the first counter by extrapolation,
And updating the first counter with the restored value
Way.
5. The method according to any one of claims 1 to 4,
Wherein the second rate is twice the first rate
Way.
5. The method according to any one of claims 1 to 4,
Wherein the second rate is (r + 1) times the first rate and r is an integer
Way.
3. The method of claim 2,
The second period includes a period after a time when power is detected as being restored to the first oscillator so that the first oscillator can stabilize before the restoration period
Way.
5. The method according to any one of claims 1 to 4,
And after the second period of time determining a time based on the value of the first counter
Way.
In an electronic device,
A first oscillator for generating a clock pulse,
A first counter - the value of the first counter represents time -
A second oscillator for generating a clock pulse,
And a second counter,
Wherein the first counter is configured such that a clock pulse derived from the first oscillator is counted from the first counter to a first rate during a first period and a value of the first counter is counted during a second period following the first period A second oscillator connected to the first oscillator so as to be kept independent of a clock pulse derived from the first oscillator,
Wherein the second counter is configured such that a clock pulse derived from the second oscillator is counted by the second counter during the second period and a clock pulse derived from the second oscillator during the restoration period subsequent to the second period, Connected to the second oscillator to be counted in a second counter,
Wherein the first counter is connected to the first oscillator such that a clock pulse derived from the first oscillator is counted at the first counter at a second rate higher than the first rate during the recovery period,
Wherein the duration of the recovery period is determined based on the number of pulses counted in the second counter during the second period
Electronic device.
14. The method of claim 13,
And the connection of the second counter to the second oscillator,
Wherein during the second period the second counter is incremented for each clock pulse derived from the second oscillator to reach a second value from a first value,
During the recovery period, the second counter is decremented for each clock pulse derived from the second oscillator until the second counter reaches a third value,
Wherein the third value is equal to the first value so that the number of clock pulses derived from the second oscillator counted by the second counter during the recovery period is greater than the number of clock pulses derived from the second counter counted by the second counter during the second period, The number of clock pulses derived from the oscillator becomes equal to the number of clock pulses derived from the oscillator
Electronic device.
The method according to claim 13 or 14,
Wherein the second counter is configured to count the second period including a period after a time when detecting that power is restored to the first oscillator to stabilize the first oscillator before the recovery period
Electronic device.

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