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KR101688080B1 - Semiconductor package - Google Patents

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KR101688080B1
KR101688080B1 KR1020150127484A KR20150127484A KR101688080B1 KR 101688080 B1 KR101688080 B1 KR 101688080B1 KR 1020150127484 A KR1020150127484 A KR 1020150127484A KR 20150127484 A KR20150127484 A KR 20150127484A KR 101688080 B1 KR101688080 B1 KR 101688080B1
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passivation film
bonding pad
wire
pad
wire bonding
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한이슬
김경태
김병진
유지연
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앰코 테크놀로지 코리아 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes) consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/4952—Additional leads the additional leads being a bump or a wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 도전성 와이어가 본딩되는 와이어 본딩패드의 구조를 새롭게 개선하여, 캐필러리에 의한 와이어 본딩력에 의하여 본딩패드가 들뜨거나 박리되는 현상을 용이하게 방지할 수 있도록 한 반도체 패키지에 관한 것이다.
이를 위해, 본 발명은 반도체 칩의 본딩패드를 제외한 표면에 형성되는 제1패시베이션 막과; 상기 반도체 칩의 본딩패드로부터 제1패시베이션 막의 원하는 위치까지 도금되는 재배선과; 상기 재배선의 타끝단부를 제외한 제1패시베이션 막의 표면에 적층되는 제2패시베이션 막과; 상기 재배선의 타끝단부 표면 및 둘레면을 감싸면서 금속 결합되는 동시에 제2패시베이션 막의 표면과 동일 평면을 이루거나 그 이상의 높이로 도금되는 와이어 본딩패드; 를 포함하여 구성된 것을 특징으로 하는 반도체 패키지를 제공한다.The present invention relates to a semiconductor package in which the structure of a wire bonding pad to which a conductive wire is bonded is newly improved to easily prevent the phenomenon that the bonding pad is lifted or peeled off by the wire bonding force by the capillary.
To this end, the present invention provides a semiconductor device comprising: a first passivation film formed on a surface of a semiconductor chip excluding a bonding pad; A plating line which is plated from a bonding pad of the semiconductor chip to a desired position of the first passivation film; A second passivation film laminated on the surface of the first passivation film except the other end of the rewiring line; A wire bonding pad which is metal-bonded while being wrapped around the other end surface and the circumferential surface of the rewiring line, and plated to a height equal to or higher than the surface of the second passivation film; And a semiconductor package.

Description

반도체 패키지{SEMICONDUCTOR PACKAGE}[0001] SEMICONDUCTOR PACKAGE [0002]

본 발명은 반도체 패키지에 관한 것으로서, 더욱 상세하게는 도전성 와이어가 본딩되는 본딩패드의 구조를 새롭게 개선하여, 캐필러리에 의한 와이어 본딩력에 의하여 본딩패드가 들뜨거나 박리되는 현상을 용이하게 방지할 수 있도록 한 반도체 패키지에 관한 것이다.
The present invention relates to a semiconductor package, and more particularly, to a semiconductor package which is improved in structure of a bonding pad to which a conductive wire is bonded, and can easily prevent the bonding pad from being lifted or peeled off by a wire bonding force by a capillary To a semiconductor package.

반도체 패키지의 고집적화 및 경박단소화의 요구에 따라 웨이퍼 레벨에서 각 칩을 패키징하여 칩의 크기에 가깝게 제조하는 칩 스케일 패키징 기술이 적용되고 있다.Chip scale packaging technology for packaging each chip at a wafer level and manufacturing it close to the size of the chip is being applied in accordance with the demand for high integration of the semiconductor package and shortening of the light weight.

칩 스케일 패키지의 일례로서, 각 칩의 면적내에 전기적 신호 전달을 위한 솔더볼과 같은 입출력단자가 전기적으로 연결되는 팬-인(fan-in) 패키지와, 별도의 인터포져 등을 이용하여 칩의 면적 바깥쪽까지 도전라인을 연장하는 동시에 연장된 부위에 입출력 단자를 융착하는 팬-아웃(fan-out) 패키지를 들 수 있다.As an example of the chip scale package, a fan-in package in which an input / output terminal such as a solder ball for electric signal transmission is electrically connected in an area of each chip, and a separate interposer, And a fan-out package that extends the conductive line to the extended portion and fuses the input / output terminal to the extended portion.

상기 칩 스케일(scale)의 웨이퍼 레벨(wafer level) 반도체 패키지는 웨이퍼 상태의 반도체 칩에 트랜지스터(transistor) 등을 형성하는 회로 집적 공정과, 반도체 칩을 외부로부터 보호하기 위하여 표면에 패시베이션(passivation)막을 형성하는 공정과, 전도성의 금속 배선라인인 재배선(RDL: Redistribution layer)을 형성하는 공정 등을 통하여 제조된다.The wafer level semiconductor package of the chip scale has a circuit integration process for forming a transistor or the like on a semiconductor chip in a wafer state and a passivation film on the surface for protecting the semiconductor chip from the outside And a step of forming a redistribution layer (RDL), which is a conductive metal wiring line, and the like.

여기서, 첨부한 도 4 및 도 5를 참조로 종래의 칩 스케일 패키지의 구조 및 제조 과정을 살펴보면 다음과 같다.Hereinafter, the structure and manufacturing process of a conventional chip scale package will be described with reference to FIGS. 4 and 5.

먼저, 웨이퍼 상태의 반도체 칩(10)이 제공되며, 이 반도체 칩(10)에는 설계된 회로가 집적되어 있고, 회로의 전기적 입출력 경로가 되는 부분에는 본딩패드(12)가 형성되어 있다.First, a semiconductor chip 10 in a wafer state is provided. A designed circuit is integrated in the semiconductor chip 10, and a bonding pad 12 is formed at a portion of the circuit which becomes an electrical input / output path.

상기 반도체 칩(10)의 본딩패드(12)를 제외한 표면에는 집적된 회로를 보호하기 위한 다이 패시베이션(14)이 형성되고, 다이 패시베이션(14) 위에는 재배선을 형성하기 위하여 일종의 절연막인 제1패시베이션 막(16)이 형성된다.A die passivation 14 for protecting integrated circuits is formed on the surface of the semiconductor chip 10 other than the bonding pads 12. A first passivation layer 14 is formed on the die passivation layer 14, A film 16 is formed.

이때, 상기 반도체 칩(10)에 소정의 배열을 이루며 형성된 다수의 금속패드 즉, 본딩패드(12)는 반도체 칩에 집적된 회로소자를 작동시키는 전압을 인가받기 위한 일종의 금속배선라인인 재배선(18)(RDL: Redistribution layer)의 일단부가 도전 가능하게 연결되도록 외부로 노출된다.A plurality of metal pads formed in the semiconductor chip 10 in a predetermined arrangement, that is, the bonding pads 12, may be a metal wiring line for receiving a voltage for operating a circuit element integrated in the semiconductor chip, 18 (RDL: redistribution layer) is exposed to the outside so as to be conductively connected.

다음으로, 상기 반도체 칩(10)의 본딩패드(12)로부터 제1패시베이션 막(16)의 원하는 위치까지 재배선(18)을 형성하는 공정이 진행된다.Next, a process of forming a rewiring line 18 from the bonding pad 12 of the semiconductor chip 10 to a desired position of the first passivation film 16 is performed.

참고로, 상기 재배선(18)을 형성하는 공정은 제1패시베이션 막 및 본딩패드의 상면에 걸쳐 도금을 위한 시드 레이어를 형성하는 과정과, 그 위에 포토레지스트를 도포한 후 포토레지스트에 대한 통상의 노광 및 디벨롭(exposure & develop)을 실시하여 반도체 칩의 본딩패드와 재배선이 형성될 영역을 노출시키는 과정과, 재배선이 형성될 영역에 재배선를 형성하기 위한 전기도금을 실시하는 과정 등을 포함한다.The process of forming the redistribution line 18 includes the steps of forming a seed layer for plating over the top surfaces of the first passivation film and the bonding pad, Exposure and development are performed to expose a region where a bonding pad and a rewiring line of the semiconductor chip are to be formed and a process of electroplating to form a rewiring line in a region where rewiring is to be formed .

이어서, 상기 제1패시베이션 막(16) 및 재배선(18)의 표면에 걸쳐 제1패시베이션 막(24)을 형성하는 바, 이 제2패시베이션 막(24)은 외부로부터의 기계적 충격, 수분, 각종 이물질 등이 재배선(18)으로 침투하는 것을 차단하는 동시에 서로 인접하는 재배선(18)간의 쇼트 현상을 방지하는 역할을 한다.Subsequently, a first passivation film 24 is formed on the surfaces of the first passivation film 16 and the rewiring lines 18, and the second passivation film 24 is formed on the surface of the first passivation film 16 and the re- Thereby preventing foreign matter or the like from penetrating into the rewiring lines 18 and preventing a short circuit between the rewiring lines 18 adjacent to each other.

이때, 상기 재배선(18)의 타끝단부는 금속 재질의 전극단자인 와이어 본딩 패드가 도금되도록 제2패시베이션 막(24)에 의하여 감싸여지지 않고 외부로 노출되는 상태가 된다.At this time, the other end of the rewiring line 18 is exposed to the outside without being wrapped by the second passivation film 24 so that the wire bonding pad, which is an electrode terminal made of a metal, is plated.

다음으로, 상기 재배선(18)의 타끝단부에 금속 재질의 전극단자인 와이어 본딩패드(26)가 도금 공정에 의하여 형성된다.Next, a wire bonding pad 26, which is an electrode terminal made of a metal, is formed at the other end of the rewiring line 18 by a plating process.

보다 상세하게는, 상기 와이어 본딩패드(26)는 재배선(18)의 타끝단부에 도전 가능하게 도금되는 접속패드(26a)와, 접속패드(26a)로부터 제2패시베이션 막(24)의 측벽 및 측벽 주변의 상면 위치까지 연장되며 도금되는 와이어 연결패드(26b)로 구성되고, 실질적으로 와이어 연결패드(26b)에 캐필러리에 의한 와이어 본딩이 이루어진다.More specifically, the wire bonding pad 26 is provided with a connection pad 26a which is electroplatically plated at the other end of the rewiring line 18 and a connection pad 26b which is electrically connected to the side wall of the second passivation film 24 from the connection pad 26a. And a wire connecting pad 26b extending to an upper surface position around the side wall and plated, and wire bonding by a capillary is substantially performed on the wire connecting pad 26b.

따라서, 상기 와이어 본딩패드(26)의 와이어 연결패드(26b)와, 상기 제2패시베이션 막(24) 위에 적층되는 제2반도체 칩(28) 또는 인접한 다른 칩 또는 기판 상호 간의 전기적인 연결을 위하여 와이어 본딩이 이루어진다.Therefore, for electrical connection between the wire connecting pad 26b of the wire bonding pad 26 and the second semiconductor chip 28 stacked on the second passivation film 24 or another adjacent chip or substrate, Bonding is performed.

예를 들어, 상기 제2반도체 칩(28)의 본딩패드에 와이어 본딩기구인 캐필러리가 도전성 와이어(29)의 일단을 1차 본딩(볼 본딩이라고도 함)을 하고, 연이어 상기 와이어 본딩패드(26)의 와이어 연결패드(26b)에 캐필러리가 도전성 와이어(29)의 타단을 2차 본딩(스티치 본딩이라고도 함)을 실시하게 된다.For example, a capillary, which is a wire bonding mechanism, is bonded to the bonding pad of the second semiconductor chip 28 by first bonding one end of the conductive wire 29 (also referred to as ball bonding) The capillary conducts secondary bonding (also referred to as stitch bonding) of the other end of the conductive wire 29 to the wire connecting pad 26b of the wire bonding pad 26b.

이에, 상기 반도체 칩(10)과 제2반도체 칩(28)이 도전성 와이어(29)와 와이어 본딩패드(26)와 재배선(18)을 통하여 전기적 신호 교환 가능하게 연결되는 상태가 된다.The semiconductor chip 10 and the second semiconductor chip 28 are electrically connected to each other through the conductive wire 29 and the wire bonding pad 26 via the rewiring line 18.

그러나, 상기와 같은 종래의 칩 스케일 패키지 제조 공정 중 다음과 같은 문제점이 발생하고 있다.However, the following problems occur in the conventional chip scale package manufacturing process.

상기 와이어 본딩패드(26)의 접속패드(26a)는 재배선(18) 위에 도금되어 상호 간의 강건한 금속 결합이 이루어진 반면, 실질적인 와이어 본딩이 이루어지는 와이어 연결패드(26b)는 금속(예, 구리) 재질이고, 와이어 연결패드(26b)와 접한 제2패시베이션 막(24)은 절연성 수지계열이므로, 상호 간의 결합력이 떨어질 수 밖에 없는 단점이 있다.The connection pads 26a of the wire bonding pads 26 are plated on the rewiring lines 18 to form a strong metal connection to each other while the wire connection pads 26b to which the actual wire bonding is performed are made of metal And the second passivation film 24 in contact with the wire connection pad 26b is of an insulating resin type.

첨부한 도 5에서 잘 볼 수 있듯이, 상기 와이어 연결패드(26b)와 제2패시베이션 막(24) 간의 결합력이 떨어진 상태에서, 캐필러리가 도전성 와이어(29)를 와이어 연결패드(26b)에 본딩할 때 와이어 연결패드(26)의 반발력이 더해져서, 와이어 연결패드(26b)가 제2패시베이션 막(24)으로부터 들뜨거나 박리되는 현상이 발생하는 문제점이 있다.5, in the state where the bonding force between the wire connecting pad 26b and the second passivation film 24 is distant, the capillary is bonded to the wire connecting pad 26b by the conductive wire 29 There is a problem that the repulsive force of the wire connecting pad 26 is added to cause the wire connecting pad 26b to be lifted or peeled off from the second passivation film 24. [

결국, 상기 와이어 연결패드(26b)가 제2패시베이션 막(24)으로부터 들뜨거나 박리되면, 와이어 연결패드(26b)에 본딩된 도전성 와이어(29)가 끊어지는 등의 불량이 발생하게 된다.
As a result, when the wire connecting pad 26b is lifted or peeled off from the second passivation film 24, a failure such as breakage of the conductive wire 29 bonded to the wire connecting pad 26b occurs.

대한민국 등록특허 등록번호 10-0799878(2008.01.24)Korea Registered Patent Registration No. 10-0799878 (Jan. 24, 2008)

본 발명은 상기와 같은 점을 감안하여 안출한 것으로서, 도전성 와이어가 본딩되는 와이어 본딩패드의 구조를 재배선과 금속 결합되는 구조로 새롭게 개선하여, 캐필러리에 의한 와이어 본딩력에 의하여 본딩패드가 들뜨거나 박리되는 현상을 용이하게 방지할 수 있도록 한 반도체 패키지를 제공하는데 그 목적이 있다.
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a wire bonding pad in which the structure of a wire bonding pad to which a conductive wire is bonded is newly improved, And it is an object of the present invention to provide a semiconductor package that can easily prevent the phenomenon of peeling.

상기한 목적을 달성하기 위한 본 발명의 일 구현예는: 반도체 칩의 본딩패드를 제외한 표면에 형성되는 제1패시베이션 막과; 상기 반도체 칩의 본딩패드로부터 제1패시베이션 막의 원하는 위치까지 도금되는 재배선과; 상기 재배선의 타끝단부를 제외한 제1패시베이션 막의 표면에 적층되는 제2패시베이션 막과; 상기 재배선의 타끝단부 표면 및 둘레면을 감싸면서 금속 결합되는 동시에 제2패시베이션 막의 표면과 동일 평면을 이루거나 그 이상의 높이로 도금되는 와이어 본딩패드; 를 포함하여 구성된 것을 특징으로 하는 반도체 패키지를 제공한다.According to an aspect of the present invention, there is provided a semiconductor device comprising: a first passivation film formed on a surface of a semiconductor chip excluding a bonding pad; A plating line which is plated from a bonding pad of the semiconductor chip to a desired position of the first passivation film; A second passivation film laminated on the surface of the first passivation film except the other end of the rewiring line; A wire bonding pad which is metal-bonded while being wrapped around the other end surface and the peripheral surface of the rewiring line and plated to a height equal to or higher than the surface of the second passivation film; And a semiconductor package.

바람직하게는, 상기 도전성 와이어의 본딩 면적 확보를 위하여, 상기 재배선의 타끝단부는 사각판 형태로 형성되고, 상기 와이어 본딩패드로 재배선의 타끝단부 표면 및 둘레면을 감싸면서 사각패드 형상으로 형성된 것임을 특징으로 한다.Preferably, the other end of the rewiring line is formed in the shape of a rectangular plate to secure the bonding area of the conductive wire, and the other end surface and the peripheral surface of the rewiring line are surrounded by the wire bonding pad, .

또한, 상기 와이어 본딩패드는 재배선과의 금속 결합이 용이한 Ni/Al 재질로 도금된 것을 특징으로 한다.In addition, the wire bonding pad is plated with a Ni / Al material that facilitates metal bonding with rewiring.

상기한 목적을 달성하기 위한 본 발명의 다른 구현예는: 반도체 칩의 본딩패드를 제외한 표면에 형성되는 제1패시베이션 막과; 상기 반도체 칩의 본딩패드로부터 제1패시베이션 막의 원하는 위치까지 도금되는 재배선과; 상기 재배선의 타끝단부를 제외한 제1패시베이션 막의 표면에 적층되는 제2패시베이션 막과; 상기 재배선의 타끝단부 표면에 도금되는 접속패드와, 접촉패드로부터 제2패시베이션 막의 표면 위까지 연장 도금되는 와이어 연결패드로 구성된 와이어 본딩패드를 포함하는 반도체 패키지에 있어서, 상기 제2패시베이션 막에 잠금홈을 형성하고, 상기 와이어 연결패드의 저부에는 잠금홈내에 잠금 삽입되며 도금되는 잠금단을 형성하여서 된 것을 특징으로 하는 반도체 패키지를 제공한다.According to another aspect of the present invention, there is provided a semiconductor device comprising: a first passivation film formed on a surface of a semiconductor chip excluding a bonding pad; A plating line which is plated from a bonding pad of the semiconductor chip to a desired position of the first passivation film; A second passivation film laminated on the surface of the first passivation film except the other end of the rewiring line; And a wire bonding pad composed of a connection pad plated on the other end surface of the rewiring line and a wire connection pad extending from the contact pad to the surface of the second passivation film, And a lock end is formed at the bottom of the wire connection pad to be locked in the lock groove and plated.

바람직하게는, 상기 잠금홈은 제1패시베이션 막 위에 마스크를 덧댄 다음, 제2패시베이션 막을 형성한 후, 마스크를 제거한 자리에 형성되는 것을 특징으로 한다.Preferably, the locking groove is formed in a place where a mask is formed on the first passivation film and then a mask is removed after the second passivation film is formed.

또한, 상기 잠금단은 와이어 본딩패드의 도금 공정시 잠금홈내에 삽입되며 도금되는 것을 특징으로 한다.
The locking end is inserted and plated in the locking groove during the plating process of the wire bonding pad.

상기한 과제 해결 수단을 통하여, 본 발명은 다음과 같은 효과를 제공한다.Through the above-mentioned means for solving the problems, the present invention provides the following effects.

본 발명에 따르면 칩 스케일 패키지의 제조 공정 중, 반도체 칩과 연결된 재배선에 도전 가능하게 적층 형성되는 와이어 본딩패드의 구조를 재배선과 금속 결합되는 구조로 개선하거나, 잠금 결합되는 구조로 개선함으로써, 와이어 본딩패드와 제2반도체 칩 또는 다른 기판 등 간을 도전성 와이어로 연결하는 와이어 본딩 공정 중, 캐필러리에 의한 와이어 본딩력이 작용하여도 와이어 본딩패드가 들뜨거나 박리되는 현상을 용이하게 방지할 수 있다.
According to the present invention, during the manufacturing process of the chip scale package, the structure of the wire bonding pad, which is formed to be conductively stacked on the rewiring line connected to the semiconductor chip, is improved to a structure of rewiring and metal bonding, It is possible to easily prevent the phenomenon that the wire bonding pad is lifted or peeled off even when the wire bonding force by the capillary acts in the wire bonding process of connecting the bonding pad to the second semiconductor chip or another substrate by a conductive wire .

도 1은 본 발명의 제1실시예에 따른 반도체 패키지를 도시한 단면도,
도 2는 본 발명의 제1실시예에 따른 와이어 본딩패드 구조를 나타낸 평면도 및 측면도,
도 3은 본 발명의 제2실시예에 따른 반도체 패키지를 도시한 단면도,
도 4는 종래의 반도체 패키지를 도시한 단면도,
도 5는 종래의 반도체 패키지에서 발생하는 문제점을 도시한 단면도.1 is a cross-sectional view of a semiconductor package according to a first embodiment of the present invention,
2 is a plan view and a side view showing a wire bonding pad structure according to the first embodiment of the present invention,
3 is a cross-sectional view of a semiconductor package according to a second embodiment of the present invention,
4 is a cross-sectional view of a conventional semiconductor package,
5 is a sectional view showing a problem occurring in a conventional semiconductor package;

이하, 본 발명의 바람직한 실시예를 첨부도면을 참조로 상세하게 설명하기로 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

제1실시예First Embodiment

첨부한 도 1은 본 발명의 제1실시예에 따른 반도체 패키지를 도시한 단면도이고, 도 2는 본 발명의 제1실시예에 따른 와이어 본딩패드 구조를 나타낸 평면도 및 측면도이다.FIG. 1 is a cross-sectional view illustrating a semiconductor package according to a first embodiment of the present invention, and FIG. 2 is a plan view and a side view illustrating a wire bonding pad structure according to a first embodiment of the present invention.

먼저, 웨이퍼 상태의 반도체 칩(10)의 본딩패드(12)를 제외한 표면에는 집적된 회로를 보호하기 위한 다이 패시베이션(14)이 형성되고, 다이 패시베이션(14) 위에는 재배선을 형성하기 위하여 일종의 절연막인 제1패시베이션 막(16)이 형성된다.First, a die passivation 14 for protecting an integrated circuit is formed on the surface of the semiconductor chip 10 in the wafer state except for the bonding pad 12, and on the die passivation 14, The first passivation film 16 is formed.

이때, 상기 반도체 칩(10)에 소정의 배열을 이루며 형성된 다수의 금속패드 즉, 본딩패드(12)는 반도체 칩에 집적된 회로소자를 작동시키는 전압을 인가받기 위한 일종의 금속배선라인인 재배선(18)의 일단부가 도전 가능하게 연결되도록 외부로 노출된다.A plurality of metal pads formed in the semiconductor chip 10 in a predetermined arrangement, that is, the bonding pads 12, may be a metal wiring line for receiving a voltage for operating a circuit element integrated in the semiconductor chip, 18 are exposed to the outside so as to be conductively connected.

다음으로, 상기 반도체 칩(10)의 본딩패드(12)로부터 제1패시베이션 막(16)의 원하는 위치까지 재배선(18)을 형성하는 통상의 도금 공정이 진행된다.Next, a conventional plating process for forming a rewiring line 18 from the bonding pad 12 of the semiconductor chip 10 to a desired position of the first passivation film 16 is performed.

이어서, 상기 제1패시베이션 막(16) 및 재배선(18)의 표면에 걸쳐 제2패시베이션 막(24)을 형성하는 바, 이 제2패시베이션 막(24)은 외부로부터의 기계적 충격, 수분, 각종 이물질 등이 재배선(18)으로 침투하는 것을 차단하는 동시에 재배선(18)을 절연 가능하게 감싸서 재배선 간의 전기적 쇼트 현상을 방지하는 역할을 한다.Next, a second passivation film 24 is formed on the surfaces of the first passivation film 16 and the rewiring lines 18, and this second passivation film 24 is formed on the surface of the first passivation film 16 and the rewiring lines 18, Foreign matter or the like is prevented from penetrating into the rewiring line 18, and at the same time, the rewiring line 18 is insulatedly wrapped to prevent electrical shorting between the rewiring lines.

이때, 상기 재배선(18)의 타끝단부는 금속 재질의 전극단자인 와이어 본딩 패드가 도금되도록 제2패시베이션 막(24)에 의하여 감싸여지지 않고 외부로 노출되는 상태가 되고, 와이어 본딩 면적 및 캐필러리에 의한 와이어 본딩 공간을 확보하기 위하여 재배선의 폭에 비하여 더 큰 면적을 갖는 사각판 형태로 형성된다.At this time, the other end of the rewiring line 18 is exposed to the outside without being wrapped by the second passivation film 24 so as to be plated with a wire bonding pad, which is an electrode terminal made of metal, And is formed in the shape of a rectangular plate having a larger area than the width of the rewiring line in order to secure a wire bonding space by the pillars.

다음으로, 상기 재배선(18)의 타끝단부에 와이어 본딩패드(26)를 도금 공정을 이용하여 적층 형성하는 바, 첨부한 도 2에서 잘 볼 수 있듯이 와이어 본딩 면적 및 캐필러리에 의한 와이어 본딩 공간을 확보하기 위하여 재배선(18)의 타끝단부 표면 및 둘레면을 감싸면서 사각패드 형상으로 형성되도록 한다.Next, a wire bonding pad 26 is laminated at the other end of the rewiring line 18 by a plating process. As can be seen in FIG. 2, the wire bonding area and the capillary wire bonding So that the other end surface of the rewiring line 18 and the circumferential surface of the rewiring line 18 are formed to have a square pad shape.

특히, 상기 재배선(18)의 타끝단부의 표면 및 둘레면을 감싸면서 형성되는 와이어 본딩패드(26)는 재배선(예, 구리 재질)과의 금속 결합이 용이한 Ni/Al 재질로 도금됨으로써, 재배선(18)의 타끝단부와 와이어 본딩패드(26)는 금속 결합에 의하여 강건하게 결합되는 상태가 된다.Particularly, the wire bonding pad 26 formed by surrounding the surface and the circumferential surface of the other end of the rewiring line 18 is plated with a Ni / Al material that is easily metal-bonded to a rewiring line (e.g., copper material) And the other end of the rewiring line 18 and the wire bonding pad 26 are in a state of being firmly coupled by metal bonding.

바람직하게는, 상기 재배선(18)의 타끝단부 표면 및 둘레면을 감싸면서 도금되는 와이어 본딩패드(26)는 와이어 본딩시 제2패시베이션 막(24)과 간섭되지 않도록 제2패시베이션 막(24)의 표면과 동일 평면을 이루거나 그 이상의 높이로 도금되도록 한다.The wire bonding pad 26 which is plated while covering the other end surface of the rewiring wire 18 and the circumferential surface of the rewiring wire 18 is preferably formed so as not to interfere with the second passivation film 24 during wire bonding, ) Of the surface of the substrate.

이와 같이 상기 재배선(18)의 타끝단부에 와이어 본딩패드(26)를 형성한 상태에서, 와이어 본딩패드(26)와 주변의 제2반도체 칩(28) 또는 기판 간을 도전성 와이어(29)로 연결하는 와이어 본딩 공정이 진행되면, 와이어 본딩패드(26)가 재배선(18)의 표면 및 둘레면에 걸쳐 강건하게 금속 결합된 상태이므로, 캐필러리에 의한 와이어 본딩력이 와이어 본딩패드(26)에 작용하여도 와이어 본딩패드(26)가 들뜨거나 박리되는 현상을 용이하게 방지할 수 있다.
The conductive wire 29 is connected between the wire bonding pad 26 and the peripheral second semiconductor chip 28 or the substrate in the state where the wire bonding pad 26 is formed at the other end of the re- The wire bonding force of the capillary is applied to the wire bonding pads 26 (26), since the wire bonding pads 26 are firmly metal-bonded on the surface and the circumferential surface of the re- It is possible to easily prevent the wire bonding pad 26 from being lifted or peeled off.

제2실시예Second Embodiment

첨부한 도 3은 본 발명의 제2실시예에 따른 반도체 패키지를 도시한 단면도이다.3 is a cross-sectional view illustrating a semiconductor package according to a second embodiment of the present invention.

먼저, 상기한 제1실시예와 같이 웨이퍼 상태의 반도체 칩(10)의 본딩패드(12)를 제외한 표면에는 집적된 회로를 보호하기 위한 다이 패시베이션(14)이 형성되고, 다이 패시베이션(14) 위에는 재배선을 형성하기 위하여 일종의 절연막인 제1패시베이션 막(16)이 형성된다.First, a die passivation 14 for protecting an integrated circuit is formed on the surface of the semiconductor chip 10 in the wafer state except for the bonding pad 12, as in the first embodiment described above. On the die passivation 14, A first passivation film 16, which is an insulating film, is formed to form a rewiring line.

이때, 상기 반도체 칩(10)에 소정의 배열을 이루며 형성된 다수의 금속패드 즉, 본딩패드(12)는 반도체 칩에 집적된 회로소자를 작동시키는 전압을 인가받기 위한 일종의 금속배선라인인 재배선(18)의 일단부가 도전 가능하게 연결되도록 외부로 노출된다.A plurality of metal pads formed in the semiconductor chip 10 in a predetermined arrangement, that is, the bonding pads 12, may be a metal wiring line for receiving a voltage for operating a circuit element integrated in the semiconductor chip, 18 are exposed to the outside so as to be conductively connected.

다음으로, 상기 반도체 칩(10)의 본딩패드(12)로부터 제1패시베이션 막(16)의 원하는 위치까지 재배선(18)을 형성하는 통상의 도금 공정이 진행된다.Next, a conventional plating process for forming a rewiring line 18 from the bonding pad 12 of the semiconductor chip 10 to a desired position of the first passivation film 16 is performed.

이어서, 상기 제1패시베이션 막(16) 및 재배선(18)의 표면에 걸쳐 제2패시베이션 막(24)을 형성하는 바, 이 제2패시베이션 막(24)은 외부로부터의 기계적 충격, 수분, 각종 이물질 등이 재배선(18)으로 침투하는 것을 차단하는 동시에 재배선(18)을 절연 가능하게 감싸서 재배선 간의 전기적 쇼트 현상을 방지하는 역할을 한다.Next, a second passivation film 24 is formed on the surfaces of the first passivation film 16 and the rewiring lines 18, and this second passivation film 24 is formed on the surface of the first passivation film 16 and the rewiring lines 18, Foreign matter or the like is prevented from penetrating into the rewiring line 18, and at the same time, the rewiring line 18 is insulatedly wrapped to prevent electrical shorting between the rewiring lines.

본 발명의 제2실시예에 따르면, 상기 제2패시베이션 막(24)을 형성할 때, 재배선(18)의 인접 위치에 해당하는 제1패시베이션 막(16) 위에 마스크(미도시됨)를 덧댄 다음, 제2패시베이션 막(24)을 형성하고, 연이어 마스크를 화학적 에칭 공정 등을 이용하여 제거하면, 마스크가 제거된 자리에 잠금홈(30)이 형성된다.According to the second embodiment of the present invention, when forming the second passivation film 24, a mask (not shown) is provided on the first passivation film 16 corresponding to the adjacent position of the rewiring line 18 Next, when the second passivation film 24 is formed and the mask is removed successively by using a chemical etching process or the like, the lock groove 30 is formed in the place where the mask is removed.

다음으로, 상기 재배선(18)의 타끝단부에 와이어 본딩패드(26)를 도금 공정을 이용하여 적층 형성하는 바, 첨부한 도 2에서 잘 볼 수 있듯이 와이어 본딩패드(26)는 재배선(18)의 타끝단부에 도전 가능하게 도금되는 접속패드(26a)와, 접속패드(26a)로부터 제2패시베이션 막(24)의 측벽을 지나 상면 위치까지 연장되며 도금되는 와이어 연결패드(26b)로 구분된다.Next, a wire bonding pad 26 is laminated on the other end of the rewiring line 18 by a plating process. As shown in FIG. 2, the wire bonding pad 26 is electrically connected to a re- And a wire connecting pad 26b extending from the connection pad 26a to the upper surface position through the side wall of the second passivation film 24 and plated Respectively.

이때, 상기 와이어 본딩패드(26)를 도금 공정을 이용하여 Ni/Al 재질로 형성할 때, 실질적인 와이어 본딩이 이루어지는 와이어 연결패드(26b)의 저부에 제2패시베이션 막(24)에 형성된 잠금홈(30)내로 잠금 삽입되는 잠금단(32)이 일체로 도금되어 형성된다.At this time, when the wire bonding pad 26 is formed of a Ni / Al material using a plating process, a lock groove (not shown) formed in the second passivation film 24 is formed on the bottom of the wire connection pad 26b, 30 are integrally plated and formed.

따라서, 상기 와이어 본딩패드(26)의 접속패드(26a)는 재배선(18)의 타끝단부의 표면과 금속 결합되어 강건한 결합 상태를 유지하고, 와이어 본딩패드(26)의 와이어 연결패드(26b)는 잠금단(32)이 잠금홈(30)내로 잠금 삽입되어 제2패시베이션 막(24)과 강건한 결합 상태를 유지하게 된다.Therefore, the connection pad 26a of the wire bonding pad 26 is metal-bonded to the surface of the other end of the rewiring line 18 to maintain a strong bonding state, and the wire connection pad 26b of the wire bonding pad 26, The locking end 32 is locked into the lock groove 30 to maintain a strong coupling state with the second passivation film 24. [

이와 같이 상기 재배선(18)의 타끝단부에 와이어 본딩패드(26)를 형성한 상태에서, 와이어 본딩패드(26)의 와이어 연결패드(26b)와 주변의 제2반도체 칩(28) 또는 기판 간을 도전성 와이어(29)로 연결하는 와이어 본딩 공정이 진행되면, 와이어 연결패드(26b)가 잠금 결합된 상태이므로, 캐필러리에 의한 와이어 본딩력이 와이어 연결패드(26b)에 작용하여도 와이어 연결패드(26b)가 들뜨거나 박리되는 현상을 용이하게 방지할 수 있다.
The wire connecting pad 26b of the wire bonding pad 26 and the second semiconductor chip 28 or the periphery of the wire bonding pad 26 may be connected to each other in the state where the wire bonding pad 26 is formed at the other end of the re- The wire bonding pad 26b is in the locked state so that the wire bonding force by the capillary acts on the wire connecting pad 26b even when the wire bonding process for connecting the liver with the conductive wire 29 is performed, The phenomenon that the pad 26b is lifted or peeled off can be easily prevented.

10 : 반도체 칩
12 : 본딩패드
14 : 다이 패시베이션
16 : 제1패시베이션 막
18 : 재배선
24 : 제2패시베이션 막
26 : 와이어 본딩패드
26a : 접속패드
26b : 와이어 연결패드
28 : 제2반도체 칩
29 : 도전성 와이어
30 : 잠금홈
32 : 잠금단10: Semiconductor chip
12: bonding pad
14: die passivation
16: First passivation film
18: Cultivation line
24: second passivation film
26: wire bonding pad
26a: connection pad
26b: Wire connection pad
28: second semiconductor chip
29: conductive wire
30: Locking groove
32: Locking stage

Claims (6)

삭제delete 삭제delete 삭제delete 반도체 칩의 본딩패드를 제외한 표면에 형성되는 제1패시베이션 막과; 상기 반도체 칩의 본딩패드로부터 제1패시베이션 막의 원하는 위치까지 도금되는 재배선과; 상기 재배선의 타끝단부를 제외한 제1패시베이션 막의 표면에 적층되는 제2패시베이션 막과; 상기 재배선의 타끝단부 표면에 도금되는 접속패드와, 접촉패드로부터 제2패시베이션 막의 표면 위까지 연장 도금되는 와이어 연결패드로 구성된 와이어 본딩패드를 포함하는 반도체 패키지에 있어서,
상기 제2패시베이션 막에 잠금홈을 형성하고, 상기 와이어 연결패드의 저부에는 잠금홈내에 잠금 삽입되며 도금되는 잠금단을 형성하되,
상기 잠금홈은 제1패시베이션 막 위에 마스크를 덧댄 다음, 제2패시베이션 막을 형성한 후, 마스크를 제거한 자리에 형성되고,
상기 잠금단은 와이어 본딩패드의 도금 공정시 잠금홈내에 삽입되며 도금되는 것을 특징으로 하는 반도체 패키지.A first passivation film formed on a surface of the semiconductor chip excluding a bonding pad; A plating line which is plated from a bonding pad of the semiconductor chip to a desired position of the first passivation film; A second passivation film laminated on the surface of the first passivation film except the other end of the rewiring line; And a wire bonding pad composed of a connection pad plated on the other end surface of the rewiring line and a wire connection pad extending from the contact pad to a position above the surface of the second passivation film,
A locking groove is formed in the second passivation film, and a locking end is formed at the bottom of the wire connection pad to be locked and inserted in the locking groove,
The locking groove is formed in a place where a mask is formed on the first passivation film and then a mask is removed after the second passivation film is formed,
Wherein the locking end is inserted and plated in the locking groove during the plating process of the wire bonding pad. 삭제delete 삭제delete
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