KR101684010B1 - Contact structure of semiconductor device - Google Patents

Abstract

The embodiments described above provide a mechanism for forming a contact structure with low resistance. A modified material stack having a plurality of sublayers. Is used to lower the schottky barrier height (SBH) of the conductive layers below the contact structure. The strained material stack includes a SiGe main layer, a graded SiG layer, a GeB layer, a Ge layer and a SiGe upper layer. The GeB layer moves the Schottky barrier to the interface between GeB and the metal germanide, which greatly reduces the Schottky barrier height (SBH). As SBH is lowered, Ge in the upper SiGe layer forms a metal germanide, and a higher B concentration in the GeB layer helps to reduce the resistance of the conductive layer below the contact structure.

Description

[0001] CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE [0002]

Cross reference of related applications

This application is related to the following pending and commonly assigned patent application Serial No. 13 / 672,258, entitled " Contact Structure of Semiconductor Device " (Atty Docket No. TSM12-0787), filed November 8, , Which is incorporated herein by reference.

The present invention relates to a contact structure of a semiconductor device.

As the semiconductor industry moves toward nanometer technology process nodes in pursuit of higher device density, higher performance and lower cost, the challenge from both manufacturing and design issues is to use fin field effect transistors (" ≪ / RTI > has led to the development of a three-dimensional design of semiconductor devices. A typical FinFET is fabricated to have a thin vertical "fin" (or fin structure) that extends from the substrate, for example, formed by etching away a portion of the silicon layer of the substrate. A channel of the FinFET is formed in this vertical pin. Gates are provided on three sides of the pins (for example, wrapping). Having a gate on both sides of the channel enables gate control of the channel from both sides. An additional benefit of FinFETs is that they reduce the short channel effect and include a higher current flow.

However, there are challenges in implementing such features and processes in complementary metal-oxide semiconductor (CMOS) fabrication. For example, silicide formation on a strained material results in high contact resistance of the source / drain regions of the FinFET, thereby degrading device performance.

According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed on the surface of the semiconductor substrate and a recess adjacent to the gate structure. The recesses are formed below the surface of the semiconductor substrate. The semiconductor device structure also includes a strained material stack that fills the recesses, wherein the lattice constant of the material in the strained material stack is different from the lattice constant of the substrate. The strained material stack includes a boron doped (B-doped) germanium (GeB) layer, a metal-Ge layer, and a metal-SiGe layer. The semiconductor device structure further includes a contact structure formed in the interlayer dielectric (ILD) layer, wherein a bottom portion of the contact structure contacts the metal-SiGe layer.

According to some alternative embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed on the surface of the semiconductor substrate and a recess adjacent to the gate structure. The recesses are formed below the surface of the semiconductor substrate. The semiconductor device structure also includes a strained material stack that fills the recesses. The strained material stack includes a SiGe layer, a graded SiGe layer, a boron-doped (B-doped) germanium (GeB) layer, a metal-Ge layer, and a metal-SiGe layer. The semiconductor device structure further includes a contact structure formed in the interlayer dielectric (ILD) layer, wherein a bottom portion of the contact structure contacts the metal-SiGe layer.

However, in accordance with some alternative embodiments, a method of forming a semiconductor device structure is provided. The method includes forming a gate structure formed on a surface of a semiconductor substrate and forming a recess adjacent to the gate structure. The recesses are formed below the surface of the semiconductor substrate. The method also includes forming a strained material stack that fills the recesses. The strained material stack includes a first SiGe layer, a graded SiGe layer, a boron-doped (B-doped) germanium (GeB) layer, a Ge layer, and a second SiGe layer.

The present disclosure is best understood from the following detailed description when taken in conjunction with the accompanying drawings. In accordance with standard practice in industry, it is emphasized that the various features are not drawn to scale but are used for illustration purposes only. Indeed, the dimensions of the various features may be increased or decreased arbitrarily to clarify the description.
1 is a flow chart illustrating a method of manufacturing a contact structure of a semiconductor device according to various aspects of the present disclosure.
2A-2H are schematic cross-sectional views of a semiconductor device including contact structures in various fabrication steps according to various aspects of the present disclosure.
FIG. 3 illustrates various strained materials in a strained material stack that fills the recess immediately adjacent to the gate structure, in accordance with some embodiments.
4A-4C are enlarged cross-sectional views of a portion of a contact structure in various fabrication steps in accordance with various aspects of the present disclosure.

It is to be understood that the following disclosure is intended to provide many different embodiments or examples for implementing various aspects of the disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. These are, of course, merely examples and not intended to be limiting. For example, in the following description, forming the first feature on or on the second feature may include an embodiment in which the first and second features are formed in direct contact, and the first feature and the second feature 2 feature may be formed between the first feature and the second feature such that the feature is not in direct contact with the second feature. In addition, the present disclosure may repeat the reference numerals and / or characters in various examples. This repetition is for the sake of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations described.

Referring to Figure 1, a flow diagram of a method 100 of manufacturing a contact structure of a semiconductor device according to some embodiments is illustrated. The method 100 begins at operation 102, where the substrate includes a gate structure and isolation structures at each side of the gate structure. The method 100 continues with operation 104, wherein a recess is formed between the gate structure and the isolation structure. After the recess is formed, at operation 106, the strained material is epitaxially grown to fill the recess. The deformation material includes a material having a lattice constant different from the lattice constant of the substrate.

The method 100 then continues to operation 108, where an interlayer dielectric (ILD) layer is formed on the substrate to cover the gate structure, the surface of the filled recess, and the isolation structure. The method 100 continues with operation 110, wherein a contact opening is formed in the ILD layer to expose an upper surface of the deformation material filling the recess. Thereafter, the method 100 continues with operation 112, wherein a metal layer and a protective layer are deposited on the surface of the substrate. The metal layer is deposited to form a film in the contact opening, and the protective layer is deposited on the metal layer.

The method 100 then continues at operation 114 where the substrate is thermally processed to form a metal suicide and a metal germanide (Metal-Ge) compound in the area surrounding the bottom of the contact opening and its bottom do. The metal silicide and the metal germanide compound are formed by a metal layer and silicon and germanium in the vicinity of the upper surface of the strained material in contact with the metal layer. Thereafter, at operation 116, the substrate is etched to remove the protective layer and unreacted metal layer. In some embodiments, optional operation 118 is performed after operation 116. Operation 118 is a thermal process used to optimize the resistance of the metal silicide and metal germanium compound formed around the bottom of the contact opening. The additional process sequence is performed later to complete the contact formation and complete the formation of the integrated circuit.

2A-2H illustrate, in accordance with some embodiments, a schematic cross-sectional view of a semiconductor device 200 including contact structures 230 at various fabrication steps. As used in this disclosure, the term semiconductor device 200 refers to a fin field effect transistor (FinFET). FinFET refers to any pin-based multi-gate transistor. In some alternative embodiments, the term semiconductor device 200 refers to a planar metal oxide semiconductor field effect transistor (MOSFET). Other transistor structures and similar structures fall within the contemplated scope of this disclosure. Semiconductor device 200 may be included in a microprocessor, memory cell, and / or other integrated circuit (IC).

In some embodiments, the operation referred to in FIG. 1 does not create a completed semiconductor device 200. The completed semiconductor device 200 may be fabricated using a complementary metal oxide semiconductor (CMOS) technology process. Thus, it should be understood that additional processes may be provided during method 100 and / or after method 100, and some other processes may be described herein briefly, before method 100 of FIG. 2A-2I are simplified for a better understanding of the concepts of the present disclosure. For example, although the figures illustrate semiconductor device 200, it should be understood that the IC may include a number of other devices, including resistors, capacitors, inductors, fuses, and the like.

Referring to Figure 2a and operation 102 of Figure 1, a substrate 20 is provided. In at least one embodiment, the substrate 20 comprises a crystalline silicon substrate (e.g., a wafer). Substrate 20 may include various doped regions depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, the doped region may be doped with a p-type or n-type dopant. For example, the doped region may be doped with a p-type dopant such as boron or BF ₂ , an n-type dopant such as phosphorous or arsenic, and / or combinations thereof. The doped region may be configured for a p-type FinFET or a planar MOSFET.

Substrate 20 may alternatively be made of any suitable semiconductor, such as diamond or germanium, a suitable compound semiconductor such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide, or silicon germanium carbide, gallium arsenide phosphide, or gallium indium And may be made of a suitable alloy semiconductor such as a phosphide. In addition, the substrate 20 may include an epitaxial layer (epilayer), may be strained for enhanced performance, and / or may comprise a silicon-on-insulator (SOI) structure.

In the illustrated embodiment, the substrate 20 further includes a fin structure 202. The fin structure 202 formed on the substrate 20 includes one or more fins. In this embodiment, for simplicity, the fin structure 202 includes a single fin. The fins may comprise any suitable material, for example the fin may comprise silicon, germanium or compound semiconductors. The fin structure 202 may further include a capping layer (not shown) disposed on the pin, which may be a silicon capping layer.

The fin structure 202 is formed using any suitable process, including various deposition, photolithography, and / or etching processes. Exemplary photolithographic processes include forming a photoresist layer (resist) over the substrate 20 (e.g., on a silicon layer), exposing the resist to a pattern, and performing a post-exposure bake process And developing the resist to form a masking element including the resist. The silicon layer may then be etched using a reactive ion etching (RIE) process and / or other suitable process. In one example, the silicon fins of the fin structure 202 may be formed by patterning and etching a portion of the silicon substrate 20. In another example, the silicon fins of the fin structure 202 may be formed by patterning and etching a silicon layer (e.g., an upper silicon layer of a silicon-insulator-silicon stack of a SOI substrate) deposited over an insulator layer. In another embodiment, the fin structure may be formed by epitaxially growing a fin from a substrate in a trench to form a dielectric layer over the substrate, trenching the dielectric layer, and forming a fin.

In the illustrated embodiment, isolation structures 204a, 204b are formed in the substrate 20 to define and electrically isolate the various pins of the fin structure 202. In one example, isolation structures 204a and 204b are shallow trench isolation (STI) structures. The isolation structures 204a and 204b may include silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), low k (lok-K) dielectric materials, and / or combinations thereof. The isolation structures 204a, 204b may be formed by any suitable process. As an example, the formation of the isolation structures 204a, 204b can include filling the trench between the pins with a dielectric material (e.g., using a chemical vapor deposition process). In some embodiments, the filled trench may have a multi-layer structure, such as a thermal oxide liner layer filled with silicon nitride or silicon oxide.

Referring again to Figure 2A, a gate stack 210 is formed on the surface 20s (i.e., fin structure 202) of the substrate between the isolation structures 204a and 204b. In the plane illustrated in the figure, the gate stack 210 extends only on the top surface of the pin, but one skilled in the art will appreciate that in other planes of the device (not shown in the figure) Lt; RTI ID = 0.0 > 202 < / RTI > In some embodiments, the gate stack 210 includes a gate dielectric layer 212 and a gate electrode layer 214 over the gate dielectric layer 212.

In some embodiments, a pair of sidewall spacers 216 are formed on either side of the gate stack 210. In the illustrated embodiment, the gate stack 210 may be formed using any suitable process, including the processes described herein. The hard mask 213 may, in some embodiments, be made of silicon nitride. However, other materials such as silicon carbide, silicon oxynitride and the like may also be used.

In one example, a gate dielectric layer 212 and a gate electrode layer 214 are sequentially deposited over the substrate 20. In some embodiments, the gate dielectric layer 212 may comprise silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant (high k) dielectric. The high k dielectric includes metal oxides. Examples of metal oxides used in the high k dielectric include Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, , Er, Tm, Yb, Lu, and mixtures thereof. In some embodiments, the gate dielectric layer 212 has a thickness in the range of about 10 Angstroms to about 30 Angstroms. The gate dielectric layer 212 may be formed by any suitable process known to those of ordinary skill in the art such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV ozone oxidation, ≪ / RTI > and combinations thereof. Gate dielectric layer 212 may further include an interfacial layer (not shown) to reduce damage between gate dielectric layer 212 and fin structure 202. The interfacial layer may comprise silicon oxide.

In some embodiments, the gate electrode layer 214 may comprise a single layer or multi-layer structure. In at least one embodiment, the gate electrode layer 214 comprises polysilicon. In addition, the gate electrode layer 214 can be a uniform or non-uniformly doped doped polysilicon. In an alternative embodiment, the gate electrode layer 214 comprises a metal selected from the group of W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn and Zr. In an alternate embodiment, the gate electrode layer 214 comprises a metal selected from the group of TiN, WN, TaN, and Ru. In some embodiments, the gate electrode layer 214 has a thickness in the range of about 30 nm to about 60 nm. The gate electrode layer 214 may be formed using a suitable process such as ALD, CVD, PVD, plating, or combinations thereof.

The hard mask 213 may comprise silicon nitride, but other materials such as, for example, silicon carbide, silicon oxynitride, and the like may also be used. In some practical embodiments, hard mask 213 has a thickness in the range of about 50 nm to about 100 nm. The hard mask 213 may be formed using any suitable process, such as ALD, CVD, PVD, plating, or combinations thereof.

A photoresist layer (not shown) is then formed over the gate electrode layer 214 by a suitable process, such as spin-on coating, and patterned to form patterned photoresist features by a suitable lithographic patterning method . In at least one embodiment, the width of the patterned photoresist features ranges from about 5 nm to about 45 nm. The patterned photoresist features are then subjected to one or more etching processes on the underlying layer (i. E. Hard mask 213, gate electrode layer 214 and gate dielectric layer 212) to form gate stack 210 Lt; / RTI > The photoresist layer can then be peeled off.

Continuing with FIG. 2A, in some embodiments, the semiconductor device 200 further includes spacers 216 (dielectric layers) formed on the sidewalls of the gate stack 210. In some embodiments, each of the gate spacers 216 includes a silicon oxide layer (not shown) and a silicon nitride layer over the silicon oxide layer, wherein the silicon oxide layer has a thickness in the range of about 15 A to about 50 A And the thickness of the silicon nitride layer may range from about 50 angstroms to about 200 angstroms. In alternate embodiments, the gate spacers 216 comprise at least one layer comprising silicon oxide, silicon nitride, silicon oxynitride, and / or other dielectric material, respectively. Suitable forming methods include plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), and other deposition methods.

Referring to FIG. 2B and operation 104 of FIG. 1, a fin structure (not shown) is formed to define source and drain (S / D) recesses 206a and 206b below the surface 20s of the substrate 20 adjacent to the gate stack 210. [ (Not where the gate stack 210 and the sidewall spacers 216 pairs are formed on) are etched. As shown in FIG. 2B, each of the S / D recesses 206a and 206b is between the gate stack 210 and one of the isolation structures 204a and 204b.

An isotropic etching may be performed to form the recesses 206a and 206b in the substrate 20 using the gate stack 210 and the pair of sidewall spacers 216 as the etching mask. The isotropic etch may be dry etching, wherein the etchant gas may be selected from CF ₄ , Cl ₂ , NF ₃ , SF _6, and combinations thereof. In an alternative embodiment, the isotropic etch step described above is omitted. Thereafter, wet etching is performed to complete the formation of the recesses 206a and 206b. The wet etching can be performed using, for example, TMAH (Tetra-Methyl Ammonium Hydroxide), potassium hydroxide (KOH) solution or the like. In some exemplary embodiments, the TMAH solution has a concentration ranging from about 1 percent to about 30 percent. After the wet etching, a facet may be formed in the recesses 206a and 206b. In some embodiments, the facets include a (111) face of the substrate 20. In some embodiments, after wet etching, the depth D1 of the recesses 206a and 206b ranges from about 300 angstroms to about 800 angstroms.

After forming the S / D recesses 206a and 206b below the surface 20s of the substrate 20, as shown in Figure 2c and the operation 106 of Figure 1, the recesses 206a and 206b of Figure 2b, Is filled by epitaxially growing a strained material stack 208. The lattice constant of the deformed material stack 208 is different from the lattice constant of the substrate 20. As a result, the channel region of the semiconductor device 200 is deformed or pressed to improve the carrier mobility of the device.

In some embodiments, the modified material stack 208 includes Si, Ge, SiGe, SiC, SiP, P-type dopants or III-V semiconductor materials. FIG. 3 illustrates various deformable materials within a modified material stack 208, in accordance with some embodiments. The various materials in the modified material stack 208 are all epitaxially grown. In some embodiments, the modified material stack 208 of FIG. 3 includes a first SiGe (silicon germanium) layer (or a main SiGe layer) 208 _A , a graded SiGe layer 208 _B , It includes GeB layer (doped with boron germanium) (208 _C), selective Ge layer (208 _D), and the SiGe layer 2 (208 _E). The SiGe layer 1 (208 _A) fills most of the concave portions (206a and 206b). The various layers (208 _B , 208 _C , 208 _D, and 208 _E ) on the first SiGe layer assist in the formation of metal silicide and metal germanide compounds at the bottom of the above-described contact openings and in the region surrounding the bottom thereof.

In advanced technology, the critical dimensions of the contacts continue to decrease. The metal silicide is used to connect between the S / D region and the contact plug (or contact) having a low resistivity. Equation (1) shows the relationship between the factors that affect the resistivity and resistivity of a conductive material, such as a metal silicide or a metal germanide, formed after the semiconductor material.

_B / SQRT(N)] ……(1)r? exp [C x SQRT (m) x

_B / SQRT (N)] ... ... (One)

_B는 반도체 재료 재료와, 금속 실리사이드 또는 금속 저마나이드를 형성하는데 사용되는 금속 사이의 SBH(Schottky barrier height)이다. N은, 반도체 재료에서의 도펀트(B 등) 농도이다.In equation (1), SQRT means the square root. C is a constant, and m is the atomic mass of the semiconductor material in the source and drain regions, such as Si or Ge.

_B is the Schottky barrier height (SBH) between the semiconductor material and the metal used to form the metal suicide or metal germanide. N is the dopant (B, etc.) concentration in the semiconductor material.

_B는 감소될 수 있다. 또한, N은 또한 증가될 수 있다. Ge의 원자 질량은 Si보다 낮다. 반도체 재료를 가진 금속 실리사이드 또는 금속 저마나이드 인터페이스에 제공되는 Si 대신에, Ge를 가지면, 콘택 저항률을 감소시킬 수 있다. Ti 또는 Ni와 같은 금속 사이에 형성된 TiSi 또는 NiSi와 같은, 금속 실리사이드에 SBH(

_B)는 약 0.6 eV이다. 이와 반대로, NiGe와 GeB 사이의 SBH는 약 0.1 eV까지 감소될 수 있다. 따라서, NiGe와 같은 금속-Ge 또는 기타 금속-Ge와, GeB 사이에 형성된 쇼트키 배리어를 가지는 것이 바람직하다. 게다가, GeB와 같은 반도체 재료에서의 도펀트(B 등) 농트는 N 값을 증가시키기 위하여 높게 유지되어야 한다.In order to reduce the resistivity, m and / or

_B can be reduced. Furthermore, N can also be increased. The atomic mass of Ge is lower than that of Si. Having Ge instead of a metal silicide with a semiconductor material or Si provided at a metal germanide interface can reduce the contact resistivity. A metal silicide, such as TiSi or NiSi formed between a metal such as Ti or Ni,

_B ) is about 0.6 eV. Conversely, the SBH between NiGe and GeB can be reduced to about 0.1 eV. Therefore, it is preferable to have a Schottky barrier formed between Ge-B and metal-Ge or other metal-Ge such as NiGe. In addition, the dopant (B, etc.) concentration in semiconductor materials such as GeB must be kept high to increase the N value.

Graded SiGe layer (208 _B) is required to prevent the substrate Si / EPI SiGe lattice mismatch induced displacement (dislocation). The GeB layer 208 _C may lower the SBH, which is described below. The optional Ge layer (208 _D ) can reduce the risk of galvanic corrosion. The second SiGe layer 208 _E is formed by depositing a metal-SiGe layer that can protect the metal germanide layer, which may be formed after thermal anneal, from being removed, during a subsequent wet etch process on the unreacted metal that has been removed .

In some embodiments, a pre-cleaning process is performed to clean the S / D recesses 206a and 206b with an HF solution or other suitable solution prior to forming the deformed material stack 208. Thereafter, the strained material 208 is sequentially and selectively grown by a low pressure CVD (LPCVD) process to fill the S / D recesses 206a and 206b. In some embodiments, the LPCVD process is performed at a temperature in the range of about 400 ° C to about 800 ° C and under a pressure in the range of about 1 Torr to about 15 Torr. In some embodiments, the reaction gas used to form the deformable material stack 208, SiH _4, SiH ₂ Cl _2, HCl, GeH _4, various combinations of _{Ge 2 H 6, B 2 H} 6, and H ₂ .

The layer (208 _A) 1 SiGe (Silicon Germanium) are formed on the substrate surface of the concave portion (206a and 206b). In some embodiments, Ge content (at%) in the SiGe layer 1 (208 _A) is in the range of from about 15% to about 30%. In some embodiments, the thickness of the SiGe layer 1 (208 _A) is in the range of from about 15 to about 30 ㎚ ㎚.

That, graded SiGe layer (208 _B) and then is formed on the SiGe layer 1 (208 _A). Graded concentrations of the SiGe layer (208 _B) is increased from a Ge concentration of the SiGe layer 1 in the (208 _A) closer to the top value on the concentration of Ge in GeB layer (208 _C). The concentration of Ge in a In some embodiments, a graded SiGe layer (208 _B) is to be the top from the bottom of the layer is increased in the range of from about 30% to about 80%. In some embodiments, the thickness of the graded SiGe layer (208 _B) is in the range of from about 15 to about 30 ㎚ ㎚.

As discussed above, the Schottky barrier will be formed at the interface between GeB and the metal-Ge layer formed over GeB after thermal annealing. In order to lower the resistivity of the metal suicide and the metal germanide compound, the B concentration of the GeB layer (208 _C ) should be as high as possible. In some embodiments, B concentration is in the range of approximately 4E20 atoms / cm ³ to about 1E21 atoms / cm ^3. To increase the B dopant density, in some embodiments, the reactive ion mixture to form the GeB layer comprises Ge ₂ H ₆ . In some embodiments, the thickness of the GeB layer 208 _C ranges from about 8 nm to about 20 nm.

Selective Ge layer (208 _D) is open after the annealing GeB layer (208 _C) (doped Ge layer) and a galvanic corrosion caused by the difference in chemical potential between the GeB layer (208 _C), metal germanium arsenide layer formed on a In order to prevent or reduce the risk. In some embodiments, the thickness of the Ge layer 208 _D ranges from about 15 nm to about 35 nm.

A second SiGe layer 208 _E is formed by depositing a Ge layer 208 _D (if this is present) or a GeB layer 208 _C [Ge (if present), to form a protective layer on the underlying metal germanide from a subsequent wet etch. Layer 208 _D does not exist). ≪ / RTI > In some embodiments, the thickness of the second SiGe layer 208 _E ranges from about 1 nm to about 10 nm. In some embodiments, the various layers in the modified material stack 208 are formed in the same process chamber. However, it is possible to form these various layers in more chambers than one chamber.

Process operations up to this point are provided in the substrate 20 with the strained stack 208 in the S / D trenches 206a and 206b. An interlayer dielectric (ILD) is formed on the modified material stack 208, the gate stack 210, the pair of sidewall spacers 216, and the isolation regions 204a and 204b, as shown in FIGS. 2d and 2e and operation 108 in FIG. ) Layer 218 is deposited. The ILD layer 218 includes a dielectric material. The dielectric material may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbon- SiCOH) and / or combinations thereof. In some embodiments, the ILD layer 218 is formed over the deformable material 208 by CVD, high density plasma (HDP) CVD, sub-atmospheric CVD (SACVD), spin on, sputtering, . In this embodiment, the ILD layer 218 has a thickness ranging from about 4000 A to about 8000 A. It should be understood that the ILD layer 218 may include one or more dielectric materials and / or one or more dielectric layers.

Thereafter, according to some embodiments, the ILD layer 218 is planarized using a chemical mechanical polishing (CMP) process until the hard mask 213 is removed. After the hard mask is removed, alternative gates are formed to replace gate dielectric layer 212 and gate electrode layer 214, according to some embodiments, as shown in Figure 2E. In an alternate embodiment, the gate dielectric layer 212 and the gate electrode layer 214 are not replaced with a replacement gate stack 210 '. In embodiments in which a replacement gate stack 210 'is formed, the gate dielectric layer 212 and the gate electrode layer 214 function as a dummy gate stack. Figure 2E illustrates an exemplary structure including a replacement gate stack 210 '. In some embodiments, the gate dielectric layer 212 'and the gate electrode layer 214' are sequentially deposited to fill openings left by the removed dummy gate stack, followed by CMP to form a gate dielectric layer 212 ' And the excess portion of the gate electrode layer 214 '. The remaining replacement gate includes a gate dielectric layer 212 'and a gate electrode layer 214'. The gate dielectric layer 212 'may comprise a high-k dielectric material having a k value greater than, for example, greater than about 7.0, and the gate dielectric layer 214' may comprise a metal or metal alloy.

The subsequent CMOS processing steps applied to the semiconductor device 200 of FIG. 2E include forming a contact opening through the ILD layer 218 to provide electrical contact to the S / D region of the semiconductor device 200. Referring to FIG. 2F, the structure of FIG. 2F is created by forming openings 220 in the ILD layer 218 to expose a portion of the deformed material stack 208. The process at operation 110 of FIG. 1 is described. As an example, the formation of the openings 220 may be accomplished by forming a photoresist layer (not shown) on the ILD layer 218 by a suitable process, such as spin-on coating, by patterning the photoresist features by a suitable lithographic method (E.g., by using a dry etch, a wet etch, and / or a plasma etch process) to etch the exposed ILD layer 218 to remove portions of the ILD layer 218 Thereby exposing a portion of the deformation material 208. The opening 220 is above the deformation material 208 and the opening 220 has a bottom 220b in contact with the sidewall 220a of the ILD layer 218 and the top surface of the strained material stack 208 . The patterned photoresist layer can then be peeled off.

According to some embodiments, after the opening 220 is formed, a conductive layer is formed at the bottom of the opening 220. After forming openings 220 in ILD layer 218, a metal layer 222 is deposited to coat the interior of openings 220 and a metal layer 222 The protective layer 223 is deposited. 4A shows a schematic cross-sectional view of a material layer that is close to the opening 220 after deposition of the metal layer 222 and the protective layer 223, according to some embodiments. The metal layer 222 may be composed of various metal types that form a metal germanium with Si-containing metal-silicide and / or Ge after a thermal process (or thermal anneal). In some embodiments, the metal is comprised of Ti, Al, Mo, Zr, Hf, Ta, In, Ni, Be, Mg, Ca, Y, Ba, Sr, Sc, or Ga. In FIG. 4A, Ni is used as an example for the metal layer 222. The protective layer 223 protects the metal layer 222 from being oxidized during a subsequent thermal process (or annealing process). The protective layer 223 must be thermally stable to, for example, 900 占 폚. Further, the protective layer 223 is made of TiN, TaN or a combination thereof. In Fig. 4A, TiN is used as an example for the metal layer 223. Each of the layers 222 and 223 may be formed by PVD, CVD, ALD, or other applicable process. In some embodiments, the metal layer 222 has a thickness in the range of about 5 nm to about 15 nm. In some embodiments, the protective layer 223 has a thickness in the range of about 5 nm to about 20 nm.

In one embodiment, the upper surface of the deformed material stack 208 is lower than the major surface 20s (not shown). In another embodiment, a strained material stack 208 that fills S / D recess 206 extends upward over surface 20s (not shown).

After the layers 222 and 223 have been deposited, the thermal process (or annealing process) at operation 114 may be performed at the bottom of the contact opening and in the area surrounding the bottom thereof, as described for operation 114 in FIG. Silicide and a metal germanide compound. In some embodiments, the thermal process is a rapid thermal annealing (RTA) process. The temperature ranges from about 150 ° C to about 300 ° C. In some embodiments, the duration of the RTA process ranges from about 20 seconds to about 100 seconds.

Figure 4B shows a schematic cross-sectional view of the material layer of Figure 4A after the thermal process of operation 114, in accordance with some embodiments. In the embodiment of Figures 4A and 4B, the metal in the metal layer 22 is comprised of Ni. During the thermal process, Ni in the metal layer 222 is diffused into the second SiGe layer 208 _E after the thermal process to form a Ni-doped SiGe (or NiSiGe) layer 208 _E '. In some embodiments, the thickness of the NiSiGe layer (208 _E ') ranges from about 1 nm to about 10 nm. The Ni-doped SiGe (or NiSiGe) layer 208 _E 'occupies only the area near the bottom of the contact opening 220. The remainder of the second SiGe layer 208 _E remains unchanged.

A portion of Ni from the metal layer 222 is diffused past the second SiGe layer 208 _E and contacts the Ge layer 208 _{D to form a} Ni-doped Ge (or NiGe, nickel germanide) layer 208 _D '). As noted in FIG. 4B, the NiGe layer 208 _D 'is formed primarily below the bottom of the contact opening 220. Ge detached from the bottom of the contact opening layer (208 _D) is left unchanged. Very thin Ge layer (208 _D ") is present between the NiGe layer (208 _D ') and GeB layer (208 _B'). In some embodiments, NiGe layer (208 _D) a very thin Ge layer (208 _D below Quot;) has a thickness in the range of about 2 A to about 10 A. The GeB layer 208 _C 'may undergo some minimum change with respect to some Ge moving upwards into the Ge layer 208 _D ' to form NiGe with Ni from the metal layer 222. The graded SiGe layer 208 _B 'is left substantially similar to the graded SiGe layer 208 _B in some embodiments. The first SiGe layer 208A is left substantially unaltered in some embodiments as well. The NiSiGe layer 208 _E 'and the NiGe layer 208 _D have conductivity.

After the thermal process of operation 114, an etch operation 116 is performed to remove the protective layer 223 and unreacted metal layer 222, as described for operation 116 of FIG. In some embodiments, a wet etch process is used in an etch operation 116. In some embodiments, the wet etch process utilizes H ₂ SO ₄ and H ₂ O ₂ . In some embodiments, the etching process also includes FeCl ₃ in the etch chemistry. Figure 4c shows the structure of Figure 4b after a wet etch process, in accordance with some embodiments. 4C shows that the protective layer 223 and the unreacted metal layer 222 are removed. In some embodiments, a portion of the NiSiGe layer (208 _E ') rises above the bottom surface (224) of the contact opening (220). In some embodiments, the NiSiGe layer 208 _E 'has a "U" shape and the upper surface of the NiSiGe layer 208 _E ' extends over the surface 20s. The very thin Ge layer 208 _{D &} quot ;, present between the NiGe layer 208 _D 'and the GeB layer 208 _B ', causes galvanic corrosion due to differences in the chemical potential between NiGe and GeB during the wet etch process However, the very thin Ge layer 208 _D "is eventually vanished due to subsequent thermal processing. The Ge in the very thin Ge layer 208 _D "moves to either the NiGe layer 208 _D 'or the GeB layer 208 _B ', or both, and the layers 208 _D 'and 208 _B ' ).

As described with respect to operation 118 of FIG. 1, after the wet etch process of operation 116, another thermal process is performed to optimize the resistance of the metal suicide and the metal germanide compound formed around the bottom of the contact opening. In some embodiments, the thermal process is a rapid thermal annealing (RTA) process. The temperature ranges from about 150 ° C to about 300 ° C. In some embodiments, the duration of the RTA process ranges from about 20 seconds to about 100 seconds. In some embodiments, operation 116 is omitted.

FIG. 4C shows the interface 229 between the semiconductor GeB layer 208 _C and the conductive NiGe layer 208 _D '. The interface 229 is the position of the short-circuit barrier. As described above, the SBH between NiGe (metal-Ge) and GeB is lower than NiSi (metal-Si) and SiGeB, which reduces the resistance of metal-Ge (or metal germanide). Using Ge as a major component of the semiconductor layer and keeping the B concentration in the GeB layer high also helps to reduce the resistance of the metal-Ge. As a result, the contact resistance can be lowered. In the above-described embodiment, Ni is used as the metal layer. In addition to Ni, other types of metals such as Ti, Mo, Au, Ag, etc. may also be used.

As described above, an additional process sequence is performed later to complete the contact formation. FIG. 2G shows, in accordance with some embodiments, a barrier layer 226 that forms a film in the contact opening 220 and that the conductive layer 227 is deposited later to fill the contact opening. The barrier layer 226 can promote adhesion between the conductive layer 227 and the ILD layer 218. In addition, if the conductive layer 227 is comprised of a diffusion element such as Cu, the barrier layer 226 can block diffusion into neighboring layers or structures. In some embodiments, the barrier layer 226 includes Ti, TiN, Ta, TaN, or a combination thereof. The barrier layer 226 may be formed by PVD, ALD, or other applicable process. In some embodiments, the thickness of layer 226 ranges from about 1 nm to about 10 nm. The barrier layer 226 contacts the NiSiGe layer 208 _E 'at the bottom of the contact opening.

The conductive layer 227 may be comprised of any conductive metal or metal alloy. Examples of suitable conductive metals for layer 277 include, but are not limited to, Cu, Al, W, Pt, Au, Ag, and the like. The conductive layer 227 may be formed by plating, PVD, ALD, or other applicable process. In some embodiments, the thickness of layer 227 ranges from about 100 nm to about 200 nm.

After the contact openings 220 are filled, a planarization process, such as a chemical mechanical polishing (CMP) process, is performed to remove the barrier layer 226 and the conductive layer 227 outside the contact openings 220. Figure 2h shows the barrier layer 226 and conductive layer 227 outside the contact opening 220 removed by the planarization process. The remaining barrier layer 226 and conductive layer 227 in the contact openings form a contact structure (or contact plug) 230. As the resistance of the conductive layer, such as the NiSiGe layer 208 _E 'and the NiGe layer 208 _D ', below the contact structure 230 is lowered using the mechanism described above, the overall contact resistance is significantly lowered.

After the steps shown in FIG. 1 are performed, as further illustrated in connection with the example shown in FIGS. 2A through 2H, a subsequent process, including interconnection processing, is performed to complete semiconductor device 200 fabrication do.

In the illustrated embodiment, the alternate gate stack 201 'is formed by a gate-last process. In an alternate embodiment, the gate stack 210 is maintained (gate-first).

The embodiments described above provide a mechanism for forming a contact structure with low resistance. A modified material stack having a plurality of sub-layers is used to lower the schottky barrier height (SBH) of the conductive layers below the contact structure. The strained material stack includes a SiGe main layer, a graded SiG layer, a GeB layer, a Ge layer and a SiGe upper layer. The GeB layer moves the Schottky barrier to the interface between GeB and the metal germanide, which greatly reduces the Schottky barrier height (SBH). As SBH is lowered, Ge in the upper SiGe layer forms a metal germanide, and a higher B concentration in the GeB layer helps to reduce the resistance of the conductive layer below the contact structure.

While the invention has been described by way of example and in terms of a preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, the invention is intended to cover various modifications and similar arrangements, which will become apparent to those skilled in the art. Accordingly, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims (20)

As a semiconductor device structure,
A gate structure formed on the surface of the semiconductor substrate,
A recess adjacent to the gate structure, the recess being formed below the surface of the semiconductor substrate;
Wherein the lattice constants of the material in the strained material stack differ from the lattice constants of the substrate and the strained material stack is a boron-doped (B-doped) germanium (GeB ) Layer, a metal-Ge layer, and a metal-SiGe layer,
A contact structure formed in an inter-layer dielectric (ILD) layer, the bottom portion of the contact structure contacting the metal-SiGe layer. 2. The semiconductor device structure of claim 1, wherein the strained material stack further comprises a germanium (Ge) layer between the GeB layer and the metal-Ge layer. According to claim 1, wherein the semiconductor device structure, to obtain a range of boron concentration of the GeB layer, 1E20 atoms / cm ³ to about 4E20 atoms / cm ^3. 2. The semiconductor device structure of claim 1, wherein the strained material stack further comprises a SiGe layer, wherein a predetermined portion of the recess is filled with the SiGe layer, and the SiGe layer fills a bottom portion of the recess. The structure of claim 1, wherein the metal element in the metal-Ge layer and the metal element in the metal-SiGe layer are the same. The method of claim 1, wherein the metal element in the metal-Ge layer and the metal element in the metal-SiGe layer are selected from the group consisting of Ti, Al, Mo, Zr, Hf, Ta, In, Ni, Be, Mg, , Sr, Sc, or Ga. 2. The semiconductor device structure of claim 1, wherein the strained material stack extends upwardly over a surface of the semiconductor substrate. As a semiconductor device structure,
A gate structure formed on the surface of the semiconductor substrate,
The recess being adjacent to the gate structure, the recess being formed beneath a surface of the semiconductor substrate;
Wherein the strained material stack comprises a SiGe layer, a graded SiGe layer, a boron-doped (B-doped) germanium (GeB) layer, a metal- SiGe < / RTI > layer,
A contact structure formed in an interlayer dielectric (ILD) layer, the bottom portion of the contact structure contacting the metal-SiGe layer. A method of forming a semiconductor device structure,
Forming a gate structure formed over the surface of the semiconductor substrate,
Forming a recess adjacent to the gate structure, the recess being formed beneath the surface of the semiconductor substrate;
Forming a deformation material stack that fills the recesses, the deformation material stack comprising a first SiGe layer, a graded SiGe layer, a boron-doped (B-doped) germanium (GeB) 2 < / RTI > SiGe < RTI ID = 0.0 > layer. ≪ / RTI > 10. The method of claim 9,
Forming a contact structure formed in the interlayer dielectric (ILD) layer,
Depositing a metal layer and a protective layer sequentially on the contact structure,
Further comprising performing thermal annealing to induce a metal in the metal layer to the second SiGe layer and the Ge layer. delete delete delete delete delete delete delete delete delete delete

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