KR101654339B1 - Wafer-level light emitting diode package and method of fabricating the same - Google Patents

Abstract

A wafer level light emitting diode package and a method for manufacturing the same are disclosed. The light emitting diode package includes: a semiconductor multilayer structure including a first conductive upper semiconductor layer, an active layer, and a second conductive lower semiconductor layer; A plurality of contact holes exposing the first conductive type upper semiconductor layer through the second conductive type lower semiconductor layer and the active layer; A first bump located under the semiconductor stacked structure and electrically connected to the first conductive type upper semiconductor layer exposed in the plurality of contact holes; A second bump located under the semiconductor laminated structure and electrically connected to the second conductive type lower semiconductor layer; And a protective insulating layer covering the side wall of the semiconductor laminated structure.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a wafer level light emitting diode package,

The present invention relates to a light emitting diode package and a method of manufacturing the same, and more particularly, to a wafer level light emitting diode package and a method of manufacturing the same.

A light emitting diode is a semiconductor element having an N-type semiconductor and a P-type semiconductor, and emits light by recombination of electrons and holes. Such light emitting diodes are widely used as display devices, traffic signals, and backlights. In addition, the light emitting diode has a smaller consumed electric power and longer life than conventional light bulbs or fluorescent lamps, and has been widely used for general lighting purposes in place of incandescent lamps and fluorescent lamps.

The light emitting diode is usually used finally as a light emitting diode module. The light emitting diode module is fabricated by wafer-level LED chip manufacturing process, packaging process and module process. That is, after semiconductor layers are grown on a growth substrate such as a sapphire substrate, the semiconductor layers are fabricated as a chip having electrode pads through a patterning process at a wafer level, and are divided into individual chips (chip fabrication process). Thereafter, the individual chips are mounted on a lead frame or printed circuit board or the like, the electrode pads are electrically connected to the lead terminals by using bonding wires, and the light emitting diode chips are molded by the molding member to fabricate the light emitting diode package (Packaging process). Thereafter, the LED package is mounted on a circuit board such as an MC-PCB to complete a light emitting diode module such as a light source module (module process).

By the packaging process, the light emitting diode chip is protected from the external environment by the housing and / or the molding member. Further, by including the phosphor in the molding member, a white light emitting diode package suitable for a white light source can be provided. The white light emitting diode package is mounted on a circuit board such as an MC-PCB and a secondary lens for adjusting the directivity of light emitted from the light emitting diode package is mounted on the light emitting diode package, Can be provided.

However, a light emitting diode package using a conventional lead frame, a printed circuit board, or the like is not only difficult to miniaturize, but also has limitations in improving heat dissipation characteristics. Furthermore, it is well known that the light emitting efficiency of a light emitting diode is reduced by light absorption by a lead frame or a printed circuit board, resistance heat generation by a lead terminal, and the like.

Further, since the chip manufacturing process, the packaging process, and the module manufacturing process are performed separately, the time and cost required for manufacturing the light emitting diode module increases.

A problem to be solved by the present invention is to provide a wafer level light emitting diode package that can be modularized on a direct circuit board without using a conventional lead frame or a printed circuit board, and a method of manufacturing the same.

Another object of the present invention is to provide a light emitting diode package having high efficiency and high heat dissipation characteristics and a method of manufacturing the same.

Another object of the present invention is to provide a method of manufacturing a light emitting diode package that can reduce the time and cost required for manufacturing a light emitting diode module.

Another object of the present invention is to provide a light emitting diode module having high efficiency and high heat dissipation characteristics and a method of manufacturing the same.

According to one aspect of the present invention, there is provided a light emitting diode package including: a semiconductor multilayer structure including a first conductive upper semiconductor layer, an active layer, and a second conductive lower semiconductor layer; A plurality of contact holes through the second conductive lower semiconductor layer and the active layer to expose the first conductive upper semiconductor layer; A first bump located under the semiconductor laminated structure and electrically connected to the first conductive upper semiconductor layer exposed in the plurality of contact holes; A second bump located under the semiconductor laminated structure and electrically connected to the second conductive type lower semiconductor layer; And a protective insulating layer covering a side wall of the semiconductor laminated structure.

The protective insulating layer covers the entire side wall of the semiconductor laminated structure to protect the semiconductor laminated structure from an external environment, such as moisture. Further, the first bumps and the second bumps may have the same height as each other, and their cross-sections may be located on the same plane. The light emitting diode package may be electrically connected to a circuit board such as an MC-PCB through the first bump and the second bump.

The light emitting diode package according to the present invention is a wafer level package that can be directly mounted on a circuit board such as an MC-PCB and can be modularized. The light emitting diode package is distinguished from a conventional light emitting diode package using a lead frame or a printed circuit board, And is distinguished from an ordinary light emitting diode chip packaged using a frame or a printed circuit board.

On the other hand, a wavelength converter may be disposed on the first conductive upper semiconductor layer. The wavelength converter is composed of a material different from that of the protective insulating layer and is distinguished from the protective insulating layer. The wavelength converter may be a phosphor sheet or a doped monocrystalline substrate. The side surface of the wavelength converter may be parallel to the protective insulating layer. That is, the wavelength converter covers the upper surface of the protective insulating layer.

The protective insulating layer may include a silicon oxide film or a silicon nitride film, and may be formed as a single layer or a multilayer. Alternatively, the protective insulating layer may be a distributed Bragg reflector in which insulating layers having different refractive indices are repeatedly laminated.

Meanwhile, the first conductive upper semiconductor layer may have a roughened surface. The roughened surface improves the light extraction efficiency.

In some embodiments, the sides of the first and second bumps may be covered by an insulating layer. This insulating layer covers at least a part of the side surfaces of the first and second bumps. Also, a dummy bump may be located between the first and second bumps. The dummy bumps emit heat generated in the semiconductor laminated structure.

In some embodiments, the light emitting diode package may further include an insulating substrate having through holes, and the first and second bumps may be formed in the through hole of the insulating substrate. The insulating substrate may be a sapphire substrate or a silicon substrate.

The light emitting diode package may include: a second contact layer contacting the second conductive type lower semiconductor layer; A first contact layer including first contact portions electrically contacting the first conductive upper semiconductor layer in the plurality of contact holes and a connection portion connecting the first contact portions to each other; A first insulating layer interposed between the first contact layer and the second contact layer to cover the second contact layer; And a second insulating layer covering the first contact layer under the first contact layer. The first bump may be located below the second insulating layer and be electrically connected to the first contact layer and the second bump may be located below the second insulating layer and electrically connected to the second contact layer, .

The protective insulating layer may be formed by the first insulating layer and / or the second insulating layer. Accordingly, the protective insulating layer may include the first insulating layer and / or the second insulating layer.

Furthermore, the light emitting diode package may further include: a first electrode pad located below the second insulating layer and connected to the first contact layer through the second insulating layer; And a second electrode pad located under the second insulating layer and connected to the second contact layer through the second insulating layer and the first insulating layer. The first bump and the second bump may be electrically connected to each other under the first electrode pad and the second electrode pad, respectively.

Also, at least one of the first insulating layer and the second insulating layer may be a distributed Bragg reflector.

According to another aspect of the present invention, there is provided a light emitting diode module including the above-described light emitting diode package. This module is a circuit board; The light emitting diode package mounted on the circuit board and a lens for adjusting a directivity angle of light emitted from the light emitting diode package. Furthermore, the circuit board may be an MC-PCB, and a plurality of the LED packages may be mounted on the MC-PCB.

According to another aspect of the present invention, a method of manufacturing a light emitting diode package is provided. The method includes: forming a semiconductor laminated structure including a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer on a growth substrate; patterning the semiconductor laminated structure to form a chip isolation region; Forming a plurality of contact holes exposing the first conductivity type semiconductor layer by patterning the second conductivity type semiconductor layer and the active layer, forming a protective insulation layer covering the side walls of the semiconductor laminated structure in the chip isolation region, And forming the first bump and the second bump on top of the laminate structure. The first bump is electrically connected to the first conductive type semiconductor layer exposed in the plurality of contact holes, and the second bump is electrically connected to the second conductive type semiconductor layer.

In some embodiments, the growth substrate may include an impurity for converting the wavelength of light generated in the active layer. The growth substrate may be a sapphire or silicon substrate.

In some embodiments, the method may further include removing the growth substrate to expose the first conductivity type semiconductor layer, and attaching the phosphor sheet on the exposed first conductivity type semiconductor layer. The protective insulating layer may be divided along with the phosphor sheet in a process of dividing it into individual packages along a chip separation region.

The method may further include forming a second contact layer on the second conductive semiconductor layer, and forming a first insulating layer covering the second contact layer and the sidewalls of the plurality of contact holes, The first conductive layer having openings exposing the first conductive type semiconductor layer in the plurality of contact holes, wherein the first contact layer is formed on the first insulating layer, Forming a second insulating layer having contact portions contacting the conductive semiconductor layer and connecting portions connecting the contact portions and covering the first contact layer; patterning the first and second insulating layers to form the first contact layer, Forming an opening for exposing the second contact layer, forming a first electrode pad on the second insulating layer, the first electrode pad connecting to the first contact layer through the openings, Connect to the floor The may further include forming a second electrode pad. The first bump and the second bump are electrically connected to the first electrode pad and the second electrode pad, respectively.

In some embodiments, forming the first bump and the second bump may include forming an insulating layer pattern having openings exposing the first and second electrode pads, And plating a metal material on the pad and the second electrode pad. Further, during formation of the first bump and the second bump, forming a dummy bump between the first bump and the second bump may be further included.

Forming the first bump and the second bump may include forming through holes in the insulating substrate, filling the through holes with the metal material, and inserting the insulating substrate having the metal material into the first and second bumps, The electrode pad, and the second electrode pad. Further, before bonding the insulating substrate, an insulating layer covering the first electrode pad and the second electrode pad is formed, and the insulating layer is patterned to expose the first electrode pad and the second electrode pad can do.

According to the present invention, a wafer level (or chip level) light emitting diode package that can be modularized into an integrated circuit board without using a conventional lead frame, a printed circuit board, or the like can be provided. Accordingly, a light emitting diode package having high efficiency and high heat dissipation characteristics is provided, and work time and cost required for manufacturing the light emitting diode module can be reduced. Further, by mounting the light emitting diode package, a light emitting diode module having high efficiency and high heat dissipation characteristics can be provided.

1 is a schematic cross-sectional view illustrating a light emitting diode package according to an embodiment of the present invention.
2 is a schematic cross-sectional view illustrating a light emitting diode package according to another embodiment of the present invention.
3 is a cross-sectional view illustrating a light emitting diode module including a light emitting diode package according to an embodiment of the present invention.
4 to 12 are views for explaining a method of manufacturing a light emitting diode package according to an embodiment of the present invention. Figs. 5 to 10A show a plan view, and Fig. 10B shows a cross-sectional view taken along a tear line AA in Fig. 10A.
13 is a cross-sectional view illustrating a method of manufacturing a light emitting diode package according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, and the like of the components may be exaggerated for convenience. Like reference numerals designate like elements throughout the specification.

1 is a cross-sectional view illustrating a light emitting diode package 10 according to an embodiment of the present invention.

1, the light emitting diode package 10 includes a semiconductor laminated structure 30, a first contact layer 35, a second contact layer 31, a first insulating layer 33, a second insulating layer 37, a first electrode pad 39a, a second electrode pad 39b, a first bump 43a, and a second bump 43b. In addition, the light emitting diode package 10 may include an insulating layer 41, a dummy bump 43c, and a wavelength converter 45.

The semiconductor laminated structure 30 includes a first conductive type upper semiconductor layer 25, an active layer 27, and a second conductive type lower semiconductor layer 29. The active layer 27 is interposed between the upper and lower semiconductor layers 25 and 29.

The active layer 27 and the upper and lower semiconductor layers 25 and 29 may be formed of a III-N compound semiconductor, for example, an (Al, Ga, In) N semiconductor. The upper and lower semiconductor layers 25 and 29 may each be a single layer or a multi-layer. For example, the upper or lower semiconductor layer 25, 29 may include a contact layer and a cladding layer, and may also include a superlattice layer. The active layer 27 may be a single quantum well structure or a multiple quantum well structure. Preferably, the first conductivity type is n-type and the second conductivity type is p-type. The upper semiconductor layer 25 can be formed of the n-type semiconductor layer having a relatively small resistance and the upper semiconductor layer 25 can be formed to have a relatively large thickness. Therefore, it is easy to form the rough surface R on the upper surface of the upper semiconductor layer 25, and the rough surface R improves the extraction efficiency of the light generated in the active layer 27.

The semiconductor laminated structure 30 includes a plurality of contact holes (see FIGS. 5 (b) and 5 (b)) for exposing the first conductive type upper semiconductor layer through the second conductive type lower semiconductor layer 29 and the active layer 27, 30a), and the first contact layer 35 is in contact with the first conductive upper semiconductor layer 25 exposed in the plurality of contact holes.

On the other hand, the second contact layer 31 contacts the second conductive type lower semiconductor layer 29. The second contact layer 31 includes a reflective metal layer and reflects the light generated in the active layer 27. In addition, the second contact layer 31 may be in ohmic contact with the second conductive type lower semiconductor layer 29.

The first insulating layer 33 covers the second contact layer 31. In addition, the first insulating layer 33 covers the sidewalls of the semiconductor laminated structure exposed in the plurality of contact holes 30a. Further, the first insulating layer 33 may cover the side surface of the semiconductor laminated structure 30. The first insulating layer 33 isolates the first contact layer 35 from the second contact layer 31 and further includes a second conductive lower semiconductor layer 29 exposed in the plurality of contact holes 30a, And the active layer 27 from the first contact layer 35. The first insulating layer 33 may be formed of a single layer of a silicon oxide film or a silicon nitride film, but is not limited thereto and may be formed of multiple layers. Further, the first insulating layer 33 may be a distributed Bragg reflector in which insulating layers having different refractive indices such as SiO2 / TiO2 or SiO2 / Nb2O5 are repeatedly laminated.

The first contact layer 35 is located below the first insulating layer 33 and penetrates the first insulating layer 33 in the plurality of contact holes 30a to form a first conductive upper semiconductor Layer 25 as shown in FIG. The first contact layer 35 includes contact portions 35a that contact the first conductive upper semiconductor layer 25 and a connection portion 35b that connects the contact portions 35a to each other. Therefore, the contact portions 35a are electrically connected to each other by the connecting portion 35b. The first contact layer 35 is formed under a part of the first insulating layer 33 and may be formed of a reflective metal layer.

The second insulating layer 37 covers the first contact layer 35 under the first contact layer 35. Further, the second insulating layer 37 may cover the side surface of the semiconductor laminated structure 30, covering the first insulating layer 33. The second insulating layer 37 may be formed as a single layer or a multilayer, and may be a distributed Bragg reflector.

The first electrode pad 39a and the second electrode pad 39b are located below the second insulating layer 37. [ The first electrode pad 39a may be connected to the first contact layer 35 through the second insulating layer 37. [ The second electrode pad 39b may be connected to the second contact layer 31 through the second insulating layer 37 and the first insulating layer 33. [

The first bump 43a and the second bump 43b are connected under the first and second electrode pads 39a and 39b, respectively. The first bump 43a and the second bump 43b may be formed by a plating technique. The first and second bumps 43a and 43b are terminals for electrically connecting to a circuit board such as an MC-PCB, and their end surfaces may be arranged on the same plane. Further, the first electrode pad 39a and the second electrode pad 39b may be formed at the same level, so that the first bump 43a and the second bump 43b may also be formed on the same surface. Accordingly, the first and second bumps 43a and 43b can have the same height.

Meanwhile, a dummy bump 43c may be positioned between the first bump 43a and the second bump 43b. The dummy bumps 43c may be formed together while forming the first and second bumps 43a and 43b and the heat generated in the semiconductor laminated structure 30 together with the first and second bumps 43a and 43b Lt; RTI ID = 0.0 > a < / RTI >

The insulating layer 41 may cover the sides of the first bump 43a and the second bump 43b. The insulating layer 41 may also cover the side surface of the dummy bump 43c. Furthermore, the insulating layer 41 fills an area between the first bump 43a, the second bump 43b and the dummy bump 43c to prevent moisture from permeating into the semiconductor laminated structure 30 from the outside. The insulating layer 41 also covers the side surfaces of the first electrode pad 39a and the second electrode pad 39b to protect the first and second electrode pads 39a and 39b from the external environment. The insulating layer 41 may cover the whole of the side surfaces of the first and second bumps 43a and 43b but is not limited thereto and may be formed such that some side surfaces near the end surfaces of the first and second bumps 43a and 43b And cover the other side.

The insulating layer 41 covers the side surfaces of the first electrode pad 39a and the second electrode pad 39b but the present invention is not limited thereto and the first and second electrode pads 39a , 39b, and the insulating layer 41 may be formed under the other insulating layer. In this case, the first and second bumps 43a and 43b can be connected to the first and second electrode pads 39a and 39b through the other insulating layer.

On the other hand, a wavelength converter 45 is disposed on the first conductive upper semiconductor layer 25. The wavelength converter 45 may contact the upper surface of the first conductive upper semiconductor layer 25. The wavelength converter 45 may be a phosphor sheet having a uniform thickness, but is not limited thereto, and may be a substrate doped with impurities for wavelength conversion, for example, sapphire or silicon substrate.

In this embodiment, the side surface of the semiconductor laminated structure 30 is covered with a protective insulating layer. The protective insulating layer may include, for example, the first insulating layer 33 and / or the second insulating layer 37. The first contact layer 35 is covered with the second insulating layer 37 and protected from the external environment and the second contact layer 31 is covered with the first insulating layer 33 and the second insulating layer 37 Can be covered and protected from the external environment. In addition, the first electrode pad 39a and the second electrode pad 39b are also protected by, for example, an insulating layer 41. Thus, deterioration of the semiconductor laminated structure 30 due to moisture or the like from the external environment can be prevented.

Meanwhile, the wavelength converter 45 may be attached on the first conductive upper semiconductor layer 25 at the wafer level, and then may be divided along with the protective insulating layer in the chip separation process. Therefore, the side surface of the wavelength converter 45 may be parallel to the protective insulating layer. The side surface of the wavelength converter 45 may be parallel to the side surface of the insulating layer 41.

2 is a schematic cross-sectional view illustrating a light emitting diode package 20 according to another embodiment of the present invention.

2, the light emitting diode package 20 is substantially the same as the light emitting diode package 10 described above except that the first and second bumps 53a and 53b are formed in the substrate 51 .

That is, the substrate 51 includes through holes, and the first and second bumps 53a and 53b are formed in the through holes, respectively. The substrate 61 may be an insulating substrate, but may be a sapphire substrate or a silicon substrate, but is not limited thereto. The substrate 51 together with the first and second bumps 53a and 53b may be attached to the first electrode pad 39a and the second electrode pad 39b. At this time, in order to prevent the first and second electrode pads 39a and 39b from being exposed to the outside, the insulating layer 49 is formed on the side surfaces and the lower surface of the first and second electrode pads 39a and 39b Can be covered. In addition, the insulating layer 49 may have openings for exposing the first and second electrode pads 39a and 39b, and additional metal layers 55a and 55b may be located in the openings. The additional metal layers 55a and 55b may be a bonding metal.

3 is a cross-sectional view illustrating a light emitting diode module in which light emitting diode packages 10 according to an embodiment of the present invention are mounted on a circuit board.

3, the light emitting diode module includes a circuit board 61, for example, an MC-PCB, a light emitting diode package 10, and a lens 71. The circuit board 61, for example, the MC-PCB, has connection pads 63a and 63b for mounting the light emitting diode package 10. First and second bumps (43a and 43b in Fig. 1) of the LED package 10 are connected to the connection pads 63a and 63b, respectively.

A plurality of light emitting diode packages 10 may be mounted on the circuit board 61 and a lens 71 may be mounted on the light emitting diode packages 100 to adjust optical characteristics such as a directivity angle of the light emitting diode packages 10. [ 10).

In another embodiment, the light emitting diode packages 20 may be mounted instead of the light emitting diode packages 10.

FIGS. 4 to 12 are views for explaining a method of manufacturing the light emitting diode package 10 according to an embodiment of the present invention. Figs. 5 to 10A show a plan view, and Fig. 10B shows a cross-sectional view taken along a perforated line A-A of Fig.

Referring to FIG. 4, a semiconductor laminated structure 30 including a first conductive semiconductor layer 25, an active layer 27, and a second conductive semiconductor layer 29 is formed on a growth substrate 21. The growth substrate 21 may be a sapphire substrate, but is not limited thereto, and may be a different substrate such as a silicon substrate. The first and second conductive semiconductor layers 25 and 29 may be formed as a single layer or a multilayer. In addition, the active layer 27 may be formed of a single quantum well structure or a multiple quantum well structure.

The compound semiconductor layers may be formed of a III-N compound semiconductor and may be grown on a growth substrate 21 by a process such as metal organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE) .

On the other hand, a buffer layer (not shown) may be formed before forming the compound semiconductor layers. The buffer layer is employed to alleviate the lattice mismatch between the sacrificial substrate 21 and the compound semiconductor layers, and may be a layer of a gallium nitride based material such as gallium nitride or aluminum nitride.

5 (a) and 5 (b), the semiconductor package structure 30 is patterned to form a chip (package) isolation region 30b, and the second conductivity type semiconductor layer 29 and the active layer A plurality of contact holes 30a are formed to expose the first conductive type semiconductor layer 25 by patterning the first conductive type semiconductor layer 27. The semiconductor laminated structure 30 may be patterned using a photolithography and etching process.

The chip separating region 30b is an area to be later divided into individual LED packages and the first conductivity type semiconductor layer 25, the active layer 27 and the second conductivity type semiconductor layer 29 The side is exposed. The chip isolation region 30b may be formed to expose the surface of the substrate 21, but the present invention is not limited thereto.

Meanwhile, the plurality of contact holes 30a may be circular, but it is not limited thereto and may have various shapes. The second conductivity type semiconductor layer 29 and the active layer 27 are exposed to the side walls of the plurality of contact holes 30a. The side walls of the contact holes 30a may be inclined as shown in FIG.

6 (a) and 6 (b), a second contact layer 31 is formed on the second conductive type semiconductor layer 29. The second contact layer 31 is formed on the semiconductor laminated structure 30 excluding the plurality of contact holes 30a.

The second contact layer 31 may include a transparent conductive oxide film such as ITO or a reflective metal layer such as silver (Ag) or Al, and may be formed as a single layer or a multilayer. The second contact layer 31 is also formed in ohmic contact with the second conductivity type semiconductor layer 29.

The second contact layer 31 may be formed after forming the plurality of contact holes 30a. However, the second contact layer 31 may be formed before forming the plurality of contact holes 30a.

7A and 7B, a first insulating layer 33 covering the second contact layer 31 is formed. The first insulating layer 33 may cover the side surfaces of the semiconductor laminated structure 30 exposed in the chip isolation region 30b and may cover the side walls of the plurality of contact holes 30a. The first insulating layer 33 has openings 33a for exposing the first conductivity type semiconductor layer 25 in the plurality of contact holes 30a.

The first insulating layer 33 may be formed of a single layer or multiple layers of an insulating material such as a silicon oxide film or a silicon nitride film. Furthermore, the first insulating layer 33 may be formed of a distributed Bragg reflector in which an insulating layer having a different refractive index is repeatedly laminated. For example, the first insulating layer 33 may be formed by repeatedly laminating SiO2 / TiO2 or SiO2 / Nb2O5. Further, by controlling the thickness of each insulating layer forming the first insulating layer 33, a distributed Bragg reflector having a high reflectance over a wide wavelength range of blue light, green light, and red light can be formed.

Referring to FIGS. 8A and 8B, a first contact layer 35 is formed on the first insulating layer 33. The first contact layer 35 includes contact portions 35a that contact the first conductive type semiconductor layer 25 exposed in the contact holes 30a and a connection portion 35b that connects the contact portions 35a to each other do. The first contact layer 35 may be formed of a reflective metal layer, but is not limited thereto.

The first contact layer 35 is formed on a part of the semiconductor multilayer structure 30 and the first insulating layer 33 is exposed in a region other than the region where the first contact layer 35 is formed.

Referring to FIGS. 9A and 9B, a second insulating layer 37 is formed on the first contact layer 35. The second insulating layer 37 may be formed of a single layer or a multilayer such as a silicon oxide layer or a silicon nitride layer, or may be formed of a distributed Bragg reflector in which an insulating layer having a different refractive index is repeatedly laminated.

The second insulating layer 37 may cover the first contact layer 35 and also cover the first insulating layer 33. The second insulating layer 37 may also cover the side surface of the semiconductor laminated structure 30 in the chip separating region 30b.

On the other hand, the second insulating layer 37 has an opening 37a for exposing the first contact layer 35. An opening 37b is formed in the second insulating layer 37 and the first insulating layer 33 to expose the second contact layer 31.

Referring to FIGS. 10A and 10B, first and second electrode pads 39a and 39b are formed on the second insulating layer 37. Referring to FIG. The first electrode pad 39a is connected to the first contact layer 35 through the opening 37a and the second electrode pad 39b is connected to the second contact layer 31 through the opening 37b.

The first electrode pad 39a and the second electrode pad 39b are spaced apart from each other. The first and second electrode pads 39a and 39b may have a relatively large area, for example, 1 / 2 and can have an area of 1/3 or more.

Referring to FIG. 11, an insulating layer 41 is formed on the first and second electrode pads 39a and 39b. The insulating layer 41 covers the first and second electrode pads 39a and 39b and has a groove exposing the upper surface of the electrode pads 39a and 39b. In addition, a groove may be formed to expose the second insulating layer 37 between the first electrode pad 39a and the second electrode pad 39b.

Subsequently, first and second bumps 43a and 43b are formed in the grooves in the insulating layer 41, and a dummy bump 43c may be formed between the first bump and the second bump. As shown, the first and second bumps 43a and 43b respectively fill the grooves in the insulating layer 41, and the first and second bumps 43a and 43b respectively form a part of the surface of the insulating layer 41 And comes into contact with the surface of the insulating layer 41.

The bumps may be formed using plating, such as electroplating. If necessary, a seed layer for plating may be formed.

Meanwhile, after the first and second bumps 43a and 43b are formed, the insulating layer 41 may be removed. For example, the insulating layer 41 may be formed of a polymer such as a photoresist, and may be removed after the bumps are completed. Alternatively, the insulating layer 41 may be left to protect the sides of the first and second bumps 43a and 43b.

Although the insulating layer 41 is directly formed on the first and second electrode pads 39a and 39b in the present embodiment, the first and second electrode pads 39a and 39b ) May be formed. The other insulating layer is formed to have openings exposing the first electrode pad 39a and the second electrode pad 39b. Then, the insulating layer 41 and the bump forming process may be performed.

Referring to FIG. 12, the growth substrate 21 is removed and a wavelength converter 45 is attached to the first conductivity type semiconductor layer 25. The growth substrate 21 can be removed using optical techniques such as laser lift-off (LLO) or mechanical polishing or chemical etching techniques.

Thereafter, a roughened surface can be formed on the surface of the exposed first conductivity type semiconductor layer 25 by anisotropic etching by PEC etching or the like.

On the other hand, a wavelength converter such as a phosphor sheet containing a phosphor can be attached to the first conductivity type semiconductor layer 25.

Alternatively, the growth substrate 21 may contain an impurity for converting the wavelength of light generated in the active layer 27. In this case, the growth substrate 21 may be used as the wavelength converter 45.

Thereafter, the light emitting diode package 10 is completed by dividing it into individual packages along the chip separation region 30b. At this time, the second insulating layer 37 is cut together with the wavelength converter 45, so that the cut surfaces are formed in parallel with each other.

13 is a cross-sectional view illustrating a method for fabricating a light emitting diode package 20 according to another embodiment of the present invention.

13, the method of manufacturing the LED package 20 according to the present embodiment includes the steps of forming the first electrode pad 39a and the second electrode pad 39b using the manufacturing method of the LED package 10 (Figs. 10 (a) and 10 (b)).

After the first and second electrode pads 39a and 39b are formed, an insulating layer 49 is formed to cover the first and second electrode pads 39a and 39b. The insulating layer 49 covers and protects the side surfaces of the first and second electrode pads 39a and 39b. The insulating layer 49 has openings for exposing the first and second electrode pads 39a and 39b. Subsequently, additional metal layers 55a and 55b are formed in the openings. The additional metal layers 55a and 55b may be, for example, a bonding metal.

On the other hand, the substrate 51 is bonded onto the first electrode pad 39a and the second electrode pad 39b. The substrate 51 may have through holes, and first and second bumps 53a and 53b may be formed in the through holes. In addition, pads 57a and 57b may be formed at the ends of the first and second bumps. The substrate 51 having the first and second bumps 53a and 53b and the pads 57a and 57b is separately manufactured and bonded onto the wafer having the first and second electrode pads 39a and 39b .

Thereafter, as described with reference to Fig. 12, the growth substrate 21 may be removed and the wavelength converter 45 may be attached to the first conductivity type semiconductor layer 25, and then divided into individual packages. Thus, the light emitting diode package 20 shown in Fig. 2 is completed.

Claims (10)

A semiconductor multilayer structure including a first conductive upper semiconductor layer, an active layer, and a second conductive bottom semiconductor layer;
A plurality of contact holes through the second conductive lower semiconductor layer and the active layer to expose the first conductive upper semiconductor layer;
A first bump located under the semiconductor laminated structure and electrically connected to the first conductive upper semiconductor layer exposed in the plurality of contact holes;
A second bump located under the semiconductor laminated structure and electrically connected to the second conductive type lower semiconductor layer;
A protective insulating layer covering a side wall of the semiconductor laminated structure; And
A plurality of grooves disposed between the first and second bumps and the semiconductor laminated structure and having a plurality of grooves,
Wherein the first and second bumps are respectively filled with the grooves of the insulating layer and are electrically connected to the first conductive upper semiconductor layer and the second conductive lower semiconductor layer through the grooves of the insulating layer, 1 and the second bumps each cover a bottom surface portion of the insulating layer and contact the lower surface of the insulating layer. The method according to claim 1,
And a wavelength converter disposed on the first conductive upper semiconductor layer. The method of claim 2,
Wherein the wavelength converter is a phosphor sheet or a single crystal substrate doped with impurities. The method of claim 2,
And a side surface of the wavelength converter is parallel to the protective insulating layer. The method according to claim 1,
Wherein the protective insulating layer is a distributed Bragg reflector. The method according to claim 1,
Wherein the first conductive upper semiconductor layer has a roughened surface. delete The method according to claim 1,
And a dummy bump positioned between the first and second bumps. The method according to claim 1,
Further comprising an insulating substrate having through holes,
Wherein the first and second bumps are formed in the through-hole of the insulating substrate. The method of claim 9,
Wherein the insulating substrate is a sapphire or a silicon substrate.

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