KR101630324B1 - Shift register - Google Patents

Abstract

The present invention relates to a shift register for stabilizing at least one reset node and a pull-down switching element provided in each stage of a shift register, thereby preventing deterioration in image quality and improving reliability thereof, In each of the plurality of stages, each of the plurality of stages includes an output pulse from the front stage or a start signal from the outside, an output pulse from the rear stage, and a plurality of charge / First to third node controllers for controlling voltage states of the first and second reset nodes; And an output pulse output section which is controlled in accordance with a voltage state of the set node and first and second reset nodes to output an output pulse, and a second and a third control nodes for controlling voltage states of the first and second reset nodes, Each of the third node controllers alternately uses the second discharging voltage source having a voltage level lower than the voltage level of the first discharging voltage source of the plurality of charge / discharge exclusive voltage sources, And discharging the node.

A shift register, a stage, a set node, first and second reset nodes,

Description

SHIFT REGISTER {SHIFT REGISTER}

The present invention relates to a shift register of an image display apparatus, and more particularly, to stabilizing at least one reset node and a pull-down switching element provided in each stage of a shift register, thereby preventing degradation of image quality and improving reliability thereof To a shift register.

In order to sequentially drive the gate lines of the video display device, a shift register for sequentially supplying scan pulses to the gate lines is required.

The shift register is composed of a plurality of stages for outputting scan pulses, and the output terminals of each stage are connected to the corresponding gate lines on a one-to-one basis. Here, the gate lines are connected to the respective pixels of the display device.

1, each conventional stage includes a node for controlling the charging and discharging states of the set node Q for enabling and the reset node QB for disabling, Up switching element Tru which outputs the output pulse Vout according to the signal state of the set node Q and a discharge voltage source VSS according to the signal state of the reset node QB And a pull-down switching device Trd for outputting the pull-down signal.

The set node Q and the reset node QB of each stage thus configured are alternately charged and discharged. When the set node Q is charged, the reset node QB maintains the discharge state When the reset node QB is charged, the set node Q maintains the discharge state. Here, when the set node Q is in the charged state, the output pulse Vout from the pull-up switching element Tru is output to the corresponding gate line, and when the reset node QB is in the charged state, A discharging voltage source from the element Trd is output to the corresponding gate line.

At this time, the pull-up switching elements Tru provided in each stage are turned on only for a period of at least one horizontal period once per frame to output the output pulse Vout. However, the pull- The discharge voltage Vout must be continuously turned on for the remaining period except for the predetermined horizontal period to supply the discharge voltage source to the corresponding gate line. That is, in the case of the reset node QB, since the pull-down switching device Trd is turned on by being kept charged for the remaining period except for the short period in which the output pulse Vout is outputted, The device Trd is deteriorated at a high temperature, and the threshold voltage thereof is raised. Accordingly, the turn-on timing becomes irregular due to the deterioration of the pull-down switching device Trd and the threshold voltage rise, and the reliability of the image deteriorates along with the quality of the image.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to stabilize at least one reset node and a pull-down switching element provided in each stage of a shift register, A shift register is provided.

According to an aspect of the present invention, there is provided a shift register including a plurality of stages connected in a dependent manner, wherein each of the plurality of stages includes an output pulse from the front stage, First to third node controllers for controlling a voltage state of the set node and the first and second reset nodes according to output pulses from the back stage and the plurality of charge / discharge exclusive voltage sources; And an output pulse output section which is controlled in accordance with a voltage state of the set node and first and second reset nodes to output an output pulse, and a second and a third control nodes for controlling voltage states of the first and second reset nodes, Each of the third node controllers alternately connects the first and second reset nodes to each other using a second discharging voltage source having a voltage level lower than the voltage level of the first discharging voltage source of the plurality of charging- And discharging.

Wherein each of the plurality of stages includes the plurality of charging voltage sources that are converted into the same or different levels for the first and second periods, respectively, set in units of at least one frame, the plurality of charging voltage sources for the first and second periods A second discharging voltage source which is maintained at a voltage level lower than the voltage level of the voltage source, at least one clock pulse among a plurality of clock pulses circulating with a sequential phase difference, And outputs the output signal.

Wherein each of the plurality of stages includes first and second charging voltage sources supplied to maintain a gate high voltage level in the first period, a third charging voltage source supplied to be maintained at a gate low voltage level, A second discharging voltage source supplied to maintain a voltage level lower than the gate low voltage level, and a second discharging voltage source supplied to maintain the gate high voltage level in the second period, 1 and a third charging voltage source, a second charging voltage source supplied to be maintained at the gate low voltage level, a first discharging voltage source supplied to maintain the gate low voltage level, and a second discharging voltage source And a second discharging voltage source supplied to maintain the level of the second discharging voltage.

Wherein the first node control unit is turned on or off according to an output pulse from the front stage or the start signal and is connected to a first node for connecting the supply line of the first charging voltage source and the set node, A second switching element that is turned on or off according to an output pulse from the rear stage and connects the supply line of the first discharging voltage source and the set node when the first discharging voltage source is turned on, A third switching element that turns on or off according to the voltage state of the set node and connects the set node and the supply source of the first discharging voltage source when turned on, And a fourth switching element that is turned on or off according to the state and connects the set node and the supply source of the first discharging voltage source when turned on .

Wherein the second node control unit sets the voltage state of the first reset node according to the output pulse from the front stage and the second and third charging voltage sources to the second charging voltage source and the first discharging voltage source And the second discharging voltage source is controlled by the second discharging voltage source.

The second node control unit is turned on or off according to a voltage level from a line to which the second charging voltage source is supplied and is turned on when the supply line of the second charging voltage source and the first reset node And a second reset node connected between the supply line of the first discharging voltage source and the first reset node in a turn-on state, the fifth switching element being turned on or off according to a voltage state of the set node, A sixth switching element which is turned on or off according to an output pulse from the front stage and connects between the supply line of the first discharging voltage source and the first reset node at the time of turn- And an eighth switching element that is turned on or off according to a voltage level of the third charging voltage source and connects the second charging voltage source supply line and the first reset node when the first charging voltage source is turned on .

Wherein the third node control unit changes the voltage state of the second reset node according to the output pulse from the front stage and the second charging voltage source and the third charging voltage source to the third charging voltage source and the first charging voltage source And is controlled by the discharge voltage source or the second discharge voltage source.

The third node control unit is turned on or off according to the voltage state of the third charging voltage source, and when the third node control unit turns on, A tenth switching element that is turned on or off according to a voltage state of the set node and connects between the second reset node and the first discharging voltage source supply line when turned on, And an eleventh switching element for connecting the second reset node and the supply source of the first discharging voltage source when turned on and an eleventh switching element for turning on the second discharging voltage source And a twelfth switching element that turns on or off according to the voltage state and connects the second reset node and the supply source of the second discharging voltage source at the time of turn-on.

Up switching element which is controlled in accordance with a voltage state of the set node and outputs an output pulse, the gate-low voltage according to the first discharging voltage source controlled by the voltage state of the first reset node, And a second full-down switching element controlled by the voltage state of the second reset node and outputting a gate-low voltage according to the first discharging voltage source .

The shift register according to the present invention having the above-described characteristics is characterized in that the shift register is provided with a first discharge voltage for each of the reset nodes and the pull-down switching elements alternately driven for at least one frame period, And supplies a second discharge voltage at a low voltage level. Accordingly, the present invention prevents deterioration of each reset node and the pull-down switching elements and further stabilizes the threshold voltage, thereby preventing the display failure of the image and improving the reliability thereof.

Hereinafter, a shift register according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a shift register according to an embodiment of the present invention.

The shift register shown in Fig. 2 is composed of n stages ST1 to STn and one dummy stage STn + 1 which are connected to each other in dependence. Here, each of the stages ST1 to STn outputs one output pulse Vout1 to Voutn + 1 during one frame period, and sequentially outputs the output pulse Vout1 to Voutn + 1 from the first stage ST1 to the dummy stage STn + (Vout1 to Voutn).

The output pulses Vout1 to Voutn output from the stages ST1 to STn except the dummy stage STn + 1 are sequentially supplied to gate lines of a display panel (not shown) for displaying an image, The gate lines of the display panel are sequentially scanned. More specifically, when the first stage ST1 outputs the first output pulse Vout1, the second stage ST2 then outputs the second output pulse Vout2, and then the third stage ST3 3 output pulse Vout3, .... Finally, the n-th stage STn outputs the n-th output pulse Voutn. On the other hand, after the n-th stage STn outputs the n-th output pulse Voutn, the dummy stage STn + 1 outputs the (n + 1) -th output pulse Voutn + (N + 1) -th output pulse Voutn + 1 output from the n-th stage STn is supplied only to the n-th stage STn without being supplied to the gate line.

As described above, each of the stages ST1 to STn + 1 drives the gate line connected thereto by using the output pulses Vout1 to Voutn + 1, and using the output pulses Vout1 to Voutn + 1 And controls the operation of the stage located at the rear stage from itself and the stage located at the front stage from the stage itself. Specifically, the k-th output pulse Voutk from the k-th stage STk (where k is any natural number) is supplied to the k-th gate line, and the k-th output pulse Voutk from the k-th stage STk is Th stage STk-1 and the (k + 1) th stage STk + 1. The k + 1 stage STk + 1 is set by the kth output pulse Voutk, and the kth stage STk-1 is reset by the kth output pulse Voutk. On the other hand, the k-th output pulse Voutk from the k-th stage STk is supplied to the k-th gate line and supplied to the k-2 stage STk-2 and the (k + 2) . In this case, the (k + 2) th stage STk + 2 is set by the kth output pulse Voutk, and the (k-2) th stage STk-2 is reset by the kth output pulse Voutk. The shift register of the present invention can be embedded in a non-display area of the display panel.

FIG. 3 is a waveform diagram showing a plurality of driving signals supplied to the shift register of FIG. 2. FIG.

Referring to FIG. 3, each stage ST1 to STn + 1 of the shift register is converted into the same or different level for a predetermined period, for example, a first period and a second period, A plurality of discharging voltage sources (VDD1, VDD2, VDD3), a plurality of discharging voltage sources (VSS1, VSS2) that are converted into the same or different levels in units of the first period and the second period, At least one clock pulse among a plurality of clock pulses CLK1 to CLK4 having a phase difference and circulating is applied. The number of the plurality of clock pulses CLK1 to CLK4 supplied to each of the stages ST1 to STn + 1 may vary depending on the circuit configuration of each of the stages ST1 to STn + 1.

The first stage ST1 located at the uppermost one of the stages ST1 to STn + 1 is connected to a plurality of charging voltage sources VDD1, VDD2 and VDD3 which are converted to the same or different levels, A start pulse Vst is further supplied together with at least one clock pulse of the plurality of discharge voltage sources VSS1 and VSS2 and the plurality of clock pulses CLK1 to CLK4. The remaining stages ST2 to STn + 1 except for the first stage ST1 receive the remaining signals except for the start pulse Vst, that is, a plurality of charging voltage sources VDD1, VDD2, and VDD3, (VSS1, VSS2) and at least one of the plurality of clock pulses (CLK1 to CLK4). Here, the remaining stages ST2 to STn + 1 except for the first stage ST1 are used to reset all the stages ST2 to STn + 1, for example, by using the start pulse Vst And further receives the start pulse Vst.

The plurality of charging voltage sources VDD1, VDD2 and VDD3 are separately supplied to a first charging voltage source VDD1, a second charging voltage source VDD2 and a third charging voltage source VDD3, Each of the third charging voltage sources VDD1, VDD2 and VDD3 is supplied so as to be converted into a voltage level of either a gate high voltage level or a gate low voltage level in units of the first period and the second period. Here, the gate high voltage level is set to a level capable of charging at least one set and a reset node provided in each of the stages ST1 to STn + 1, that is, a set and a reset of each stage ST1 to STn + And is set to a level capable of turning on the switching elements connected to the node.

The plurality of discharging voltage sources VSS1 and VSS2 are separately supplied to the first discharging voltage source VSS1 and the second discharging voltage source VSS2 and the first and second discharging voltage sources VSS1 and VSS2 Are preset and supplied with voltage levels of different sizes. Specifically, the first discharging voltage source VSS1 may be maintained at a gate low voltage level. In the case of the second discharging voltage source VSS2, the first discharging voltage source VSS1 may be maintained at a lower voltage level than the first discharging voltage source VSS1. do. The first discharging voltage source VSS1 discharges at least one set and a reset node included in each of the stages ST1 to STn + 1, Off < / RTI > In the case of the second discharging voltage source VSS2, the voltage is set to the gate-low voltage level, that is, the voltage level lower than the first discharging voltage source VSS1. More specifically, for example, the voltage level of the first discharging voltage source VSS1 may be a ground voltage level (e.g., a ground voltage of 0V) or a negative voltage level (for example, In which case the voltage level of the second discharging voltage source VSS2 may be set to a negative voltage level (for example, -5V to -8V) lower than the gate low voltage level have.

Meanwhile, the plurality of clock pulses CLK1 to CLK4, for example, the first to fourth clock pulses CLK1 to CLK4 may be periodically generated to have an amplitude of a gate low voltage level and a gate high voltage level. Each of these clock pulses CLK1 to CLK4 has the same pulse width and the same duty ratio. On the other hand, the first to fourth clock pulses CLK1 to CLK4 may be supplied to the shift register so as to be generated so as to simultaneously maintain an active state (high period) for a predetermined period between clock pulses generated adjacent to each other.

The plurality of clock pulses CLK1 to CLK4 are output sequentially in phase with each other. The second clock pulse CLK2 is delayed by one pulse width from the first clock pulse CLK1 and the third clock pulse CLK3 is delayed by one pulse width from the second clock pulse CLK2, The fourth clock pulse CLK4 is delayed by one pulse width from the third clock pulse CLK3 and the first clock pulse CLK1 is one pulse width longer than the fourth clock pulse CLK4, And the phase is delayed by a predetermined amount. Here, the fourth clock pulse CLK4 and the start pulse Vst may be output in synchronization with each other. As such, when the fourth clock pulse CLK4 and the start pulse Vst are synchronized with each other, the fourth clock pulse CLK4 among the first through fourth clock pulses CLK4 is output first.

Each of the clock pulses CLK1 to CLK4 is a signal used to generate an output pulse of each stage and each of the stages ST0 to STn + 1 uses either one of these clock pulses CLK1 to CLK4 And generates output pulses Vout1 to Voutn. For example, the 4k + 1 < th > stage of the n stages outputs the 4k + 1 < th > output pulses using the first clock pulse CLK1 and the 4k + The 4k + 3 < th > stage outputs a 4k + 3 < th > output pulse using the third clock pulse CLK3, and the 4 < And outputs 4k + 4th output pulses using the clock signal CLK4. In the example of FIG. 3, four kinds of clock pulses having different phase differences are used. However, any number of clock pulses can be used as long as two or more clock pulses having different phase differences are used.

Referring to the input waveform diagram of FIG. 3, the voltage level changes of the input signals in the first and second periods, which are set in units of at least one frame, are as follows.

The first and second clock pulses CLK1 to CLK4 are alternately applied to the first and second clock pulses CLK1 to CLK3, CLK4 are periodically supplied with an amplitude of the gate low voltage level and the gate high voltage level, and the first charging voltage source VDD1 and the second charging voltage source VDD2 are supplied to maintain the gate high voltage level. The third charging voltage source VDD3 is supplied so as to maintain the voltage level of the opposite polarity to the second charging voltage source VDD2, that is, the gate-low voltage level in the first period. At this time, the first discharging voltage source VSS1 is supplied to maintain the gate low voltage level, and the second discharging voltage source VSS2 is supplied with a voltage level lower than the gate low voltage level of the first discharging voltage source VSS1 .

On the other hand, the first to fourth clock pulses CLK1 to CLK4 in the second period are periodically supplied with the amplitude of the gate low voltage level and the gate high voltage level in the same manner as the first period, and the first charging voltage source VDD1 and the third charging voltage source VDD3 are supplied to maintain the gate high voltage level. On the other hand, the second charging voltage source VDD2 is supplied in the second period to maintain the voltage level of the opposite polarity to the third charging voltage source VDD3, that is, the gate-low voltage level. The first discharging voltage source VSS1 is supplied to maintain a gate low voltage level and the second discharging voltage source VSS2 is supplied with a voltage level lower than the gate low voltage level of the first discharging voltage source VSS1 .

Next, the configuration of each stage ST1 to STn + 1 provided in the shift register of the present invention supplied with the signals as described above will be described.

4 is a diagram showing a circuit configuration of the second stage shown in Fig.

The second stage ST2 shown in Fig. 4 includes the output pulse Vout1 from the first stage or the start signal Vst from the outside, the output pulse Vout3 from the third stage which is the stage at the succeeding stage, And first and second reset nodes QB1 and QB2 according to a plurality of charge-up only voltage sources VDD1 to VDD3, VSS1 and VSS2 supplied from the outside, A third node control unit; And an output pulse output section which is controlled in accordance with the voltage state of the set node and the first and second reset nodes to output an output pulse.

Here, each of the second and third node controllers for controlling the voltage states of the first and second reset nodes QB1 and QB2 is connected to a second node of the voltage level lower than the voltage level of the first discharging voltage source VSS1 The first and second reset nodes are alternately discharged by using the dedicated voltage source VSS2.

The first node control unit receives the output pulse from the front stage, that is, the output pulse Vout1 or the start signal Vst from the first stage ST1, the output pulse from the rear stage, that is, the output from the third stage ST3 The voltage of the set node Q is set to the first charging or first discharging voltage source VDD1 or VSS1 according to the pulse Vout3, the first charging voltage source VDD1 and the first discharging voltage source VSS1, ). ≪ / RTI > To this end, the first node control unit includes first through fourth switching elements Tr1 through Tr4.

The first switching element Tr1 of the first node control unit is turned on or off according to the output pulse Vout1 from the first stage ST1 which is the previous stage and is turned on when the first charging voltage source VDD1 is turned on, And the set node (Q). Here, an output pulse Vout1 from the previous stage or a start signal Vst supplied from the outside is supplied to the drain terminal (or source terminal) of the first switching device Tr1 instead of the first charging voltage source VDD It is possible.

The second switching element Tr2 is turned on or off according to the output pulse Vout3 from the third stage ST3 in the subsequent stage and is turned on when the supply line of the first discharging voltage source VSS1 is turned on, (Q).

The third switching element Tr3 is turned on or off according to the voltage state of the first reset node QB1 and is supplied with the supply of the set node Q and the first discharging voltage source VSS1 at the turn- Connects humans.

The fourth switching element Tr4 is turned on or off according to the voltage state of the second reset node QB2 and is turned off when the set node Q and the first discharging voltage source VSS1 are turned on Connects humans.

The second node control unit controls the output voltage of the first stage ST1 according to the output pulse Vout1 from the first stage ST1 and the second charging voltage source VDD2 and the third charging voltage source VDD3, The voltage state of the set node QB1 is controlled by the second charging voltage source VDD2 and the first discharging voltage source VSS1 or the second discharging voltage source VSS2. To this end, the second node control section includes the fifth to eighth switching elements Tr5 to Tr8.

The fifth switching device Tr5 of the second node control unit is turned on or off according to the voltage level from the line to which the second charging voltage source VDD2 is supplied and is turned on when the second charging voltage source VDD2 And the first reset node QB1.

The sixth switching element Tr6 is turned on or off according to the voltage state of the set node Q and is turned on when the supply line of the first discharging voltage source VSS1 and the first reset node QB1 are turned on, Connect the liver.

The seventh switching device Tr7 is turned on or off according to the output pulse Vout1 from the front stage ST1 and is turned on when the supply line of the first discharging voltage source VSS1 and the first resetting voltage source And connects the nodes QB1.

The eighth switching element Tr8 is turned on or off according to the third charging voltage source VDD3 from the third charging voltage source VDD3 supply line and turned on when the second discharging voltage source VSS2 is turned on, And connects the supply line and the first reset node QB1.

The third node control unit controls the output voltage Vout1 of the first stage ST1 in accordance with the output pulse Vout1 from the first stage ST1 and the second charging voltage source VDD2 and the third charging voltage source VDD3, The voltage state of the set node QB2 is controlled by the third charging voltage source VDD3 and the first discharging voltage source VSS1 or the second discharging voltage source VSS2. To this end, the third node control section includes ninth to twelfth switching elements Tr9 to Tr12.

The ninth switching element Tr9 of the third node control unit is turned on or off according to the voltage state of the third charging voltage source VDD3 and is turned on when the third charging voltage source VDD3 is turned on, And the second reset node QB2.

The tenth switching element Tr10 is turned on or turned off according to the voltage state of the set node Q and the second reset node QB2 and the first discharging voltage source VSS1 are turned on, .

The eleventh switching element Tr11 is turned on or off according to the output pulse Vout2 from the front stage ST2 and is turned on when the second reset node QB2 and the first discharging power source VSS1) to connect the human.

The twelfth switching element Tr12 is turned on or off according to the voltage state of the second charging voltage source VDD2 and turned on when the second reset node QB2 and the second discharging power source VSS2 ) Supply the human to connect.

The output pulse output section is controlled in accordance with the voltage state of the first reset node QB1 by a pull-up switching element Tru controlled by the voltage state of the set node Q to output a second output pulse Vout2 A first pull-down switching device Trd1 for outputting a gate low voltage according to the first discharging voltage source VSS1, a first full-down switching device Trd2 for controlling a voltage of the first discharging voltage source VSS1, which is controlled in accordance with the voltage state of the second reset node QB2, And a second pull-down switching device Trd2 for outputting a gate-low voltage according to the second pull-down switching device Trd2.

The pull-up switching element Tru is turned on or off according to the voltage of the set node Q. The pull-up switching element Tru is connected to the output pulse output terminal of one of the clock transmission lines on turn- For example, the second clock pulse CLK2 to the second output pulse Vout2.

The first pull-down switching element Trd1 is turned on or off according to the voltage of the first reset node QB1 and the output terminal of the output pulse at the turn-on time is connected to the first discharging voltage source VSS1 Electrical connection.

The second pull-down switching element Trd2 is turned on or off according to the voltage of the second reset node QB2. The output terminal of the output pulse at the turn-on time is connected to the first discharging voltage source VSS1 Electrical connection.

In each of the stages ST1 to STn + 1 configured and operated as described above, the gate high voltage level is maintained together with the first to fourth clock pulses CLK1 to CLK4 in the first period of the display period of the image The third charging voltage source VDD3 supplies the first charging voltage source VDD1 and the second charging voltage source VDD2 while the third charging voltage source VDD3 supplies the first charging voltage source VDD1 and the second charging voltage source VDD2, To a low voltage level. At this time, a second discharging voltage source VSS2 having a voltage level lower than the voltage levels of the first discharging voltage source VSS1 and the first discharging voltage source VSS1 is supplied to the second and third node control units, respectively. Accordingly, in the first period, the second node control unit is controlled by the first and second charging voltage sources VDD1 and VDD2 and the first discharging voltage source VSS1, So that a gate-low voltage corresponding to the dedicated voltage source VSS1 is supplied to the corresponding gate line. Since the third node controller of the first period operated in this manner is discharged by the second discharging voltage source VSS2 of the voltage level lower than the voltage level of the first discharging voltage source VSS1, The threshold voltage of the pull-down switching device Trd2 is lowered by the second discharging voltage source VSS2.

Thereafter, in the second period of the display period of the image, the first charging voltage source VDD1 and the third charging voltage source VDD3 are controlled so as to maintain the gate high voltage level together with the first to fourth clock pulses CLK1 to CLK4, And the second charging voltage source VDD2 is supplied to the gate low voltage level so as to maintain the voltage level of the polarity opposite to that of the third charging voltage source VDD3. At this time, as in the first period, the second discharging voltage source VSS2 having a voltage level lower than the voltage levels of the first discharging voltage source VSS1 and the first discharging voltage source VSS1 is applied to the second and third node control units Supply. Accordingly, in the second period, the third node control unit is controlled by the first and third charging voltage sources VDD1 and VDD3 and the first discharging voltage source VSS1, So that a gate-low voltage corresponding to the dedicated voltage source VSS1 is supplied to the corresponding gate line. Since the second node controller in the second period operated in this manner is discharged by the second discharging voltage source VSS2 having a voltage level lower than the voltage level of the first discharging voltage source VSS1, The threshold voltage of the pull-down switching device Trd1 is lowered by the second discharging voltage source VSS2.

Accordingly, the shift register according to the embodiment of the present invention includes first and second reset nodes QB1 and QB2 that are alternately driven in units of first and second periods, first and second pull- A second discharge voltage VSS2 having a voltage level lower than the first discharge voltage VSS1 in units of the first and second periods is supplied to each of the discharge cells Trd1 and Trd2. Accordingly, the present invention prevents deterioration of each of the reset nodes QB1 and QB2 and the pull-down switching elements Trd1 and Trd2 and further stabilizes the threshold voltage, thereby preventing the display failure of the image, Can be improved.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

1 is a view showing a stage of a shift register according to the related art.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register.

Fig. 3 is a waveform diagram showing a plurality of driving signals supplied to the shift register of Fig. 2; Fig.

4 is a circuit diagram showing a circuit configuration of the second stage shown in Fig.

BRIEF DESCRIPTION OF THE DRAWINGS FIG.

Tr: switching element ST2: second stage

Vout2: second output pulse VDD1: first charging voltage source

VSS1: first discharging voltage source Q: set node for enabling

Tru: Full-up switching device Trd1: First pull-down switching device

Vout1: first output pulse CLK: clock pulse

Claims (9)

A shift register comprising a plurality of stages connected in a dependent manner, Wherein each of the plurality of stages includes: A first node controller for charging the set node using the first charging voltage source in response to an output pulse from the front stage and discharging the set node using the first discharging voltage source in response to an output pulse from the rear stage, , In the first frame period, the first reset node is discharged using the first discharging voltage source in response to the output pulse from the front stage, and the first reset node is charged using the second charging voltage source Discharging the first reset node by using a second discharging voltage source having a voltage level lower than the voltage level of the first discharging voltage source in response to the voltage from the third charging voltage source during the second frame period 2 node control unit, In the second frame period, the second reset node is discharged using the first discharging voltage source in response to the output pulse from the front stage, and the second reset node is charged using the third charging voltage source A third node control unit for discharging the second reset node in response to a voltage from the second charging voltage source in the first frame period using the second discharging voltage source, And an output pulse output section which is controlled according to a voltage state of the set node and the first and second reset nodes to output an output pulse, And each of the second and third node control units alternately discharges the first and second reset nodes in units of one frame period by using the second discharging voltage source. delete The method according to claim 1, Wherein each of the plurality of stages A first and a second charging voltage source supplied to maintain a gate high voltage level, A third charging voltage source supplied to be maintained at the gate low voltage level, A first discharging voltage source supplied to maintain the gate low voltage level, and A second discharging voltage source supplied to maintain a voltage level lower than the gate low voltage level, In the second period A first and a third charging voltage source supplied to maintain the gate high voltage level, A second charging voltage source supplied to be maintained at the gate low voltage level, A first discharging voltage source supplied to maintain the gate low voltage level, and And a second discharging voltage source supplied to maintain a voltage level lower than the gate-low voltage level. The method of claim 3, The first node control unit A first switching element that turns on or off according to an output pulse from the front stage and connects the supply line of the first charging voltage source and the set node when the first charging voltage source is turned on, A second switching element that is turned on or off according to an output pulse from the rear stage and connects the supply line of the first discharging voltage source and the set node when the first discharging voltage source is turned on, A third switching element that is turned on or off according to the voltage state of the first reset node and connects the set node to the supply source of the first discharging voltage source when turned on, And a fourth switching element that is turned on or off according to a voltage state of the second reset node and connects the set node and the supply source of the first discharging voltage source when turned on. 5. The method of claim 4, The second node controller And a second charging voltage source, a second discharging voltage source, and a second discharging voltage source, wherein the voltage state of the first reset node according to the output pulse from the front stage and the second and third charging voltage sources, . 6. The method of claim 5, The second node controller On or off according to the voltage level from the line to which the second charging voltage source is supplied and is connected to the supply line of the second charging voltage source and the first reset node at turn- Switching elements, A sixth switching element that is turned on or off according to a voltage state of the set node and connects the supply line of the first discharging voltage source and the first reset node when the first discharging voltage source is turned on, A seventh switching element that is turned on or off according to an output pulse from the front stage and connects between the supply line of the first discharging voltage source and the first reset node at the time of turn- And an eighth switching element that is turned on or off according to a voltage level of the third charging voltage source and connects the second charging voltage source supply line and the first reset node when the first charging voltage source is turned on, register. The method according to claim 6, The third node control unit The voltage state of the second reset node in accordance with the output pulse from the front stage and the second charging voltage source and the third charging voltage source is set to the third charging voltage source and the first discharging voltage source, A shift register controlled by a second discharging voltage source. 8. The method of claim 7, The third node control unit A ninth switching element that is turned on or off according to a voltage state of the third charging voltage source and connects between the third charging voltage source line and the second reset node when turned on, A tenth switching element that is turned on or off according to the voltage state of the set node and connects the second reset node and the first discharging voltage source supply source when the first switching element is turned on, An 11th switching element that turns on or off according to an output pulse from the front stage and connects the second reset node and the supply source of the first discharging voltage source when turned on, And a twelfth switching element that is turned on or off according to the voltage state of the second charging voltage source and connects the second reset node and the supply source of the second discharging voltage source when the first charging voltage source is turned on Shift register. 9. The method of claim 8, The output pulse output section A pull-up switching element controlled according to a voltage state of the set node to output an output pulse, A first pull-down switching element controlled according to a voltage state of the first reset node to output a gate low voltage according to the first discharging voltage source, And a second pull-down switching element controlled according to a voltage state of the second reset node to output a gate low voltage according to the first discharging voltage source.

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