KR101626362B1 - Method of fabricating substrate for thin film transistor - Google Patents

Abstract

A method of manufacturing a thin film transistor substrate according to the present invention is a bottom gate structure thin film transistor using polycrystalline silicon as an active layer of a thin film transistor and adopts an etch stopper structure, And the back channel is not exposed using the gate structure, thereby securing the reliability of the device. In addition, the etch stopper, the active layer, and the pad contact hole are formed by a single mask process, thereby reducing the number of masks and simplifying the manufacturing process.

Polycrystalline silicon, bottom gate, etch stopper, active layer, pad portion contact hole

Description

TECHNICAL FIELD [0001] The present invention relates to a method of fabricating a thin film transistor substrate,

The present invention relates to a method of manufacturing a thin film transistor substrate, and more particularly, to a method of manufacturing a thin film transistor substrate having a bottom gate structure using polycrystalline silicon as an active layer of a thin film transistor.

Recently, interest in information display has increased, and a demand for using portable information media has increased, and a light-weight flat panel display (FPD) that replaces a cathode ray tube (CRT) And research and commercialization are being carried out. Particularly, among such flat panel display devices, a liquid crystal display (LCD) is an apparatus for displaying an image using the optical anisotropy of a liquid crystal, and is excellent in resolution, color display and picture quality and is actively applied to a notebook or a desktop monitor have.

The liquid crystal display comprises a color filter substrate, a thin film transistor substrate, and a liquid crystal layer formed between the color filter substrate and the thin film transistor substrate.

An active matrix (AM) method, which is a driving method mainly used in the liquid crystal display, is a method of driving a liquid crystal of a pixel portion by using an amorphous silicon thin film transistor (a-Si TFT) to be.

Hereinafter, the structure of a typical liquid crystal display device will be described in detail with reference to FIG.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

As shown in the figure, the liquid crystal display comprises a color filter substrate 5 and a thin film transistor substrate 10, and a liquid crystal layer (not shown) formed between the color filter substrate 5 and the thin film transistor substrate 10, ) ≪ / RTI >

The color filter substrate 5 includes a color filter C composed of a plurality of sub-color filters 7 implementing colors of red (R), green (G) and blue (B) A black matrix 6 for separating the sub-color filters 7 from each other and shielding light transmitted through the liquid crystal layer 30 and a transparent common electrode for applying a voltage to the liquid crystal layer 30 8).

The thin film transistor substrate 10 includes a plurality of gate lines 16 and data lines 17 arranged vertically and horizontally to define a plurality of pixel regions P and a plurality of gate lines 16 and data lines 17, A thin film transistor T which is a switching element formed in a crossing region of the pixel region P and a pixel electrode 18 formed on the pixel region P. [

The color filter substrate 5 and the thin film transistor substrate 10 are bonded together to face each other by a sealant (not shown) formed on the outer periphery of the image display region to constitute a liquid crystal display panel, 5 and the thin film transistor substrate 10 are bonded to each other through a joint key (not shown) formed on the color filter substrate 5 or the thin film transistor substrate 10.

Since the hydrogenated amorphous silicon used in the amorphous silicon thin film transistor is disordered in its atomic arrangement, there is a weak bond (week Si-Si bond) and a dangling bond, Therefore, stability is a serious problem when it is used as a thin film transistor device, and a low charge transfer path is limited to use as a driving circuit.

Therefore, the crystallization technique is applied in order to secure a fast response speed and stability by increasing the charge mobility.

2 is a cross-sectional view schematically showing the structure of a general polycrystalline silicon thin film transistor.

As shown in the figure, a typical polycrystalline silicon thin film transistor includes a buffer layer 11 and an active layer 24 formed on a predetermined substrate 10 in an upper gate structure, an active layer 24, A gate electrode 21 formed on the first insulating layer 15a, a second insulating layer 15b formed on the gate electrode 21, a source / drain region 15b of the active layer 24, The source and drain electrodes 22 and 23 electrically connected to the source electrodes 24a and 24b and the third insulating film 15c formed on the source and drain electrodes 22 and 23 and the drain electrode 23, And a pixel electrode 18.

Reference numeral 24c denotes a channel region of the active layer 24 forming a conductive channel between the source electrode 22 and the drain electrode 23. The active layer 24 is formed of a polycrystalline silicon Thin film.

Hereinafter, a manufacturing process of the polycrystalline silicon thin film transistor having such a structure will be described in detail with reference to the drawings.

3A to 3F are cross-sectional views sequentially illustrating a manufacturing process of the thin film transistor shown in FIG. 2, illustrating a process of manufacturing a thin film transistor of a pixel portion in which an n-channel thin film transistor is formed

As shown in FIG. 3A, a buffer layer 11 and an amorphous silicon thin film are formed on a substrate 10 made of a transparent insulating material such as glass, and then the amorphous silicon thin film is crystallized to form a polycrystalline silicon thin film. Thereafter, the polycrystalline silicon thin film is patterned using a photolithography process (first mask process) to form the active layer 24 made of the polycrystalline silicon thin film.

3B, a first insulating layer 15a and a first conductive layer are sequentially formed on the entire surface of the substrate 10, and then the first conductive layer 15a and the first conductive layer are sequentially patterned using a photolithography process (second mask process) A gate electrode 21 made of the first conductive film is formed on the active layer 24 by selectively patterning the film.

Then, high concentration n + ions are implanted into a predetermined region of the active layer 24 using the gate electrode 21 as a mask to form an n + source region 24a and a drain region 24b. Here, reference numeral 24c denotes a channel region forming a conduction channel between the source region 24a and the drain region 24b.

Next, as shown in FIG. 3C, a second insulating film 15b is deposited on the entire surface of the substrate 10, and then the first insulating film 15a and the second insulating film 15b are formed through a photolithography process (a third mask process) A first contact hole 40a exposing a part of the source region 24a and a second contact hole 40b exposing a part of the drain region 24b are formed by removing a part of the insulating film 15b .

3D, the second conductive film is formed on the entire surface of the substrate 10, and then patterned using a photolithography process (fourth mask process) to form the source region 40a through the first contact hole 40a, A source electrode 22 electrically connected to the drain region 24a is formed and a drain electrode 23 electrically connected to the drain region 24b is formed through the second contact hole 40b.

3E, a third insulating film 15c is deposited on the entire surface of the substrate 10, and then the third insulating film 15c is patterned using a photolithography process (fifth mask process) A third contact hole 40c exposing a part of the drain electrode 23 is formed.

3F, a third conductive film is formed on the entire surface of the substrate 10 on which the third insulating film 15c is formed, and then the third conductive film is formed using a photolithography process (sixth mask process) A pixel electrode 18 electrically connected to the drain electrode 23 is formed through the third contact hole 40c.

In order to manufacture the thin film transistor substrate including the polycrystalline silicon thin film transistor, at least 6 to 7 mask processes are required. In the mask process, a pattern drawn on the mask is transferred onto the substrate on which the thin film is deposited to form a desired pattern The process consists of a number of processes, such as coating of photoresist, exposure, and development, and many masking processes reduce production yield. In particular, the mask designed to form the pattern is very expensive, so that as the number of masks applied to the process increases, the manufacturing cost of the thin film transistor substrate rises accordingly.

In addition, since the polycrystalline silicon thin film transistor is generally formed with a top gate structure, a new investment is required because a manufacturing line of a conventional amorphous silicon thin film transistor having a bottom gate structure can not be used, and a doping and laser crystallization process is further required It is disadvantageous in terms of size and cost.

It is an object of the present invention to provide a method of manufacturing a TFT having a bottom gate structure using polycrystalline silicon as an active layer of a thin film transistor.

Another object of the present invention is to provide a semiconductor device which adopts an etch stop structure and at the same time ensures that the back channel is not exposed by using the bottom gate structure to secure the reliability of the device, And a thin film transistor is manufactured by a total of four mask processes.

Other objects and features of the present invention will be described in the following description of the invention and claims.

According to another aspect of the present invention, there is provided a method of manufacturing a thin film transistor substrate including forming a gate electrode and a gate line in a pixel portion through a first mask process, forming a gate pad line and a data pad Thereby forming a pad line.
In addition, an active layer made of polycrystalline silicon is formed on the gate electrode through a second mask process, an etch stopper made of an insulating film is formed on the active layer, a first contact hole exposing a part of the data pad line, And a second contact hole and a third contact hole exposing a part of the gate pad line and another part of the data pad line are formed. At this time, the second mask process may use a multiple exposure mask, or a half-tone mask and an additional ashing process.
In addition, a source / drain region of n + amorphous silicon is formed on the active layer through a third mask process and a source / drain electrode is formed on the active layer, and electrically connected to a portion of the data pad line through the first contact hole Thereby forming a data line to be connected.
Then, a pixel electrode electrically connected to the drain electrode is formed through a fourth mask process.

As described above, the method of manufacturing a thin film transistor substrate according to the present invention provides an effect that can be used in a high charge moving driving circuit by using polycrystalline silicon as an active layer of a thin film transistor.

In addition, the manufacturing method of the thin film transistor substrate according to the present invention adopts the etch stop structure and protects the back channel region by using the lower gate structure, thereby improving the reliability of the device and improving the process uniformity in the large area substrate And provides an effect that can be achieved.

The method of manufacturing a thin film transistor substrate according to the present invention is characterized in that the etch stopper, the active layer and the pad portion contact holes are formed by a single mask process, thereby reducing the number of masks used in manufacturing the thin film transistor, Saving effect.

As described above, according to the method of manufacturing a thin film transistor substrate according to the present invention, the number of masks is reduced by applying a bottom gate structure, and a subsequent process is performed in a state in which a back channel region is not exposed, thereby securing reliability and securing cost competitiveness do.

Hereinafter, preferred embodiments of a method of manufacturing a thin film transistor substrate according to the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view schematically showing a part of a thin film transistor substrate according to an embodiment of the present invention, and schematically shows a substrate structure of a polycrystalline silicon thin film transistor using polycrystalline silicon as an active layer.

5 is a cross-sectional view schematically showing a part of a thin film transistor substrate according to an embodiment of the present invention. The thin film transistor substrate shown in FIG. 4 has a cross section along line A-A 'and line BB and a cross section For example.

4 and 5 illustrate one pixel including a gate pad portion, a data pad portion, and a thin film transistor of the pixel portion. 5 illustrates a portion of a link portion to which a data line and a data pad line are connected.

As shown in the figure, a thin film transistor substrate 110 according to an embodiment of the present invention includes gate lines 116 and data lines 117 arranged vertically and horizontally on the substrate 110 to define pixel regions, . A polycrystalline silicon thin film transistor, which is a switching element, is formed in an intersection region between the gate line 116 and the data line 117. A color filter substrate (not shown) is connected to the polycrystalline silicon thin film transistor in the pixel region, And a pixel electrode 118 for driving a liquid crystal layer (not shown) is formed.

The polycrystalline silicon thin film transistor according to an embodiment of the present invention includes a gate electrode 121 connected to the gate line 116, a source electrode 122 connected to the data line 117, And an electrode 123. The polycrystalline silicon thin film transistor includes an active layer 124 made of polycrystalline silicon which forms a conduction channel between the source electrode 122 and the drain electrode 123 by a gate voltage supplied to the gate electrode 121 do.

At this time, a part of the pixel electrode 118 overlaps a part of the gate line 116 under the gate insulating film 115a to form a storage capacitor Cst. The storage capacitor Cst serves to keep the voltage applied to the liquid crystal capacitor constant until the next signal is received. The storage capacitor Cst has effects such as stabilization of gray scale display and reduction of flicker and afterimage in addition to signal retention.

A gate pad electrode 126p and a data pad electrode 127p electrically connected to the gate line 116 and the data line 117 are formed in an edge region of the TFT substrate 110, The scan signal and the data signal received from the driver circuit portion (not shown) of the scan driver 116 and the data line 117, respectively.

That is, the gate line 116 and the data line 117 extend to the driving circuit portion and are connected to the corresponding gate pad line 116p and the data pad line 117p, respectively. The line 117p connects the scanning signal and the data signal from the driving circuit through the gate pad electrode 126p and the data pad electrode 127p electrically connected to the gate pad line 116p and the data pad line 117p, .

The data pad line 117p is connected to the data line 117 through a first contact hole formed in the link portion and the gate pad electrode 126p is connected to the gate pad via the second contact hole 140b. Line 116p and the data pad electrode 127p is electrically connected to the data pad line 117p through the third contact hole 140c.

For reference, reference numerals 125a, 125b, and 125 'each represent a source region, a drain region, and an n + amorphous silicon thin film pattern made of n + amorphous silicon.

The polycrystalline silicon thin film transistor according to an embodiment of the present invention having such a characteristic is formed between the source electrode 122 and the drain electrode 123 on the back channel region of the active layer 124, An etch stopper 150 made of an insulating film is formed. The etch stopper 150 serves to prevent the back channel region from being damaged by a subsequent process. That is, the etch stopper 150 according to the embodiment of the present invention is formed on the back channel region of the active layer 124 so that the back channel region of the active layer 124 can be chemically Contact with a material, wet or dry etching, and plasma process.

Particularly, the polycrystalline silicon thin film transistor according to the embodiment of the present invention adopts a lower gate structure like the general structure of the amorphous silicon thin film transistor, and the etch stopper 150, the active layer 124, The number of masks can be reduced in manufacturing the thin film transistor substrate 110 by forming the second and third contact holes 140b and 140c in a single mask process using a multiple exposure mask or a half-tone mask .

As described above, the thin film transistor substrate according to the embodiment of the present invention includes a plurality of exposure masks, that is, a blocking region made up of a dark portion, a first transparent region transmitting all light, a second transparent region having a half- A thin film transistor substrate can be manufactured through a total of four mask processes by forming an etch stopper, an active layer and a contact hole by a single mask process using a multi-tone mask in a third transmission region, The manufacturing method of the thin film transistor substrate will be described in detail.

6A to 6D are plan views sequentially illustrating the manufacturing process of the thin film transistor substrate shown in FIG.

7A to 7D are cross-sectional views sequentially illustrating a manufacturing process of the thin film transistor substrate shown in FIG.

6A and 7A, a substrate 110 made of a transparent insulating material forms a gate electrode 121 and a gate line 116 in a pixel portion, and a gate pad 121 and a gate pad 116 are formed in a gate pad portion and a data pad portion, respectively. Line 116p and a data pad line 117p.

The gate electrode 121, the gate line 116, the gate pad line 116p and the data pad line 117p are formed by depositing a first conductive layer on the entire surface of the substrate 110 and then performing a photolithography process A mask process).

Here, the first conductive layer may be formed of one selected from the group consisting of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), nickel (Ni), chromium A low resistance opaque conductive material such as molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta) The first conductive layer may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or the like. Layer structure.

6B and 7B, on the entire surface of the substrate 110 on which the gate electrode 121, the gate line 116, the gate pad line 116p, and the data pad line 117p are formed, The amorphous silicon thin film is crystallized into a polycrystalline silicon thin film through crystallization processes such as excimer laser crystallization or electron beam (e-beam).

Thereafter, an active layer 124 made of the polycrystalline silicon is formed on the gate electrode 121 by selective patterning through a photolithography process (second mask process), and the active layer 124 is formed on the back channel region of the active layer 124 An etch stopper 150 made of the insulating film is formed.

The etch stopper 150 is formed in an island shape on the back channel region of the active layer 124, thereby preventing the back channel of the thin film transistor from being damaged when patterning the source / drain electrode in a process to be described later.

A portion of the gate insulating layer 115a is removed from the link portion of the substrate 110 to form a first contact hole 140a exposing a portion of the data pad line 117p. A second contact hole 140b and a third contact hole 140b for partially exposing the gate pad line 116p and the data pad line 117p are formed in the pad portion of the gate insulating layer 115a, (140c) is formed.

Here, the active layer 124, the etch stopper 150, and the contact holes 140a to 140c according to the exemplary embodiment of the present invention may be formed by a single exposure process using a multiple exposure mask or a half-tone mask and an ashing process (Second mask process). The second mask process will be described in detail with reference to the drawings.

FIGS. 8A to 8I are cross-sectional views illustrating a second mask process according to an embodiment of the present invention shown in FIGS. 6B and 7B, which is a second mask process using a multiple exposure mask.

8A, a gate insulating layer 115a and an amorphous silicon layer are formed on the entire surface of the substrate 110 on which the gate electrode 121, the gate line 116, the gate pad line 116p and the data pad line 117p are formed. A thin film 120 'and an insulating film 130 are formed.

In this case, the gate insulating film (115a) and an insulating film 130 is a silicon nitride (SiNx), an inorganic insulating film or hafnium, such as a silicon oxide film (SiO _2); may be formed of a highly dielectric oxide film, such as (hafnium Hf) oxide, aluminum oxide .

The gate insulating layer 115a and the insulating layer 130 may be formed by a CVD method using a plasma enhanced chemical vapor deposition (PECVD) apparatus or a physical vapor deposition (PVD) method using a sputtering method .

Next, as shown in FIG. 8B, a predetermined crystallization process is performed to crystallize the amorphous silicon thin film 120 'into a polycrystalline silicon thin film 120.

Here, typical methods for forming the amorphous silicon thin film 120 'include a low pressure chemical vapor deposition (LPCVD) method and a plasma chemical vapor deposition method. In addition, various crystallization methods can be used for the crystallization of the amorphous silicon thin film 120 '. In the case of using a laser annealing method using a laser, excimer laser annealing (ELA) using a pulse- ) Method is mainly used, but it is also possible to use a sequential lateral solidification (SLS) method in which grains are grown in a horizontal direction to improve crystallization characteristics.

8C, a photoresist layer 170 made of a photosensitive material such as photoresist is formed on the entire surface of the substrate 110, and then a photoresist layer 170 is formed on the entire surface of the substrate 110 using a multiple exposure mask 180 according to an embodiment of the present invention. And selectively irradiates the photosensitive film 170 with light.

At this time, the multiple exposure mask 180 includes a first transmissive region I for transmitting all the irradiated light and a second transmissive region II consisting of a half-tone portion for transmitting only a part of light and blocking a part thereof, A third transmissive region III made of a slit portion and a blocking region IV blocking all the irradiated light are provided and only the light transmitted through the multiple exposure mask 180 is irradiated to the photoresist layer 170 .

8D, after the photoresist layer 170 exposed through the multiple exposure mask 180 is developed, the blocking region IV and the second transmissive region II and the third transmissive region 170, as shown in FIG. 8D, The first photoresist pattern 170a to the fourth photoresist pattern 170d having a predetermined thickness remain in a region where light is entirely blocked or partially blocked through the third transparent region III, The photoresist layer is completely removed and the surface of the insulating layer 130 is exposed.

The first photoresist pattern 170a formed in the blocking region IV may include a second photoresist pattern 170b through a fourth photoresist pattern 170b formed through the second transmissive region II and the third transmissive region III, 170d. The second photoresist pattern 170b and the third photoresist pattern 170c formed through the third transmissive area III are formed in the same pattern as the fourth photoresist pattern 170d formed through the second transmissive area II And the photoresist film is completely removed in the region where the light is completely transmitted through the first transmissive region I. This is because the positive type photoresist is used and the present invention is not limited thereto, A photoresist may be used.

Next, as shown in FIG. 8E, using the first photoresist pattern 170a to the fourth photoresist pattern 170d formed as described above as a mask, a gate insulating layer 115a, a polycrystalline silicon thin film 120 A first contact hole 140a is formed in a link portion of the substrate 110 to expose a part of the data pad line 117p. A second contact hole 140b and a third contact hole 140c for exposing a part of the gate pad line 116p and the data pad line 117p, respectively, are formed in the pad portion of the pad.

As shown in FIG. 8F, when the ashing process for removing a part of the thicknesses of the first to fourth photoresist patterns 170a to 170d is performed, The photoresist pattern is completely removed.

At this time, the first to third photoresist patterns to the fourth to the eighth photoresist patterns 170a 'to 170c' are removed by the thickness of the fourth photoresist pattern, The source region and the drain region corresponding to the third transmissive region III and the channel region between the source region and the drain region.

8G, if the polycrystalline silicon thin film and the insulating film formed therebelow are selectively removed using the remaining fifth photoresist pattern 170a 'to the seventh photoresist pattern 170c' as a mask, The active layer 124 made of the polycrystalline silicon is formed in the pixel portion of the substrate 110.

At this time, an insulating film pattern 130 'formed of the insulating film and patterned in substantially the same shape as the active layer 124 is formed on the active layer 124.

8H, when the ashing process for removing a part of the thickness of the fifth photoresist pattern 170a 'to the seventh photoresist pattern 170c' is performed, The sixth photosensitive film pattern and the seventh photosensitive film pattern are completely removed.

At this time, the fifth photoresist pattern is the eighth photoresist pattern 170a 'removed by the thickness of the sixth photoresist pattern and the seventh photoresist pattern only in the channel region corresponding to the blocking region III.

8I, a portion of the insulating film is selectively removed using the remaining eighth photosensitive film pattern 170a "as a mask, thereby forming the insulating film on the active layer 124, An etch stopper 150 for protecting the channel region of the layer 124 is formed.

As described above, the active layer 124, the etch stopper 150, and the contact holes 140a to 140c according to the embodiment of the present invention can be formed through a single mask process by using multiple exposure masks. As a result, the number of masks used in manufacturing the thin film transistor can be reduced, thereby providing a manufacturing process and a cost saving effect.

In addition, the thin film transistor according to the embodiment of the present invention forms and protects the etch stopper 150 so that the back channel region of the active layer 124 is not exposed, so that the thickness of the active layer 124 is relatively thin And it is possible to prevent the back channel region of the active layer 124 from being contaminated. As a result, the thickness of the active layer 124 and the gate insulating film 115a can be reduced, and the effect of substantially lowering the driving voltage and the threshold voltage of the thin film transistor can be obtained.

Meanwhile, as described above, the active layer, the etch stopper, and the contact hole may be formed through a single mask process by using a half-tone mask and an additional ashing process, which will be described in detail with reference to the following drawings.

FIGS. 9A to 9I are cross-sectional views illustrating another second mask process according to an embodiment of the present invention shown in FIGS. 6B and 7B, and show a second mask process using a half-tone mask and an ashing process .

9A, a gate insulating layer 215a and an amorphous silicon thin film 215b are formed on the entire surface of a substrate 210 on which a gate electrode 221, a gate line 216, a gate pad line 216p and a data pad line 217p are formed. (220 ') and an insulating film (230).

Then, as shown in FIG. 9B, the amorphous silicon thin film 220 'is crystallized into the polycrystalline silicon thin film 220 by performing a crystallization process such as laser crystallization or electron beam.

9C, a photoresist layer 270 made of a photosensitive material such as a photoresist is formed on the entire surface of the substrate 210, and then, a half-tone mask 280 according to an embodiment of the present invention is formed And selectively irradiates the photoresist layer 270 with light.

At this time, the half-tone mask 280 is provided with a first transmission region I through which all the irradiated light is transmitted, a second transmission region II through which only a part of light is transmitted and a portion is blocked, And only the light transmitted through the half-tone mask 280 is irradiated onto the photoresist layer 270.

After the photoresist layer 270 exposed through the half-tone mask 280 is developed, light is emitted through the blocking region III and the second transmissive region II, as shown in FIG. 9D. A first photoresist pattern 270a and a second photoresist pattern 270b having a predetermined thickness are left in an area where all the light is blocked or partially blocked and the photoresist is completely removed in the first light transmission area I The surface of the insulating film 230 is exposed.

At this time, the first photoresist pattern 270a formed in the blocking region III is thicker than the second photoresist pattern 270b formed through the second transmissive region II. In addition, the photoresist layer is completely removed from the region through which the light is completely transmitted through the first transmissive region I because the positive type photoresist is used. The present invention is not limited to this, May be used.

9E, using the first photoresist pattern 270a and the second photoresist pattern 270b formed as described above as a mask, a gate insulating layer 215a, a polycrystalline silicon thin film 220 A first contact hole 240a exposing a part of the data pad line 217p is formed on a link portion of the substrate 210. The first contact hole 240a may be formed on the substrate 210, A second contact hole 240b and a third contact hole 240c are formed to expose a part of the gate pad line 216p and the data pad line 217p, respectively.

Then, ashing process for removing a part of the thickness of the first photoresist pattern 270a and the second photoresist pattern 270b is performed, as shown in FIG. 9F, 2 photoresist pattern is completely removed.

At this time, the first photoresist pattern is formed by the third photoresist pattern 270a ', which is removed by the thickness of the second photoresist pattern, between the source region and the drain region corresponding to the blocking region III and between the source region and the drain region Only in the channel region of FIG.

9G, when the polycrystalline silicon thin film and the insulating film formed therebelow are selectively removed using the remaining third photoresist pattern 270a 'as a mask, the polycrystalline silicon thin film and the insulating film are selectively removed from the pixel portion of the substrate 210 An active layer 224 made of the polycrystalline silicon is formed.

At this time, the insulating layer pattern 230 'formed of the insulating layer and patterned in substantially the same shape as the active layer 224 is formed on the active layer 224.

9H, a part of the width of the third photoresist pattern 270a 'is removed to form a predetermined pattern of the fourth photoresist pattern 270a', as shown in FIG. 9H. To remain in the channel region only.

Thereafter, as shown in FIG. 9I, the active layer 224 is partially formed of the insulating film by selectively removing a part of the insulating film using the remaining fourth photoresist pattern 270a "as a mask, An etch stopper 250 for protecting the channel region of the layer 224 is formed.

Next, as shown in FIGS. 6C and 7C, after the n + amorphous silicon thin film and the second conductive film are deposited on the entire surface of the substrate 110 on which the active layer 124 and the etch stopper 150 are formed, Source / drain regions 125a and 125b made of n + amorphous silicon are formed in the pixel portion of the substrate 110 by selectively patterning the source / drain regions 125a and 125b through a process (a third mask process) The n + amorphous silicon thin film pattern 125 'made of the n + amorphous silicon is formed.

At this time, source / drain electrodes 122 and 123, which are made of the second conductive film and electrically connected to the source / drain regions 125a and 125b, are formed in the pixel portion of the substrate 110 through the third mask process. .

In addition, the data line 117 is formed of the second conductive film through the third mask process, and crosses the gate line 116 to define a pixel region. At this time, the data line 117 and the n + amorphous silicon thin film pattern 125 'are electrically connected to the lower data pad line 117p through the first contact hole 140a at the link portion.

The second conductive layer may be a low resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, nickel, chromium, molybdenum, titanium, platinum or tantalum to form a source electrode, a drain electrode and a data line . The second conductive layer may be formed of a transparent conductive material such as indium-tin-oxide or indium-zinc-oxide, or may have a multilayer structure in which two or more conductive materials are stacked.

6D and 7D, a third conductive layer is formed on the entire surface of the substrate 110 on which the source electrode 122, the drain electrode 123, and the data line 117 are formed. Then, a photolithography process (A fourth mask process), thereby forming a pixel electrode 118 made of the third conductive film and electrically connected to the drain electrode 123 in the pixel portion of the substrate 110 do.

The third conductive film is formed through the fourth mask process and is electrically connected to the gate pad line 116p and the data pad line 117p through the second contact hole 140b and the third contact hole 140c, A gate pad electrode 126p and a data pad electrode 127p which are electrically connected to each other are formed.

Here, the third conductive layer includes a transparent conductive material having a high transmittance such as indium-tin-oxide or indium-zinc-oxide to form a pixel electrode, a gate pad electrode, and a data pad electrode.

The thin film transistor substrate according to an embodiment of the present invention fabricated as described above is adhered to the color filter substrate opposite to the color filter substrate by a sealant formed on the outer side of the image display area. A black matrix for preventing light from leaking into the line, and a color filter for realizing red, green and blue colors are formed.

At this time, the color filter substrate and the thin film transistor substrate are bonded together through a covalent key formed on the color filter substrate or the thin film transistor substrate.

As described above, the present invention can be applied not only to liquid crystal display devices but also to other display devices manufactured using thin film transistors, for example, organic electroluminescent display devices in which organic electroluminescent devices are connected to driving transistors.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

1 is an exploded perspective view schematically showing a general liquid crystal display device.

2 is a cross-sectional view schematically showing a structure of a general polycrystalline silicon thin film transistor.

FIGS. 3A to 3F are cross-sectional views sequentially illustrating a manufacturing process of the thin film transistor shown in FIG. 2; FIG.

4 is a plan view schematically showing a part of a thin film transistor substrate according to an embodiment of the present invention.

5 is a cross-sectional view schematically showing a part of a thin film transistor substrate according to an embodiment of the present invention.

6A to 6D are plan views sequentially showing a manufacturing process of the thin film transistor substrate shown in FIG.

7A to 7D are cross-sectional views sequentially showing a manufacturing process of the thin film transistor substrate shown in FIG.

8A to 8I are cross-sectional views illustrating a second mask process according to an embodiment of the present invention shown in FIGS. 6B and 7B.

FIGS. 9A to 9I are cross-sectional views illustrating another second mask process according to the embodiment of the present invention shown in FIGS. 6B and 7B. FIG.

DESCRIPTION OF REFERENCE NUMERALS

110: substrate 116: gate line

116p: gate pad line 117: data line

117p: data pad line 118: pixel electrode

121: gate electrode 122: source electrode

123: drain electrode 124: active layer

126p: gate pad electrode 127p: data pad electrode

150: Etch Starper

Claims (9)

Providing a substrate comprising a pixel portion, a gate pad portion and a data pad portion; Forming a gate electrode and a gate line in the pixel portion through a first mask process, and forming a gate pad line and a data pad line in the gate pad portion and the data pad portion, respectively; Forming a gate insulating layer on the substrate on which the gate electrode, the gate line, the gate pad line, and the data pad line are formed; Forming an active layer made of polycrystalline silicon on the gate electrode over which the gate insulating film is formed through a second mask process and forming an etch stopper made of an insulating film on the active layer; Forming a first contact hole exposing a part of the data pad line by using the second mask process, forming a first contact hole exposing a part of the gate pad line and another part of the data pad line in the gate pad part and the data pad part, Forming a second contact hole and a third contact hole exposing the second contact hole; Forming a source / drain region made of n + amorphous silicon on the active layer through a third mask process and forming a source / drain electrode electrically connected to the source / drain region, Forming a data line electrically connected to a portion of the data pad line through the first contact hole; And And forming a pixel electrode electrically connected to the drain electrode through a fourth mask process. The method of claim 1, wherein the n + amorphous silicon thin film pattern is formed of the n + amorphous silicon under the data line by using the third mask process. 3. The method of claim 2, wherein the data line and the n + amorphous silicon thin film pattern are electrically connected to a part of the data pad line through the first contact hole. The method of claim 1, further comprising: forming a gate pad electrode and a data pad electrode electrically connected to the gate pad line and the data pad line through the second contact hole and the third contact hole using the fourth mask process, Wherein the method further comprises the step of forming a thin film transistor substrate. 2. The method of claim 1, Forming an amorphous silicon thin film and an insulating film on the gate insulating film; Crystallizing the amorphous silicon thin film into a polycrystalline silicon thin film; Forming a first photoresist pattern to a fourth photoresist pattern on the insulating layer by applying a plurality of exposure masks; Forming a first contact hole exposing a part of the data pad line by selectively removing the gate insulating film, the polycrystalline silicon thin film, and the insulating film using the first photoresist pattern to the fourth photoresist pattern as masks, Forming a second contact hole and a third contact hole exposing a pad line and a part of the data pad line; Forming a fifth photoresist pattern to a seventh photoresist pattern by removing the fourth photoresist pattern through a first ashing process and removing a portion of the thickness of the first photoresist pattern to the third photoresist pattern; Selectively removing the polycrystalline silicon thin film and the insulating film using the fifth photoresist pattern to the seventh photoresist pattern as masks to form an active layer made of the polycrystalline silicon on the gate electrode on which the gate insulating film is formed; Removing the sixth photosensitive film pattern and the seventh photosensitive film pattern through a second ashing process and removing a portion of the fifth photosensitive film pattern to form an eighth photosensitive film pattern; And And selectively removing a portion of the insulating film using the eighth photoresist pattern as a mask to form an etch stopper made of the insulating film on the active layer. 6. The method of claim 5, wherein the eighth photoresist pattern is formed to correspond to a channel region of the active layer. The method of claim 5, wherein the amorphous silicon thin film is crystallized using laser crystallization or an electron beam. 2. The method of claim 1, Forming an amorphous silicon thin film and an insulating film on the gate insulating film; Crystallizing the amorphous silicon thin film into a polycrystalline silicon thin film; Forming a first photoresist pattern and a second photoresist pattern on the insulating layer by applying a half-tone mask; Forming a first contact hole exposing a part of the data pad line by selectively removing the gate insulating film, the polycrystalline silicon thin film and the insulating film using the first photoresist pattern and the second photoresist pattern as masks, Forming a second contact hole and a third contact hole exposing a pad line and a part of the data pad line; Removing the second photoresist pattern through a first ashing process and removing a portion of the thickness of the first photoresist pattern to form a third photoresist pattern; Selectively removing the polycrystalline silicon thin film and the insulating film using the third photoresist pattern as a mask to form an active layer made of the polycrystalline silicon on the gate electrode on which the gate insulating film is formed; Forming a fourth photoresist pattern by removing a portion of the thickness and width of the third photoresist pattern through a second ashing process; And And selectively removing a portion of the insulating film using the fourth photoresist pattern as a mask to form an etch stopper made of the insulating film on the active layer. The method of claim 8, wherein the fourth photoresist pattern is formed to correspond to a channel region of the active layer.

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