KR101623596B1 - Organic light emitting diode display device - Google Patents

Abstract

The present invention relates to an organic light emitting diode display, and more particularly, A first capacitor formed between the first node and the second node; A second capacitor formed between the second node and the third node; A driving TFT including a gate electrode connected to the first node, a source electrode connected to the second node, and a drain electrode connected to the fourth node, the driving TFT being supplied with a high potential driving voltage through the second node; A first switch TFT for forming a current path between the fourth node and the anode electrode of the organic light emitting diode during the first and fourth periods; A second switch TFT connecting the first node and the fourth node during the first period and the second period; A third switch TFT for supplying a data voltage to the first node during a third period; A fourth switch TFT connecting the first node and the third node during the first and fourth periods; And a fifth switch TFT for connecting the first node and the third node during the first and second periods.

Description

TECHNICAL FIELD [0001] The present invention relates to an organic light emitting diode (OLED) display device,

The present invention relates to an organic light emitting diode display.

Various flat panel displays (FPDs) have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes (CRTs). The flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an electroluminescence device.

An electroluminescent device is a self-luminous device which is divided into an inorganic electroluminescent device and an organic light emitting diode (OLED) according to the material of the light emitting layer and emits self-luminous elements. The electroluminescent device has a high response speed, There is an advantage of a large viewing angle. The organic light emitting diode display device can be driven by driving methods such as voltage driving, voltage compensation, current driving, digital driving, and external compensation.

Organic light emitting diode. It is a self-luminous organic light-emitting device that emits light by using an electroluminescence phenomenon that emits light when a fluorescent or phosphorescent organic compound is energized. AM is divided into PM (passive type) and AM (active type) according to the driving method and AM is suitable for a large area high resolution.

FIGS. 1 and 2 are diagrams illustrating typical voltage driven pixels and driving signal waveforms of an AM organic light emitting diode display device.

1 and 2, each pixel of the AM organic light emitting diode display device includes a data line DL, a gate line GL intersecting with the data line DL, a switch TFT SW1, a drive TFT DR1 ), A storage capacitor (Cst), and an OLED.

The switch TFT SW1 is turned on in accordance with the scan pulse SCAN from the gate line GL to make the current path between the data line DL and the first node N1 conductive. The data voltage DATA from the data line DL is applied to the source electrode and the drain electrode of the switch TFT SW1 and to the gate of the drive TFT DR1 via the first node N1, Terminal. The driving TFT DR1 regulates the amount of current flowing to the OLED according to the voltage of the first node N1. The storage capacitor Cst maintains the voltage of the first node N1.

The electric characteristic deviations of the driving TFT DR1 formed in each of the pixels in the AM organic light emitting diode display device are relatively large, so that the luminance uniformity is not good and the picture quality may be deteriorated. The cause of the electric characteristic deviation of the driving TFT DR1 varies depending on the backplane of the panel. In a panel using a low temperature polysilicon (LTPS) -based backplane, TFT drifts due to excimer laser annealing (ELA) process variations, and amorphous silicon (a-Si) The deterioration of the TFT progressing while driving the panel proceeds differently for each pixel, resulting in a characteristic deviation of the TFT. Due to such a characteristic deviation of the TFT, the current outputted from the driving TFT DR1 is changed. In the case of an AM organic light emitting diode display device having pixels as shown in FIG. 1, if the threshold voltage (Vth) deviation of the driving TFT DR1 is 0 to 2 V, an error rate is generated up to 83.55% of the output current.

The present invention provides an organic light emitting diode display device capable of realizing image quality with uniform luminance regardless of a threshold voltage deviation of a driving TFT.

According to an aspect of the present invention, an organic light emitting diode display device includes an organic light emitting diode including an anode electrode and a cathode electrode to which a low potential driving voltage is supplied; A first capacitor formed between the first node and the second node; A second capacitor formed between the second node and the third node; A driving TFT including a gate electrode connected to the first node, a source electrode connected to the second node, and a drain electrode connected to the fourth node, the driving TFT being supplied with a high potential driving voltage through the second node; (N is a positive integer) emission control pulse generated during the first and fourth periods to form a current path between the fourth node and the anode electrode of the organic light emitting diode, ; A second switch TFT that is turned on according to an (n-1) th scan pulse during the first period and the second period to connect the first node and the fourth node; A third switch TFT which is turned on according to an n < th > scan pulse during a third period to supply a data voltage to the first node; A fourth switch TFT that is turned on according to the n-th emission control pulse for the first and fourth periods to connect the first node and the third node; And a fifth switch TFT which is turned on according to the (n-1) th scan pulse during the first and second periods to connect the first node and the third node.

The present invention can realize picture quality with uniform luminance regardless of the threshold voltage deviation of the driving TFT by using the circuit of the pixel. Furthermore, the present invention can increase the data voltage holding ratio in the light emitting period by using the capacitor for storing the threshold voltage of the driving TFT as a storage capacitor for storing data in the light emitting period.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The names of components used in the following description are selected in consideration of ease of specification, and may be different from actual product names.

3 and 4, the organic light emitting diode display of the present invention includes a display panel 100 in which M × N pixels (M and N are positive integers, respectively) are arranged in a matrix form, A scan driver for sequentially supplying a scan pulse SCAN and a light emission control pulse EM to the scan lines 103 intersecting the data lines 101, A data driver 104, and a timing controller 105 for controlling the data driver 102 and the scan driver 104.

The data driver 102 converts the digital video data RGB input from the timing controller 105 into a gamma compensation voltage and supplies the gamma compensation voltage to the data lines 101. The scan driver 104 sequentially supplies the scan pulses SCAND and the emission control pulses EM shown in FIG. 4 and FIG. 5 to the scan lines 103.

The timing controller 105 supplies the digital video data RGB to the data driver 102 and outputs a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync, a data enable signal DE and a dot clock CLK And generates timing control signals SDC and GDC for controlling the operation timings of the data driver 102 and the scan driver 104. [

Each of the pixels of the display panel 100 includes an OLED, six TFTs (T1 to T5, DT) and two capacitors (Cst, CVth) as shown in FIG. The TFTs T1 to T5 and DT may be implemented as a p-type MOSFET (metal-oxide-semiconductor field-effect transistor) as shown in FIG. The TFTs T1 to T5 and DT are not limited to p-type MOSFETs but may be implemented as n-type MOSFETs and CMOS (complementary metal semiconductor) TFTs. Hereinafter, with reference to FIG. 4 and FIG. 5, a circuit structure of an n-th (n is a positive integer) pixel and its operation will be described with reference to an example in which the TFTs T1 to T5 and DT are implemented by a p- .

4 and 5, a high potential driving voltage VDD, a low potential driving voltage VSS and an n-1th scanning pulse SCAN (n-1) are applied to the nth (n is a positive integer) , The n th scan pulse SCAN (n), and the n th emission control pulse EM (n).

The pixel includes an OLED, an OLED, a driving TFT DT, first through fifth switch TFTs T1 through T5, a first capacitor Cst, and a second capacitor CVth. The operation of the pixel may be divided into first to fourth periods as shown in FIG. The first period TA is an initial period for initializing the voltages of the first node N11 and the capacitors Cst and CVth. The second period TB is a threshold voltage sensing period (Vth sensing period) for sensing the threshold voltage Vth of the driving TFT DT and storing it in the capacitors Cst and Cth. The third period TC is a data program period for charging the data voltage [DATA (m)] to the first node. The fourth period TD is an emission period during which the OLED emits light according to the data voltage DATA (m).

A multilayer organic compound layer is formed between the anode electrode and the cathode electrode of the OLED. The organic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer EIL). The OLED emits light during the fourth period (TD) in accordance with the current supplied under the control of the driving TFT (DT). The anode electrode of the OLED is connected to the fourth node N14 and the cathode electrode thereof is connected to the low potential voltage source VSS or the ground voltage source GND.

The driving TFT DT supplies the current from the high potential power source VDD to the organic light emitting diode OLED via the fourth node N14 and controls the current to the gate-source voltage. The gate electrode of the driving TFT DT is connected to the first node N11, and the drain electrode thereof is connected to the fourth node N14. The high potential driving voltage VDD is applied to the source electrode of the driving TFT DT via the second node N12.

The first switch TFT T1 is turned on according to the n-th emission control pulse EM (n) during the fourth period TD to turn on the current path between the fourth node N14 and the anode electrode of the OLED . The first switch TFT T1 maintains an off state during the second period TA and the fourth period TD. The source electrode of the first switch TFT (T1) is connected to the fourth node (N14), and the drain electrode thereof is connected to the anode electrode of the OLED. The emission control pulse EM (n) is supplied to the gate electrode of the first switch TFT T1.

The second switch TFT T2 is turned on in accordance with the (n-1) th scan pulse SCAN (n-1) during the first and second periods TA and TB to turn on the gate electrode of the drive TFT DT and the drain Electrodes are connected to operate the driving TFT DT as a diode. The second switch TFT T2 maintains the off state during the third and fourth periods TC and TD. The source electrode of the second switch TFT T2 is connected to the drain electrode of the driver TFT DT via the fourth node N14 and the drain electrode thereof is connected to the driver TFT DT via the first node N11, As shown in FIG. The (n-1) th scan pulse SCAN (n-1) is supplied to the gate electrode of the second switch TFT T2.

The third switch TFT T3 is turned on according to the n-th scan pulse SCAN (n) during the third period TC to connect the data line 101 to the first node N11, 1 node N11. The third switch TFT T3 maintains the off state during the first, second and fourth periods TA, TB and TD. The source electrode of the third switch TFT (T3) is connected to the first node (N11), and the drain electrode thereof is connected to the data line (101). The n-th scan pulse SCAN (n) is supplied to the gate electrode of the third switch TFT T3.

The fourth switch TFT T4 is turned on according to the n-th emission control pulse EM (n) for the first and fourth periods TA and TD to turn on the second capacitor CVth to the first node N11, . The fourth switch TFT T4 is kept off during the second and third periods TB, TC. The source electrode of the fourth switch TFT (T4) is connected to the second capacitor (CVth) via the third node (N13), and the drain electrode thereof is connected to the first node (N11). The n-th emission control pulse EM (n) is supplied to the gate electrode of the fourth switch TFT (T4).

The fifth switch TFT T5 is turned on according to the (n-1) th scan pulse SCAN (n-1) during the first and second periods TA and TB to turn on the second capacitor CVth to the first node (N11). The fifth switch TFT T5 maintains the off state during the third and fourth periods TC and TD. The source electrode of the fifth switch TFT (T5) is connected to the second capacitor (CVth) via the third node (N13), and the drain electrode thereof is connected to the first node (N11). The (n-1) th scan pulse SCAN (n-1) is supplied to the gate electrode of the fifth switch TFT T5.

The first capacitor Cst is initialized while the voltage of the first node N11 is discharged during the first period TA and stores the source-drain voltage of the driving TFT DT during the second period TB, The threshold voltage Vth of the TFT DT is sampled. The first capacitor Cst maintains the voltage of the first node N11, that is, the gate voltage of the driving TFT DT, constant during the fourth period TD.

The second capacitor CVth is connected to the first node N11 during the first period TA and is initialized while the voltage of the first node N11 is discharged. And stores the source-drain voltage to sample the threshold voltage (Vth) of the driving TFT (DT). The second capacitor (CVth) maintains the voltage of the first node (N11) constant during the fourth period (TD).

The operation of the n-th pixel will be described step by step along the time axis of FIG. 5 as follows.

During the first period TA, the n-th emission control pulse EM (n) and the n-1th scan pulse SCAN (n-1) are generated as a low logic voltage. The nth light emission control pulse EM (n) and the (n-1) th scan pulse SCAN (n-1) are applied to the first, second, fourth and fifth switch TFTs T1, T2, T4, On state. During the first period TA, the voltage VN11 of the first node N11 is set to a low-potential driving state (i.e., a low-potential driving state) via the second TFT T2, the fourth node N14, the first switch TFT T1, And is discharged to the voltage source VSS. Therefore, the voltage of the first node N11 is lowered to a voltage close to the low potential driving voltage VSS during the first period TA. During the first period TA, the OLED is not emitted because the voltage of the first node N11 is lowered. During the first period (TA), the current flowing through the OLED is the leakage current flowing in the OFF state of the OLED. During the first period TA, the voltages of the first and second capacitors Cst and CVth are initialized to the difference voltage between the voltage VN11 of the discharged first node N11 and the high potential driving voltage VDD .

During the second period TB, the n-th scan pulse SCAN (n-1) maintains the low logic voltage while the nth emission control pulse EM (n) is inverted to the high logic voltage. The first and fourth switch TFTs T1 and T4 are turned off during the second period TB. The second and fifth switch TFTs T2 and T5 maintain the ON state. During the second period TB, the voltage of the first node N11 rises to the voltage of the first and second capacitors Cst and CVth to which the high potential driving voltage VDD is applied. During the second period TB, the first and second capacitors Cst and CVth are connected in parallel between the first node N11 and the second node N12 so that the gate-source voltage .

During the third period TC, the nth scan pulse SCAN (n-1) is inverted to a high logic voltage while the nth scan pulse SCAN (n) is inverted to a low logic voltage. The second and fifth switch TFTs T2 and T5 are turned off during the third period TC. The third switch TFT T3 is turned on according to the n-th scan pulse SCAN (n) during the third period TC. During the third period TC, the data voltage DATA ( _PGM ) is supplied to the first node N11.

During the fourth period TD, the nth scan pulse SCAN (n) is inverted to a high logic voltage, while the nth emission control pulse EM (n) is inverted to a low logic voltage. The third switch TFT (T3) is turned off during the fourth period (TD). The first and fourth switch TFTs T1 and T4 are turned on according to the nth emission control pulse EM (n) during the fourth period TD to constitute a circuit as shown in Fig. During the fourth period TD, the driver TFT DT regulates the current I _OLED flowing to the OLED in accordance with its gate voltage, that is, the data voltage DATA _EM . Thus, the OLED may emit during the fourth period (TD). During the fourth period TD, the voltage of the first node N11, that is, the data voltage DATA ( _EM ), is expressed by the following equation (1).

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the present invention should not be limited to the details described in the detailed description, but should be defined by the claims.

FIGS. 1 and 2 are diagrams illustrating typical voltage driven pixels and driving signal waveforms of an AM organic light emitting diode display device.

3 is a block diagram illustrating an organic light emitting diode display according to an embodiment of the present invention.

4 is a circuit diagram showing a pixel circuit of the display panel shown in Fig.

5 is a waveform diagram showing driving signals of the pixel shown in FIG.

6 is a circuit diagram showing the operation of the pixel circuit shown in FIG. 4 during the threshold voltage sensing period.

7 is a circuit diagram showing the operation of the pixel circuit shown in FIG. 5 during a light emission period.

Description of the Related Art

100: display panel 102: data driver

104: scan driver 105: timing controller

OLED: Organic light emitting diode Cst, CVth: Capacitor

DT: driving TFTs T1 to T5: switching TFT

Claims (7)

An organic light emitting diode including an anode electrode and a cathode electrode to which a low potential driving voltage is supplied; A first capacitor formed between the first node and the second node; A second capacitor formed between the second node and the third node; A driving TFT including a gate electrode connected to the first node, a source electrode connected to the second node, and a drain electrode connected to the fourth node, the driving TFT being supplied with a high potential driving voltage through the second node; (N is a positive integer) emission control pulse generated during the first and fourth periods to form a current path between the fourth node and the anode electrode of the organic light emitting diode, ; A second switch TFT that is turned on according to an (n-1) th scan pulse during the first period and the second period to connect the first node and the fourth node; A third switch TFT which is turned on according to an n < th > scan pulse during a third period to supply a data voltage to the first node; A fourth switch TFT that is turned on according to the n-th emission control pulse for the first and fourth periods to connect the first node and the third node; And And a fifth switch TFT which is turned on according to the (n-1) th scan pulse during the first and second periods to connect the first node and the third node. The method according to claim 1, During the fourth period, The data voltage DATA _EM to be charged to the first node may be expressed by Equation 1, where Cst is capacitance of the first capacitor, CVth is capacitance of the second capacitor, DATA _PGM , and the threshold voltage of the driving TFT is Vth.

The method according to claim 1, The first switch TFT includes: And a gate electrode connected to the scan line to which the n-th emission control pulse is supplied, a source electrode connected to the fourth node, a drain electrode connected to the anode electrode of the organic light emitting diode, Display device. The method of claim 3, The second switch TFT And a gate electrode connected to a source electrode connected to the fourth node, a drain electrode connected to the first node, and a scan line supplied with the (n-1) th scan pulse. . 5. The method of claim 4, The third switch TFT includes a source electrode connected to the first node, a drain electrode connected to the data line to which the data voltage is supplied, and a gate electrode connected to the scan line to which the nth scan pulse is supplied Characterized in that the organic light emitting diode display device. 6. The method of claim 5, And the fourth switch TFT includes a source electrode connected to the third node, a drain electrode connected to the first node, and a gate electrode connected to the scan line to which the nth emission control pulse is supplied Organic light emitting diode display. The method according to claim 6, And the fifth switch TFT includes a source electrode connected to the third node, a drain electrode connected to the first node, and a gate electrode connected to the scan line to which the (n-1) th scan pulse is supplied The organic light emitting diode display device.

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