KR101615732B1 - Wideband dual-tuned ring voltage controlled oscillator - Google Patents

Abstract

The present invention relates to a voltage controlled oscillator. The voltage-controlled oscillator includes a digital-to-analog converter (DAC) for outputting a voltage corresponding to a selected voltage level among voltage levels obtained by dividing a first voltage and a second voltage lower than the first voltage by a predetermined number, Stage ring VCO unit including first, second, and first delay cells, and a voltage regulator unit that converts the voltage output from the DAC unit to a constant voltage and supplies the voltage to the VOC unit with a set voltage for setting a frequency band. According to the present invention, there is provided a broadband dual tuning ring voltage controlled oscillator having a function of adjusting a voltage to frequency gain ( _KVCO ).

Description

[0001] The present invention relates to a wideband dual tuned ring voltage controlled oscillator

The present invention relates to a voltage controlled oscillator, and more particularly, to a broadband dual tuning ring voltage controlled oscillator having a function of adjusting a voltage to frequency gain (K _VCO ).

In recent times, impulse radio based ultra-wideband (IR-UWB) using sub-nanosecond impulse signals has been noted as a practical technology for Doppler radar systems that detect human vital signals such as heart and respiration. . The large bandwidth of IR-UWB provides increased time resolution, and the wide frequency range of IR-UWB can selectively use the optimal bandwidth to maximize the detection accuracy of biomedical signals that vary according to the object and conditions. Let's do it.

A major component of this IR-UWB system is a wideband ring voltage controlled oscillator (VCO) used to generate a reference frequency in the range of multiple GHz.

However, excessive voltage to frequency gain (K _VCO ) is inevitable in a typical broadband ring voltage controlled oscillator. Since a large K _VCO results in too small a charge pump current or too large a loop filter capacitance, a large K _VCO will not only produce a voltage-controlled oscillator that is susceptible to noise, Loop, and PLL). Also, changes in process, voltage, and temperature (PVT) as well as sensitive variations in K _VCO at different frequencies degrade the stability of the phase-locked loop.

In recent years, dual frequency tuning concepts such as the division of sub-frequency bands have been introduced in order to obtain a wide range and a stable K _VCO . However, the frequency range of the voltage controlled oscillator to which this technique is applied is limited to several hundreds of M Hz, and there is no method of scaling the K _VCO .

Therefore, there is a need for a voltage controlled oscillator having a K _VCO scaling function, which can stably maintain the K _VCO over a wider frequency band, ensure stable operation of the phase-locked loop.

Accordingly, it is an object of the present invention to provide a broadband dual tuning ring voltage controlled oscillator having a function of adjusting a voltage-to-frequency gain (K _VCO ).

According to an aspect of the present invention, there is provided a voltage-controlled oscillator including a voltage-controlled oscillator for outputting a voltage corresponding to a selected voltage level among a voltage level obtained by equally dividing a first voltage and a second voltage lower than the first voltage by a predetermined number Stage ring VCO unit including a first and a second delay cell, and a second-stage ring VCO unit for converting the voltage output from the DAC unit into a constant voltage, And a voltage regulator unit for supplying the voltage to the VCO unit.

The DAC unit may be a DAC of 6-bit string structure using 64 resistors, and may include two 3-bit decoders for selection of the voltage level.

In order to achieve the above object, the present invention provides an electronic device for generating a reference frequency using the voltage-controlled oscillator.

According to the present invention, a new broadband dual tuning ring voltage controlled oscillator is provided that has the ability to adjust the voltage to frequency gain ( _KVCO ). The voltage-controlled oscillator according to the present invention can divide the frequency band of 6 GHz equally using a DAC that controls V _coarse , and can be set digitally using a DAC. Further, the specific target oscillation frequency can be finely adjusted by changing the intensity of the latch in the delay cell. Then, the latch bank for fine-tuning, voltage-to-frequency gain (K _VCO) can appropriately be adjusted, as a whole 2-8 voltage gain vs. frequency over the frequency band G㎐ (K _VCO) can be kept stable Therefore, stable operation of the phase-locked loop can also be guaranteed.

1 is a circuit diagram of a voltage-controlled oscillator according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a delay cell in FIG. 1,
3 and 4 are graphs showing output spectra of a voltage-controlled oscillator according to an embodiment of the present invention,
5 is a graph showing oscillation frequency vs. V _coarse of a voltage controlled oscillator according to the present invention,
FIG. 6 is a graph showing the phase noise measured in the voltage-controlled oscillator according to the present invention,
7 is a graph showing output frequencies of a voltage-controlled oscillator according to an embodiment of the present invention,
8 is a graph showing voltage vs. frequency gain in a voltage controlled oscillator according to the present invention, and
9 is a table comparing the performance of the voltage-controlled oscillator according to the present invention.

Hereinafter, the present invention will be described in detail with reference to the drawings.

1 is a circuit diagram of a voltage-controlled oscillator according to an embodiment of the present invention.

1, the voltage controlled oscillator 100 includes a digital-to-analog converter (DAC) unit 110 having a string structure, a voltage regulator unit 130, and a two-stage ring VCO unit 150 .

The DAC unit 110 of the string structure is a D / A converter having a series of resistors arranged in series to ensure monotonicity due to the string structure. In the present voltage-controlled oscillator 100, it is possible to use a DAC 110 of a 6-bit string structure in which 64 registers of R0 to R63 are basically arranged in series to evenly divide the voltage level between V _high and V _low have.

The two 3-bit decoder bridges 115 and 117 in the DAC unit 110 of the string structure divide one of the 64 voltage levels between V _high and V _low into the voltage regulator unit 130 according to DAC <5: 0> As shown in FIG.

The voltage regulator 130 converts the voltage input from the DAC unit 130 into a constant voltage and provides it as V _coarse which sets the frequency band of the voltage controlled oscillator 100. Since the output frequency of the voltage-controlled oscillator 100 is linearly tuned by the supplied voltage, the frequency bands of 64 are equalized.

FIG. 2 shows a delay cell in FIG.

A delay cell in the voltage controlled oscillator 100 according to the present invention includes NMOSFETs M _n1 and M _n2 , PMOSFETs M _p1 and M _p2 , and a latch bank 170.

The latch bank 170 is composed of four latch portions 171, 173, 175 and 177, and each latch portion includes a PMOSFET cross coupling pair M _p3 and M _p4 and two NMOSFETs M _n3 , M _n4 ).

In this configuration, since the PMOSFET M _p1 or M _p2 adjusts the output impedance of the delay cell to be in inverse proportion to V _coarse , the frequency tuning is linear and the tuning range is greatly extended.

For fine tuning, the voltage-controlled oscillator 100 controls the strength of the latch portions 171, 173, 175, and 177 using the NMOSFETs M _n3 and M _n4 as switching elements. When V _fine decreases, the desired latch section causes the output frequency to increase.

The four latch portions 171, 173, 175, and 177 in the latch bank 170 are for _KVCO control. And although every latch unit M _p3 and M _p4 are the same size in the (171, 173, 175, 177 ), M n3 (3: 0), M n4 (3: 0) of the W / L ratio of 10: 4: 3 : 2.

According to the switching unit S <3: 0>, the gates of M _n3 <3: 0> and M _n4 <3: 0> can be connected to one of V _fine or V _DD . Thus, only the selected latch portion S (k) = 1 participates in the frequency tuning, so the higher value of S < 3: 0 > results in a higher K _VCO .

For stable operation of the voltage controlled oscillator 100, the MSB S <3> is fixed at zero and provides a default path for the oscillator. Thus, eight completely different K _VCOs can be used.

를 분석하면 다음과 같다.Meanwhile, in the voltage-controlled oscillator 100 according to the present invention,

The following is the analysis.

는 다음의 식과 같이 나타낼 수 있다. Generally, the oscillation frequency of the N-stage ring VCO

Can be expressed by the following equation.

은 단계의 수,

은 한 단계의 전파 지연,

은 출력 임피던스,

은 부하 커패시턴스를 나타낸다. 따라서,

의 변화에 따라

가 변경되므로, 결국

도 변경된다.here,

The number of steps,

Is one stage of propagation delay,

Output impedance,

Represents the load capacitance. therefore,

According to the change of

Is changed, eventually

Is also changed.

은 다음의 [수학식 2]와 같이 나타낼 수 있다.In the delay cell shown in Fig. 2

Can be expressed by the following equation (2).

,

, 및

는 각각

,

,

의 진성 출력 임피던스이다. 또한,

는

의 트랜스 컨덕턴스(transconductance)이고,

는 래치(latch)의 트랜스 컨덕턴스이다. here,

,

, And

Respectively

,

,

Is the intrinsic output impedance. Also,

The

Is transconductance,

Is the transconductance of the latch.

는 다음과 같이 나타낼 수 있다.According to the equations (1) and (2)

Can be expressed as follows.

는 거시적 튜닝시

의 변화에 의해 제어되며, 미시적 튜닝시

변화에 의해 제어될 수 있다.Based on Equation (3), in the voltage controlled generator 100 according to the present invention,

Macro tuning

Is controlled by the change of the micro-tuning

Can be controlled by a change.

는 다음과 같이 나타낼 수 있다.With respect to macroscopic tuning, in equation (3) the DC operating point

Can be expressed as follows.

는

의 종횡비(aspect ration) 이다. here,

The

(Aspect ration) of the surface.

와

사이의 관계은 다음의 식과 같이 나타낼 수 있다.From Equation (3) and Equation (4)

Wow

Can be expressed as the following equation.

를 스위핑(sweeping)하여, 광대역

는 선형적으로 제어될 수 있다.

Sweeping,

Can be controlled linearly.

는 뱅크에서 4개의 레지의 트랜스 컨덕턴스의 합으로 표현할 수 있다.With respect to micro-tuning, in Equation (3)

Can be expressed by the sum of the transconductances of four banks in the bank.

에 도달하기 전에 신호는 스위치

에 의해 억제된다. 그러므로, [수학식 6]에서

는 다음과 같이

,

의 온 레지스턴스, 및

,

의 게이트에서 커패시턴스로 구성된 진성 RC-필터에 의해 억제된

로 간주할 수 있다.In each latch

Lt; RTI ID = 0.0 &gt;

. Therefore, in Equation (6)

Is as follows

,

On resistance, and

,

Suppressed by an intrinsic RC-filter consisting of a capacitance at the gate of

.

는

의 종횡비이다. 그리고,

는, 도 2에 도시한 바와 같이, k번째 래치가 주파수 튜닝에 사용되면 1이고, 그 외의 경우에는 0을 나타낸다. 만일

이 충분히 큰 경우,

가 동일한 크기를 가지므로,

와

사이의 관계는 다음과 같이 나타낼 수 있다.here,

The

. And,

2 is 1 when the kth latch is used for frequency tuning as shown in Fig. 2, and 0 otherwise. if

Is sufficiently large,

Lt; / RTI &gt; have the same size,

Wow

Can be expressed as follows.

는

에 의해 미세하게 튜닝될 수 있다.therefore,

The

Lt; / RTI &gt;

에 대한

의 변화율은 NMOS 스위치의 전체 크기인

에 비례한다.According to Equation (9)

For

Lt; RTI ID = 0.0 &gt; NMOS &lt; / RTI &

.

대신 VDD에 연결된다. As described above, the largest switch is for stable operation of the voltage-controlled oscillator

Instead it is connected to VDD.

의 관계는 다음의 식과 같이 나타낼 수 있다.

Can be expressed as the following equation.

의 제어에 의해 8 레벨 중 하나로

는 스케일될 수 있다.Based on Equation (10), it can be seen that in the entire frequency band

By one of the eight levels

Can be scaled.

3 to 8 are graphs showing experimental results of the voltage-controlled oscillator according to the present invention. For the experiments, the voltage controlled oscillator 100 according to the present invention was fabricated in a 65 nm CMOS process. The V _high and V _low of the DAC unit 110 are set to 1.35 V and 0.71 V, respectively.

3 and 4 are graphs showing output spectrums of a voltage-controlled oscillator according to the present invention.

FIG. 3 shows the output spectrum measured at 4.04 GHz, and FIG. 4 shows the output spectrum measured at 8.16 GHz.

5 is a graph illustrating oscillation frequency vs. V _coarse of a voltage controlled oscillator according to the present invention.

Referring to FIG. 5, a voltage controlled oscillator according to the present invention covers 2-8 GHz, resulting in a 120% tuning range. In addition, the linear oscillation frequency versus V _coarse curve shows that voltage controlled oscillator 100 provides equally divided subbands.

6 shows the phase noise measured at 4.21 GHz.

Referring to FIG. 6, in the voltage controlled generator according to the present invention, phase noise exhibits -82.7 dBc / Hz at 100 KHz and -101 dBc / Hz at 1 MHz

7 is a graph showing the output frequency of the voltage-controlled oscillator according to the present invention.

In Fig. 7, the oscillation frequency for V _fine was measured in three bands set by V _coarse . That is, it is a high band around 7.5 GHz, a middle band around 5.0 GHz, and a low band around 3.5 GHz.

As can be seen in FIG. 7, when V _fine swwts incrementally, the oscillation frequency decreases, which corresponds to an analysis that the strong latch hinders the oscillation of the fast voltage controlled oscillator.

In Figure 7, if more latches are excluded by V _fine (higher S < 2: 0 &gt;), the slope of the curve becomes steep, resulting in a high K _VCO .

This trend is visualized in FIG. 8 as a graph of K _VCO vs. S < 2: 0 &gt;. Depending on the change in S <2: 0>, the K _VCO can be scaled as needed.

For example, in the region highlighted in gray in FIG. 8, when S <2: 0> is appropriately set in each band, the K _VCO becomes constant over the range of multi GHz, ensuring the stability of the PLL . The active region of the voltage controlled oscillator (VCO) is 0.038 ㎟, and the power consumption is 1.7 ㎽ at 2 ㎓ and 6.8 ㎽ at 8 ㎓.

9 is a table comparing the performance of the voltage-controlled oscillator according to the present invention.

9 shows the performance of the voltage-controlled oscillator according to the present invention, and the reference document is as follows.

[1] C. Ta-Shun et al., &Quot; A short-range UWB impulse-radio CMOS sensor forhumanfeaturedetection, in Proc. IEEE Int. Conf. Solid-State Circuits (ISSCC'11), Feb. 2011, pp. 294.296.

[2] L. HaiQi et al., "A low-noise multi-GHz CMOS multiloop ring oscilator with coarse and fine frequency tuning," IEEE Trans. Very Large Scale Integr. Syst., Vol. 17, pp. 571-577, 2009.

[3] S. Zhinian et al., "A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture," IEEE J. Solid-State Circuits, vol. 39, pp. 452-462, 2004.

[4] L. Changzhi et al., "A 1-9 GHz linear-wide-tuning-range quadrature ring oscillator in 130 nm CMOS for non-contact vital sign radar ap-plication," IEEE Microw. Wireless Compon. Lett., Vol. 20, pp. 34-366, 2010.

[5] Y. Wachiet et al., &Quot; A28 GHzlow-phase-noiseCMOSVCOusinganamplitude-redistribution technique, &quot; in Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC'08), Feb. 2008, vol. 482, pp. 3.7.

[6] J. Liang et al., "A 6.0-13.5 GHz alias-locked loop frequency synthesizer in 130 nm CMOS," IEEE Trans. Circuits Syst. I: Regular Papers, vol. 60, no. 1, p. 108, 115, Jan. 2013.

[7] B. Fahset et al. "A two-stage ring oscillator 0.13-um CMOS for UWB impulse radio," IEEE Trans. Microw. Theory Tech., Vol. 57, no. 5, p. 1074, 1082, May 2009.

In addition, a performance comparative table is described in Y. Wachiet et al., "A 28 GHz low-phase-noise CMOS VCO using an amplitude-redistribution technique, IEEE Int. Solid-State Cir-cuits Conf. (ISSCC'08), Feb. 2008, vol. 482, pp. Included are the frequency-tuning range (FTR) and figure of merit (FOM) as defined in paragraphs 3-7.

Referring to FIG. 9, the voltage controlled oscillator 100 according to the present invention has a much higher FTR than the dual tuning architecture disclosed in [2] and [3]. In addition, it can be seen that the voltage controlled oscillator according to the present invention provides a competitive FOM having a good phase noise and a wide tuning range as compared with the latest broadband voltage controlled oscillator disclosed in [4], [6] and [7].

The voltage controlled oscillator according to the present invention is not limited in the configuration and the method of the embodiments described above, but the embodiments may be modified so that all or some of the embodiments are selectively As shown in FIG.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, It should be understood that various modifications may be made by those skilled in the art without departing from the spirit and scope of the present invention.

110: DAC unit 130: Voltage regulator unit
150: VCO unit 170: latch bank

Claims (9)

A digital-to-analog converter (DAC) for outputting a voltage corresponding to a selected voltage level among voltage levels obtained by dividing a first voltage and a second voltage lower than the first voltage by a predetermined number;
A two-stage ring VCO unit including first and second delay cells; And
And a voltage regulator unit for converting a voltage output from the DAC unit into a constant voltage and supplying the voltage to the VCO unit at a set voltage for setting a frequency band,
The first and second delay cells may include:
A first PMOSFET having a source connected to the set voltage;
A second PMOSFET whose source is connected to the set voltage;
A drain connected to a first node to which a gate and a drain of the first PMOSFET are connected, and a source connected to a ground terminal;
A second NMOSFET having a drain connected to a second node to which a gate and a drain of the second PMOSFET are connected, and a source connected to a ground terminal; And
And a latch bank coupled between the first node and the second node. The method according to claim 1,
Wherein the DAC unit is a 6-bit string DAC using 64 resistors. 3. The method of claim 2,
Wherein the DAC section comprises two 3-bit decoders for selection of a voltage level. The method according to claim 1,
The voltage regulator unit includes:
An operational amplifier to which an output voltage of the DAC unit is connected to a negative input terminal; And
A gate connected to an output terminal of the operational amplifier, a drain connected to a power supply voltage, and a source connected to a (+) input terminal of the operational amplifier to supply a voltage for setting an oscillation frequency band of the ring VCO section And a voltage controlled oscillator. delete The method according to claim 1,
Wherein the latch bank includes first to fourth latch portions. The method according to claim 6,
Each of the first through fourth latch portions includes:
A third PMOSFET having a source connected to the set voltage and a drain connected to the first node;
A fourth PMOSFET having a source connected to the set voltage and a drain connected to the second node;
A third NMOSFET having a source connected to the first node and a drain connected to a gate of the fourth PMOSFET; And
A source coupled to the second node, a drain coupled to a gate of the third PMOSFET, and a gate coupled to a gate of the third NMOSFET. The method according to claim 6,
Wherein the latch bank further comprises a switching unit for supplying a voltage set to the latch unit selected from the first to fourth latch units. An electronic device for generating a reference frequency by using the voltage-controlled oscillator according to any one of claims 1 to 4 or 6 to 8.

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