KR101611912B1 - Display device - Google Patents

Abstract

The present invention relates to a display device capable of automatically recognizing the format of image data without allocating an external format information signal by allocating data format information to idle bits of image data, And if there is an idle bit in the image data, assigns to the idle bit information about the format of the image data to the unused idle bit among the bits constituting the image data, ; And a timing controller for receiving the image data from the system and recognizing the format information assigned to the idle bit of the image data to recognize the format format of the image data and formatting and outputting the image data according to the recognized result. .

Display, Format, System, LVDS, Timing controller, JEIDA, VESA

Description

Display device {DISPLAY DEVICE}

The present invention relates to a display device, and more particularly to a display device capable of automatically recognizing the format of image data without allocating a separate format information signal from the outside by allocating data format information to idle bits of image data.

The image data from the system is formatted in various ways. In this case, the format information of the image data must be provided to the timing controller that receives the image data from the system. Conventionally, any one of a plurality of pins formed in the connector for connecting the system and the timing controller, A format information signal indicating the format of the data is provided to the timing controller. That is, the format information signal is externally applied to the pin by hardware or software so that the timing controller can recognize the format of the image data. However, if the size of the resistor connected to the pin is unstable, the timing controller can not correctly recognize the logical state of the format information signal, and thus image data is output in a format format different from the format format of the originally set image data .

Also, if the protocol of the format information differs between the system provider and the display device provider, there may be a great problem in compatibility between the system and the display device.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the problems described above, and it is an object of the present invention to provide an image processing apparatus and method, And it is an object of the present invention to provide a display device in which the timing controller can automatically recognize the format information for the image data.

According to an aspect of the present invention, there is provided a display apparatus including: a display control unit for checking whether there is an idle bit in image data, and when there is an idle bit in the image data, A system for allocating information on a formatting method of data to the idle bit, and outputting image data including the formatting information; And a timing controller for receiving the image data from the system and recognizing the format information assigned to the idle bit of the image data to recognize the format of the image data and formatting and outputting the image data according to the recognized result, .

When there is no idle bit in the image data, the system supplies the image data in which the idle bit does not exist to the timing controller, and outputs a format information signal indicating information on the format of the image data to the timing controller Supply; The timing controller formats and outputs the image data in which the idle bit does not exist according to the format information signal.

The system and the timing controller transmit and receive the image data through an interface unit of a low voltage differential signal (LVDS) system.

Wherein the interface unit comprises: an LVDS transmission unit for outputting, in the form of an LVDS signal, image data in the form of a TTL (Transistor Transistor Logic) signal input from the system; A plurality of differential signal transmission lines for transmitting image data in the form of an LVDS signal from the LVDS transmission unit; And an LVDS receiver for recovering image data of the LVDS signal type input from the differential signal transmission lines into a TTL signal form.

Wherein the image data includes a 1-bit data enable signal, a 1-bit vertical synchronizing signal, a 1-bit horizontal synchronizing signal, 8-bit red data, 8-bit green data, and 8-bit blue data; The plurality of differential signal transmission lines are composed of four; Each differential signal transmission line transmits data by 7 bits during one period of a clock pulse; The first differential signal transmission line sequentially transmits 6 bits of red data and 1 bit of green data for one period of the clock pulse; The second differential signal transmission line sequentially transmits 5 bits of green data and 2 bits of blue data for one period of the clock pulse; The third differential signal transmission line sequentially transmits 4 bits of blue data, 1 bit of a horizontal synchronizing signal, 1 bit of a vertical synchronizing signal, and 1 bit of a data enable signal in one cycle of the clock pulse; The fourth differential signal transmission line includes 2 bits of red data, 2 bits of green data, 2 bits of blue data, and 1 bit of format information indicating information on the format of the image data for one period of the clock pulse Respectively.

Wherein the image data includes a 1-bit data enable signal, a 1-bit vertical synchronizing signal, a 1-bit horizontal synchronizing signal, 10-bit red data, 10-bit green data, and 10-bit blue data; The plurality of differential signal transmission lines are composed of five; Each differential signal transmission line transmits data by 7 bits during one period of a clock pulse; The first differential signal transmission line sequentially transmits 6 bits of red data and 1 bit of green data for one period of the clock pulse; The second differential signal transmission line sequentially transmits 5 bits of green data and 2 bits of blue data for one period of the clock pulse; The third differential signal transmission line sequentially transmits 4 bits of blue data, 1 bit of a horizontal synchronizing signal, 1 bit of a vertical synchronizing signal, and 1 bit of a data enable signal in one cycle of the clock pulse; The fourth differential signal transmission line sequentially outputs 2-bit red data, 2-bit green data, 2-bit blue data, and 1-bit format information indicating information on the format of the image data for one period of the clock pulse Transmit; The fifth differential signal transmission line sequentially transmits 2 bits of red data, 2 bits of green data, 2 bits of blue data, and 1 bit of idle bits in one cycle of the clock pulse.

The format information is any one of logical data '1' and '0'; If the image data is a format of JEIDA (Japanese Electronics Industry Development Association) scheme, the logical data of the format information is '1'; If the image data is of the Video Electronics Standards Association (VESA) format, the logical data of the format information is '0'.

The display device according to the present invention has the following effects.

First, by assigning information on the formatting method of the image data to the idle bits of the image data provided through four or more differential signal transmission lines, the timing controller automatically outputs the format information for the image data without any external format information signal .

Second, since the image data provided through the differential signal transmission lines of three pairs or less is confirmed by the format information signal from the outside and recognizes the format of the image data, image data using four or more pairs of differential signal transmission lines and image data of three The format information can be recognized for all of the image data using the differential signal transmission lines of the pair or less.

1 is a view showing a display device according to an embodiment of the present invention.

1, a display device according to an embodiment of the present invention includes gate lines GL and data lines DL intersecting with each other, and gate lines GL and data lines DL, A data driver 8 for inputting data to the data lines DL of the display panel 2, a display panel 2 including a thin film transistor (TFT) A gate driver 10 for inputting scan pulses to the gate lines GL of the display panel 2, a backlight unit 4 including a plurality of light sources for emitting light to the display panel 2, A lamp driver 6 for driving the light sources of the backlight unit 4 and a timing controller 6 for controlling the data driver 8, gate driver 10 and lamp driver 6 of the display panel 2 12, a liquid crystal display panel and a backlight unit 4, Includes a power generating unit (14).

The thin film transistor TFT formed at the intersection of the data lines DL and the gate lines GL of the display panel 2 receives the data on the data lines DL in response to the scanning pulse from the gate driver 10. [ To the liquid crystal cell. The source electrode of the thin film transistor TFT is connected to the data line DL, and the drain electrode is connected to the pixel electrode of the liquid crystal cell. The gate electrode of the thin film transistor TFT is connected to the gate line GL. The display panel 2 includes a color filter array substrate and a TFT array substrate bonded together with a liquid crystal layer interposed therebetween. A color filter and a common electrode are formed on the color filter array substrate. The color filters allow red, green, and blue color filter layers to be disposed to transmit light in a specific wavelength band, thereby enabling color display. A black matrix is formed between color filters of adjacent colors.

Each liquid crystal cell includes a liquid crystal capacitance capacitor Clc for holding data for one frame period and an auxiliary capacitance capacitor for stably maintaining the data for the frame period.

The timing controller 12 rearranges the pixel data input from the digital video card by the red pixel data R, the green pixel data G and the blue pixel data B. The pixel data (R, G, B) rearranged by the timing controller 12 is input to the data driver 8.

The timing controller 12 generates the data control signal DCS and the gate control signal GCS using the horizontal synchronizing signal H, the vertical synchronizing signal V and the clock signal CLK input to the timing controller 12 And supplies it to the data driver 8 and the gate driver 10. The data control signal DCS includes a dot clock, a source shift clock, a source enable signal, a polarity reversal signal, and the like. The gate control signal GCS is input to the gate driver 10 including a gate start pulse, a gate shift clock, a gate output enable, and the like.

The data driver 8 samples the pixel data in accordance with the data control signal DCS from the timing controller 12 and then outputs the sampled data to the latch circuit 1 for each horizontal period (1H, 2H, ...) And supplies the latched data to the data lines DL. That is, the data driver 8 converts the pixel data (R, G, B) from the timing controller 12 into an analog pixel signal using the gamma voltages GMA1 to GMA6 input from the power generator 14 And supplies them to the data lines DL.

The gate driver 10 includes a shift register for sequentially generating a scan pulse in response to a gate start pulse of a gate control signal GCS from the timing controller 12 and a control circuit for controlling the voltage of the scan pulse to a voltage level suitable for driving the liquid crystal cell And a level shifter. The gate driver 10 sequentially supplies a gate high voltage to the gate lines GL in response to the gate control signal GCS.

The power generating unit 14 supplies the common electrode voltage Vcom to the display panel 2 and the gamma voltages GMA1 to GMA6 to the data driver 8. [

2 is a diagram for explaining a method of transmitting image data between the timing controller and the system of FIG.

As shown in FIG. 2, the system 55 and the timing controller 12 are connected by an interface unit 60 of a low voltage differential signal (LVDS) scheme. That is, the system 55 and the timing controller 12 exchange image data through the interface unit 60. 2, the interface unit 60 includes an LVDS transmission unit 33 for outputting image data in the form of a TTL (Transistor Transistor Logic) signal input from the system 55 in the form of an LVDS signal, A plurality of differential signal transmission lines LVL1 to LVL4 for transmitting image data in the form of an LVDS signal from the differential signal transmission lines 33 and an image data in the form of an LVDS signal input from the differential signal transmission lines LVL1 to LVL4, And an LVDS receiver 44 for recovering the TTL signal form.

The LVDS transmitting unit 33 is embedded in the system 55 and the LVDS receiving unit 44 is embedded in the timing controller 12. [

3 is a detailed configuration diagram of the interface unit 60 of FIG.

As shown in FIG. 3, the LVDS transmitter 33 includes a plurality of transmitters Tx1 to Tx4. The transmitters Tx1 to Tx4 change the image data of the TTL signal type supplied thereto to the LVDS signal form and supply the image data of the LVDS signal form to the LVDS receiver 44 through the plurality of differential signal transmission lines do. Each differential signal transmission line is composed of two differential lines La and Lb. A terminal resistance RT is connected to the ends of the pair of differential lines La and Lb.

The LVDS receiving unit 44 includes a number of receivers Rx1 to Rx4 corresponding to the transmitters Tx1 to Tx4. The receivers Rx1 to Rx4 restore the image data of the LVDS signal type supplied thereto to TTL signal form and output it.

The system 55 confirms whether there is an idle bit in the image data, and when there is an idle bit in the image data, the system 55 writes the information on the format of the image data to the unused idle bit among the bits constituting the image data, Bit, and outputs image data including this format information.

The timing controller 12 receives the image data from the system 55, identifies the format information assigned to the idle bit of the image data, recognizes the format of the image data, and outputs the image data in accordance with the recognized result Format and output.

This image data can be formatted in any one of a Japanese Electronics Industry Development Association (JEIDA) scheme and a Video Electronics Standards Association (VESA) scheme.

4A is a diagram showing that image data including 8 bits of red, green, and blue data is formatted and transmitted in a JEIDA manner.

As shown in FIG. 4A, the image data includes a 1-bit data enable signal DE, a 1-bit vertical synchronizing signal Vsync, a 1-bit horizontal synchronizing signal Hsync, R19, 8-bit green data G12-G16, and 8-bit blue data B12-B19.

Each of the differential signal transmission lines LVL1 to LVL4 transmits data by 7 bits during one period of the clock pulse CLK.

That is, the first differential signal transmission line LVL1 sequentially transmits 6 bits of red data (R14 to R19) and 1 bit of green data (G14) during one period of the clock pulse (CLK); The second differential signal transmission line LVL2 sequentially transmits 5 bits of green data G15 to G19 and 2 bits of blue data B14 and B15 for one period of the clock pulse CLK; The third differential signal transmission line LVL3 outputs 4 bits of blue data B16 to B19, 1 bit of a horizontal synchronization signal Hsync, 1 bit of a vertical synchronization signal Vsync, , And a 1-bit data enable signal (DE); The fourth differential signal transmission line LVL4 includes two bits of red data R12 and R13 representing information on the format of the image data for one period of the clock pulse CLK, two bits of green data G12 , G13), two bits of blue data (B12, B13), and one bit of format information (F). For example, if the image data is of the JEIDA format, the logical data of the format information can be set to '1'. If the image data is of the Video Electronics Standards Association (VESA) format, Data can be set to '0'.

Since the format information F having logical data '1' is assigned to the idle bit which is the least significant bit of the image data shown in FIG. 4A, it can be understood that the image data is formatted by the JEIDA method. In the image data formatted by this JEIDA method, the lower 2 bits of the red data, the lower 2 bits of the green data, and the lower 2 bits of the blue data contained in the image data are transmitted through the fourth differential signal transmission line LVL4 do.

On the other hand, FIG. 4B shows that image data including 8 bits of red, green, and blue data is formatted and transmitted in the VESA format. As shown in FIG. 4B, the least significant bits of the image data, Since format information having data '0' is allocated, it can be understood that this image data is formatted in the VESA format. In the image data formatted by the VESA method, the upper 2 bits of the red data, the upper 2 bits of the green data, and the upper 2 bits of the blue data included in the image data are transmitted through the fourth differential signal transmission line LVL4 .

Although the four differential signal transmission lines LVL1 to LVL4 are illustrated in FIGS. 2, 3, 4A and 4B, the number of the differential signal transmission lines LVL1 to LVL4 is not limited thereto. Or may be five or more, depending on the bits of red, green, and blue data included in the image data.

5A is a diagram showing that image data including 10-bit red, green, and blue data is formatted and transmitted in the JEIDA format.

As shown in Fig. 5A, the image data includes a 1-bit data enable signal DE, a 1-bit vertical synchronizing signal Vsync, a 1-bit horizontal synchronizing signal Hsync, R19), 10 bits of green data (G10 to G19), and 10 bits of blue data (B10 to B19).

The plurality of differential signal transmission lines are composed of five, and each differential signal transmission line transmits data by 7 bits during one period of a clock pulse (CLK).

At this time, the first differential signal transmission line LVL1 sequentially transmits 6 bits of red data (R14 to R19) and 1 bit of green data (G14) during one period of the clock pulse (CLK); The second differential signal transmission line LVL2 sequentially transmits 5 bits of green data G15 to G19 and 2 bits of blue data B14 and B15 for one period of the clock pulse CLK; The third differential signal transmission line LVL3 outputs 4 bits of blue data B16 to B19, 1 bit of a horizontal synchronization signal Hsync, 1 bit of a vertical synchronization signal Vsync, , And a 1-bit data enable signal (DE); The fourth differential signal transmission line LVL4 outputs two bits of red data R12 and R13, two bits of green data G12 and G13 and two bits of blue data B12 and G13 for one period of the clock pulse CLK. B13) and 1-bit format information (F) indicating information on the format of the image data; The fifth transmission line receives two bits of red data R10 and R11, two bits of green data G10 and G11, two bits of blue data B10 and B11, and two bits of blue data B10 and B11 for one period of the clock pulse CLK. And one bit of the idle bit (X) in order. For example, if the image data is of the JEIDA format, the logical data of the format information F can be set to '1'. If the image data is of the Video Electronics Standards Association (VESA) format, The logical data of the information F can be set to '0'.

Since the format information having logical data '1' is allocated to the idle bit of the image data shown in FIG. 5A, it can be understood that the image data is formatted by the JEIDA method. The image data formatted by this JEIDA method includes the lower 4 bits (R16 to R19) of the red data included in the image data, the lower 4 bits (G16 to G19) of the green data, and the lower 4 bits (B16 to B19 Are transmitted through the fourth and fifth differential signal transmission lines LVL4 and LVL5.

On the other hand, FIG. 5B shows that image data including 10-bit red, green, and blue data is formatted and transmitted in the VESA format. As shown in FIG. 5B, Is assigned to the image data, it can be understood that the image data is formatted by the VESA method. The image data formatted by this VESA method is transmitted through the fourth and fifth differential signal transmission lines with the upper 4 bits of the red data, the upper 4 bits of the green data, and the upper 4 bits of the blue data included in this image data .

5A and 5B have two idle bits, one idle bit is assigned the above-described format information F, and the other idle bit X is assigned to Don Care It remains as a do not care bit. Other information may be assigned to this remaining idle bit (X).

The image data to which the format information F is assigned by the system 55 is supplied to the timing controller 12 through the interface unit 60. The timing controller 12 converts the format information of the image data (F), thereby automatically recognizing the format format of the image data, and formatting and outputting image data in accordance with this format format.

On the other hand, when there is no idle bit in the image data inputted to the system 55, the system 55 supplies the image data in which the idle bit does not exist to the timing controller 12 and also displays information about the format of the image data And supplies a format information signal to the timing controller 12. That is, the format information signal is supplied to the timing controller 12 through any one of the pins of the connector connecting the system 55 and the timing controller 12. [ The timing controller 12 formats and outputs the image data in which the idle bit does not exist in accordance with the format information signal.

6 is a flowchart illustrating a method of driving a display device according to an embodiment of the present invention.

First, the system 55 confirms whether idle data exists in the image data input to the system 55 (S1). This is possible by confirming that the system 55 is transmitting image data over a D pair line. That is, the first to fifth differential signal transmission lines LVL1 to LVL5 are defined as an A pair line, a B pair line, a C pair line, a D pair line, and an E pair line, That is, when four or more differential signal lines are used, idle bits may exist in this image data. On the other hand, when this image data uses less than or equal to the C pair line, that is, three or less differential signal lines, there can be no idle bit in this image data.

If this picture data is using a line of D pairs or more, format information is allocated in the 7th, that is, the least significant bit of the 7 bits of data transmitted through this D pair line. This format information indicates the JEIDA scheme or the VESA scheme.

The timing controller 12 confirms the format information F of the image data and automatically recognizes the format of the image data (S2). If the logical data of the format information F is '1', the timing controller 12 formats and outputs the image data in the JEIDA format. (S3) On the other hand, 0 ", the image data is formatted and output by the VESA method (S2-1).

On the other hand, if it is determined in step S1 that the image data does not use lines of D pairs or more, a format information signal indicating the format information of the image data is input to the pins of the connector. If the image data is formatted according to the JEIDA method, the logical data of the format information signal becomes '1'. If the image data is formatted by the VESA method, the logical data of the format information signal becomes '0'. The format information signal is supplied to the timing controller 12 through the pin of the connector. The timing controller 12 recognizes the format of the image data based on the logical data of the format information signal, and formats and outputs the image data according to the recognized result.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

1 is a view showing a display device according to an embodiment of the present invention;

2 is a diagram for explaining an image data transmission method between the timing controller and the system of FIG. 1; FIG.

3 is a detailed configuration diagram of the interface unit of Fig.

4A is a diagram showing that image data including 8-bit red, green, and blue data is formatted and transmitted in a JEIDA manner

4B is a diagram showing that image data including 8-bit red, green and blue data is formatted and transmitted in the VESA format

5A is a diagram illustrating that image data including 10-bit red, green, and blue data is formatted and transmitted in the JEIDA format

5B is a diagram showing that image data including 10-bit red, green, and blue data is formatted and transmitted in the VESA format

6 is a flowchart showing a driving method of a display apparatus according to an embodiment of the present invention.

Claims (7)

It is checked whether there are idle bits in the image data by checking the number of differential signal transmission lines used for transmission of the image data among a plurality of differential signal transmission lines at the time of image data transmission and if there is an idle bit in the image data A system for assigning information on a format scheme of the image data to unused idle bits among the bits constituting the image data to the idle bit and outputting image data including the format information; And Receiving image data from the system through the differential signal transmission lines, recognizing format information assigned to idle bits of the image data, recognizing a formatting method of the image data, and displaying the image data in a format And outputting the timing control signal to the timing controller. The method according to claim 1, When there is no idle bit in the image data, the system supplies image data in which the idle bit does not exist to the timing controller, and supplies a format information signal indicating information on the format of the image data to the timing controller ; And, Wherein the timing controller formats and outputs image data in which the idle bit does not exist according to the format information signal. The method according to claim 1, Wherein the system and the timing controller transmit and receive the image data through an interface unit of a low voltage differential signal (LVDS) system. The method of claim 3, The interface unit includes: An LVDS transmitter for outputting image data in the form of a TTL (Transistor Transistor Logic) signal input from the system in the form of an LVDS signal; A plurality of differential signal transmission lines for transmitting image data in the form of an LVDS signal from the LVDS transmission unit; And And an LVDS receiver for restoring, in the form of a TTL signal, image data in the form of an LVDS signal input from the differential signal transmission lines. 5. The method of claim 4, Wherein the image data includes a 1-bit data enable signal, a 1-bit vertical synchronizing signal, a 1-bit horizontal synchronizing signal, 8-bit red data, 8-bit green data, and 8-bit blue data; The plurality of differential signal transmission lines are composed of four; Each differential signal transmission line transmits data by 7 bits during one period of a clock pulse; The first differential signal transmission line sequentially transmits 6 bits of red data and 1 bit of green data for one period of the clock pulse; The second differential signal transmission line sequentially transmits 5 bits of green data and 2 bits of blue data for one period of the clock pulse; The third differential signal transmission line sequentially transmits 4 bits of blue data, 1 bit of a horizontal synchronizing signal, 1 bit of a vertical synchronizing signal, and 1 bit of a data enable signal in one cycle of the clock pulse; And, The fourth differential signal transmission line sequentially transmits 2-bit red data, 2-bit green data, 2-bit blue data, and 1-bit format information indicating information on the format of the image data for one period of the clock pulse / RTI > 5. The method of claim 4, Wherein the image data includes a 1-bit data enable signal, a 1-bit vertical synchronizing signal, a 1-bit horizontal synchronizing signal, 10-bit red data, 10-bit green data, and 10-bit blue data; The plurality of differential signal transmission lines are composed of five; Each differential signal transmission line transmits data by 7 bits during one period of a clock pulse; The first differential signal transmission line sequentially transmits 6 bits of red data and 1 bit of green data for one period of the clock pulse; The second differential signal transmission line sequentially transmits 5 bits of green data and 2 bits of blue data for one period of the clock pulse; The third differential signal transmission line sequentially transmits 4 bits of blue data, 1 bit of a horizontal synchronizing signal, 1 bit of a vertical synchronizing signal, and 1 bit of a data enable signal in one cycle of the clock pulse; The fourth differential signal transmission line sequentially outputs 2-bit red data, 2-bit green data, 2-bit blue data, and 1-bit format information indicating information on the format of the image data for one period of the clock pulse Transmit; And, The fifth differential signal transmission line sequentially transmits 2 bits of red data, 2 bits of green data, 2 bits of blue data, and 1 bit of idle bits in one cycle of the clock pulse. The method according to any one of claims 5 and 6, The format information is any one of logical data '1' and '0'; If this image data is of the Japanese Electronics Industry Development Association (JEIDA) format, the logical data of the format information is '1'; And, And the logical data of the format information is '0' when the image data is of a Video Electronics Standards Association (VESA) format.

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