KR101571133B1 - Coincidence counter and method for counting coincidence - Google Patents

Abstract

A coincidence counter comprises: a pulse width control unit for controlling a pulse width included in a first input signal; a coincidence signal generator for generating a signal representing coincidence of the pulse with the controlled width included in the first input signal, and a pulse included in a second input signal; and a counter for counting the number of pulse included in the generated signal representing the coincidence. The pulse width control unit includes a rising edge detection unit for detecting a rising edge of the pulse included in the first input signal.

Description

[0001] COUNTERENCE COUNTER AND METHOD FOR COUNTING COINCIDENCE [0002]

Embodiments relate to a coincidence counter and coincidence counting method for counting the simultaneous generation of a plurality of signals, and more particularly to a technique for reducing the coincidence counting time window.

A coincidence counting unit (CCU) is a module for counting the coincidence of a plurality of input signals, including an optical experiment for counting the coincidence between a plurality of single-photon detectors and a quantum cryptography system It is used in various fields. For example, the measurement-device-independent quantum key distribution (MDI-QKD), which is not related to the recently proposed measuring instrument, can also be used to detect bell measurements (two-fold simultaneous detection between four single photon detectors Bell measurement.

In a coincidence counter, a coincidence time window is defined as the maximum time interval during which the occurrence of a plurality of signals is detected as a coincidence, and is generally defined as a sum of pulse widths included in signals to be simultaneously measured do. If simultaneous counting is used in optical or quantum information experiments, the longer the coincidence counting time window is, the higher the probability that the noise will be measured and the accidental coincidence counts are increased and the performance of the coincidence counter is degraded. That is, the simultaneous counting time window is a very important factor determining the performance of the coincidence counter.

As a method for implementing the coincidence counter, time-to-amplitude converters (TACs) can be used. In general, a time-to-amplitude converter can have a resolution of a few ps (picoseconds), but this method is expensive and takes up a lot of volume.

Another way to implement the coincidence counter is to use a digital gate chip. Recently, PLD (Programmable Logic Device) and ECL (Emitter-Coupled Logic) technologies have been used to implement a high-performance co-counter. As a method of using a digital gate chip, lt; RTI ID = 0.0 > nanoseconds < / RTI > However, digital gate chips require high power dissipation, difficulty in resetting the inputs, and adjustable external delay generators because the internal delays are generally fixed.

On the other hand, when a simultaneous counter is implemented using a field programmable gate array (FPGA), it is possible to easily implement a simultaneous counter at a relatively low cost. Conventional simultaneous counters using FPGAs are using simultaneous counting time windows of several ns using the AND gate of the FPGA. However, in order to realize the simultaneous counting time window in units of ns, a method of reducing the simultaneous counting time window using a low-cost FPGA and requiring an expensive FPGA is required.

D. Branning, S. Khanal, Y. H. Shin, B. Clary and M. Beck, "Scalable Multiphoton Coincidence-Counting Electronics ", Rev. Sci. Instrum. 82, 016102 (2011)

According to an aspect of the present invention, it is possible to provide a high performance synchronous counter having a simultaneous counting time window of 1 ns or less by using a low-cost Field Programmable Gate Array (FPGA).

Further, according to an aspect of the present invention, it is possible to provide a coincidence counter that does not require an auxiliary delay generator by delaying each input signal inside the coincidence counter.

A coincidence counter according to an embodiment of the present invention includes a pulse width controller for controlling a width of a pulse included in a first input signal; A simultaneous generation signal generator for generating a signal indicating the simultaneous generation of the pulse included in the first input signal whose width is controlled and the pulse included in the second input signal; And a counter for counting the number of pulses included in the generated signal indicating the coincidence, wherein the pulse width controller includes a rising edge detector for detecting a rising edge of the pulse included in the first input signal .

According to another aspect of the present invention, there is provided a coincidence counting method comprising: controlling a width of a pulse included in a first input signal; Generating a signal indicating a simultaneous generation of the pulse included in the first input signal whose width is controlled and the pulse included in the second input signal; And counting the number of pulses included in the signal indicating the generated coincidence, wherein the step of controlling the width of the pulse included in the first input signal comprises: And detecting the rising edge and outputting the first rising edge detection signal.

According to one aspect of the present invention, the simultaneous counting method or the coincidence counting method can increase the accuracy of the coincidence coefficient by obtaining a simultaneous counting time window of 1 ns or less using a low-cost FPGA (Field Programmable Gate Array) have.

Further, according to the simultaneous counting or coincidence counting method according to one aspect of the present invention, an input signal can be delayed without an external delay generator.

1 is a block diagram schematically illustrating an internal structure of a coincidence counter according to an embodiment of the present invention.
FIGS. 2A and 2B are block diagrams schematically illustrating an internal structure of a pulse width control unit of a coincidence counter according to embodiments of the present invention.
3 is a graph exemplarily showing signal waveforms at respective nodes of the pulse width control unit of the coincidence counter of FIG. 2B.
4 schematically shows the internal structure of the pulse width control unit and the co-generated signal generation unit of the coincidence counter according to the embodiment of the present invention.
5 is a graph showing the coincidence count time window of the coincidence counter according to the number of delay buffers operating in the pulse width controller according to an embodiment of the present invention.
6 is a block diagram schematically illustrating an internal structure of a coincidence counter according to an embodiment of the present invention.
7 is a block diagram schematically illustrating a connection relationship between a coincidence counter and a user terminal according to an embodiment of the present invention.
8 is a graphical user interface (GUI) program screen for controlling the coincidence counter according to an embodiment of the present invention.
9A-9C are flow charts of a coincidence counting method in accordance with embodiments of the present invention.
10 is a flowchart of a coincidence counting method according to an embodiment of the present invention.
11 is a graph showing results of simultaneous counting of the coincidence counter according to the frequency of an input signal according to an embodiment of the present invention.
12 is a graph showing a simultaneous counting time window of a coincidence counter according to embodiments of the present invention, according to a delay between two input signals.
13 is a graph showing the results of an optical experiment using a coincidence counter according to embodiments of the present invention, according to the coincidence counting time window.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Where similar reference numerals are used in the several figures, like reference numerals refer to the same or similar functions for various embodiments.

The coincidence counter detects when a plurality of signals occur within a coincidence counting time window, that is, within a constant time interval, and counts the number of coincidences that occur during a predetermined duration. 1 is a block diagram schematically illustrating an internal structure of a coincidence counter according to an embodiment of the present invention. In one embodiment, the coincidence counter 100 includes a pulse width controller 110, a coincidence signal generator 120, and a counter 130, wherein the pulse width controller 110 receives the input signal S _in And a rising edge detector 210 for detecting a rising edge of a pulse. The rising edge detector 210 may be implemented using an FPGA (Field Programmable Gate Array).

The input signal S _in including the pulse is transmitted to the pulse width control unit 110 to control the width of the pulse and the input signal whose pulse width is controlled is transmitted to the coincidence signal generator 120. The width of the pulse can be controlled according to the user's input through the user interface (UI). The coincidence signal generator 120 receives a control signal having a controlled pulse width and another input signal and outputs a signal indicating whether a pulse included in the received plurality of signals occurs within a coincidence counting time window having a predetermined time interval And transmits the generated signal to the counter 130. The counter 130 counts the pulses included in the signal received from the coincidence signal generator 120.

The pulse width control unit 110 may be arranged such that the output is delivered to the co-occurrence signal generator as shown in FIG. 1, and may control the width of the pulse included in the input signal, do.

The rising edge detection unit 210 detects a rising edge of the input signal S _in and generates a first rising edge detection signal having a rising edge or a falling edge at the same time as the rising edge do. The coincidence counter 100 includes the rising edge detector 210 in the pulse width controller 110, so that it is resistant to noise in pulse width control and can generate a wide range of simultaneous count pulse widths.

FIGS. 2A and 2B are block diagrams schematically illustrating an internal structure of a pulse width control unit of a coincidence counter according to embodiments of the present invention.

As shown in FIG. 2A, the pulse width controller 110 may include a rising edge detector 210 and a pulse delay unit 220.

The pulse delay unit 220 generates a second rising edge detection signal by delaying the input first rising edge detection signal by a predetermined time. At this time, the pulse delay unit 220 may delay the first rising edge detection signal by a time shorter than the width of the pulse included in the first rising edge detection signal. Accordingly, by forming the first rising edge detection signal and the second rising edge detection signal having a high section simultaneously for a predetermined time, the pulse width of the input signal is controlled using the first and second rising edge detection signals can do.

2B, the pulse width control unit 110 may further include an EX-OR operation unit 230. The EX- The EX-OR operation unit 230 receives the first rising edge detection signal and the second rising edge detection signal and performs an EX-OR operation on the first rising edge detection signal and the second rising edge detection signal, S _in ) and finally outputs a signal whose pulse width is controlled.

FIG. 3 is a graph exemplarily showing signal waveforms at respective nodes of the pulse width control unit of the coincidence counter of FIG. 2B, and the horizontal axis represents time (sec). The signal S _in (FIG. 2B) input to the pulse width controller 110 (FIG. 2B) shows the same waveform as the signal S ₁ . Signal (S ₁₎ is a rising edge detector for; (Figure 2b 210) has a first rising edge detection signal (S ₂₎ indicating the rising edge of the signal (S ₁₎ is transmitted to the (210 Fig. 2b), the rising edge detector Output. For example, as illustrated in Figure 3, the rising edge detector 210 (Fig. 2b) are the input signal (S ₁₎ 2n in the (n = 0, 1, 2 , ...) falling to a rising edge occurs when the second detection The first rising edge detection signal S ₂ can be generated so as to have the rising edge at the rising edge occurrence time having the (2n + 1) th detected edge. The signal S ₂ is input to the pulse delay unit 220 (FIG. 2B) and the pulse delay unit 220 (FIG. 2B) delays the first rising edge detection signal S ₂ to generate the second rising edge detection signal S ₃ ). The EX-OR operation unit 230 (FIG. 2B) outputs the signal S ₄ by performing an EX-OR operation on the first rising edge detection signal S ₂ and the second rising edge detection signal S ₃ . Comparing the signal S ₁ with the signal S ₄ , it can be seen that the width of the pulse is reduced with the rising edge at the same time.

4 schematically shows the internal structure of the pulse width control unit and the co-generated signal generation unit of the coincidence counter according to the embodiment of the present invention. The rising edge detection unit 210 (FIG. 1) and the EX-OR operation unit 230 (FIG. 2B) may include a flip flop 410 and an EX-OR gate 430, respectively. In addition, the pulse delay unit 220 (FIG. 2A) may include a delay buffer 420a and / or a MUX 420b. Meanwhile, the coincidence signal generator 120 may include an AND gate 440.

4, the input signal input from the signal channel CH1 is transmitted to the EX-OR gate 430 and the delay buffer 420a via the flip-flop 410. At this time, The input signal to be input may be a TTL type input. Flip-flop 410 may be a JK flip-flop, an RS flip-flop, a T flip-flop, or a D flip-flop and detects the rising edge of the input signal.

The rising edge detection signal from the flip flop 410 is transferred to the delay buffer 420a and the MUX 420b can determine the number of the delay buffers 420a that operate to delay the rising edge detection signal. The user input for the coincidence count time window value or the amount of delay of the rising edge detection signal is transmitted to the MUX 420b via an input pin and the amount of delay of the rising edge detection signal capable of determining the pulse width of the input signal is Since it is controlled in accordance with the number of the operating delay buffers 420a, the EX-OR gate 430 can generate a width-controlled pulse according to the user's input in real time.

The EX-OR gate 430 performs an EX-OR operation on the two received signals to generate an output signal, and transmits the generated output signal to the AND gate 440. In one embodiment, the output of the pulse width controller 110 may be directly input to the AND gate 440 of the co-occurrence signal generator 120, thereby minimizing the delay difference of the signals transmitted on different paths .

The AND gate 440 in the coincidence signal generation unit 120 receives the output signal of the pulse width control unit 110 and other signals and performs an AND operation on the received plurality of signals, And outputs a signal indicative of occurrence. For example, a signal indicating coincidence is held high in a period in which a plurality of signals are simultaneously generated, and held in a low period in a period in which a plurality of signals are not simultaneously generated. The coincidence signal generating unit 120 may output a signal having the same number of pulses as the number of coincidence of a plurality of inputted signals. The internal structure and operation of the counter 130 (FIG. 1) for counting the number of pulses included in the signal indicative of simultaneous generation are known in the art, so a detailed description will be omitted.

5 is a graph showing the coincidence count time window of the coincidence counter according to the number of delay buffers operating in the pulse width controller according to an embodiment of the present invention. Referring to FIG. 5, as the number of delay buffers for delaying the first rising edge detection signal increases, the simultaneous counting time window also increases. That is, the controlled pulse width or coincidence counting time window of the input signal has a linear relationship with the number of delay buffers.

6 is a block diagram schematically illustrating an internal structure of a coincidence counter according to an embodiment of the present invention. The coincidence counter 600 may further include an input signal delay unit 640 as well as a pulse width control unit 610, a coincidence signal generator 620 and a counter 630. 6, the input signal delay unit 640 may be arranged to delay the input signal S _in by a predetermined time, and to deliver the delayed input signal to the pulse width control unit 610.

An input signal delay unit 640 is the input signal (S _in) the may include a delay buffer and a multiplexer (not shown) in order to delay, and an amount (i. E., Time) for delaying the input signal (S _in) is a user interface Lt; / RTI > For example, when the user wants to observe the simultaneous occurrence of the input signal and the delayed input signal, if the user inputs a time to delay through the user interface, the multiplexer outputs a delay buffer It is possible to add a delay to one input signal.

7 is a block diagram schematically illustrating a connection relationship between a coincidence counter and a user terminal according to an embodiment of the present invention. The input signal is input from the plurality of input channels CH1, CH2, ..., and CH8 and the operation process of the input signal delay unit 740, the pulse width control unit 710, and the concurrent generation signal generator 720 is as described above The description is omitted. The counter 730 counts the number of pulses included in the signal indicating concurrent occurrence received from the coincidence signal generator 720 and outputs the counted number of pulses to the processor 750 when the timer 750 triggers the information upload signal. RTI ID = 0.0 > 760 < / RTI > The processor 760 transmits the count information to the user's PC 780 via a USB (Universal Serial Bus) -serial board 770. The user can confirm the counted information through the user interface on the PC 780 or the like.

7, in one embodiment, the co-occurring signal generator 720 may include a multiplexer (MUX), which is coupled to an AND gate to receive an input signal via a select pin And thus can determine the signals to be counted for coincidence.

8 is a graphical user interface (GUI) program screen for controlling the coincidence counter according to an embodiment of the present invention. The user inputs an input delay step for delaying the input signal in the input signal delay unit through the GUI, a coincidence count time window value (Time (k)) to be obtained by controlling the pulse width of the input signal through the pulse width control unit window step and a data upload period for measuring the coincidence can be inputted and the pulse count value (single counts) for each input signal and the You can see the coincidence counts. The coincidence counter according to an exemplary embodiment may delay an input signal by a user input to an input signal delay amount or correspond to a user input value for a coincidence window Can be controlled by the pulse width.

9A-9C are flow charts of a coincidence counting method in accordance with embodiments of the present invention. 9A, a coincidence counting method includes controlling 910 the width of a pulse included in a first input signal, comparing the pulse included in the first input signal with a width controlled and the second input signal (920) generating a signal indicative of the coincidence of the pulses included in the first input signal, and counting (930) the number of pulses included in the signal indicative of the concurrent occurrence generated, The step 910 of controlling the width of the included pulse may include the step 910a of detecting the rising edge of the pulse included in the first input signal and outputting the first rising edge detection signal.

9B, in one embodiment, controlling 910 the width of the pulse included in the first input signal may include outputting a second rising edge detection signal by delaying the first rising edge detection signal (Step 910b), and further includes performing (910c) an EX-OR operation on the first rising edge detection signal and the second rising edge detection signal, as shown in FIG. 9c It is possible.

Further, in one embodiment, controlling (910) the width of the pulse included in the first input signal comprises receiving a user input related to the width of the pulse and controlling the width of the pulse included in the first input signal And controlling the width of the pulse. Thus, the width of the pulse can be controlled in real time according to user input.

10 is a flowchart of a coincidence counting method according to an embodiment of the present invention. The coincidence counting method may further include delaying (940) the first input signal by a predetermined time before controlling (910) the width of the pulse included in the first input signal. The step 940 of delaying the first input signal by a predetermined amount of time also includes receiving a user input for a predetermined time and delaying the first input signal according to a user input for a predetermined time can do.

11 is a graph showing results of simultaneous counting of the coincidence counter according to the frequency of an input signal according to an embodiment of the present invention. The same input signal was applied to the two input ports of the coincidence counter, the input frequency was gradually increased, and the frequency of coincidence was measured. Herein, the input frequency means the frequency of the pulse included in the input signal. The coincidence count time window was set to about 1 ns. Referring to FIG. 11, it can be seen that the coincidence counts at the input frequencies of less than about 163 MHz are accurately counted simultaneously, while the counts at the input frequencies of about 163 MHz or more are reduced sharply. This is because the operating speed of the FPGA used in the experiment is limited by the hardware performance. When using the higher-level FPGA with higher operating speed, it is possible to extend the range of the input frequency at which the coincidence coefficient is accurately made.

12 is a graph showing a simultaneous counting time window of a coincidence counter according to embodiments of the present invention, according to a delay between two input signals. We set two arbitrary pulses as an input signal through a pulse generator and measured the simultaneous counting time window when one pulse was delayed. At this time, the simultaneous counting time window can be defined as a time delay of two input signals when the coincidence probability is 0.5. In the experiments, the pulse width controller controlled the input signal with three different pulse widths, with the widest pulse width for the graph shown in black and the narrowest pulse width for the graph shown in red. As shown in FIG. 12, the narrower the pulse width is, the shorter the simultaneous counting time window is obtained, and the 0.70 ns simultaneous counting time window is obtained when the pulse width is controlled to be the narrowest (red).

13 is a graph showing the results of an optical experiment using a coincidence counter according to embodiments of the present invention, according to the coincidence counting time window. This optical experiment is an experiment to confirm the accidental coincidence. It adjusts the light intensity of the light source and sets the output signal of the Avalanche Photo Diode (APD) as the input signal of the coincidence counter, The coefficients were processed. A line graph shown by a solid line in FIG. 13 represents a theoretical value, and a point graph shown by a point such as a triangle, a square, or a circle represents a measured value. Referring to FIG. 13, it can be seen that the coincidence counter according to embodiments of the present invention counts coincidence similar to the theoretical value. (Tc = 7.18 ns, Tc = 13.2 ns), the error was generated from the theoretical value when the pulse width was controlled to be wide (Tc = 13.2 ns) as compared with the case where the pulse width was controlled to be the shortest This is because the rise or fall time of the rising or falling edge of the pulse is not zero.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments or constructions. .

100: coincidence counter 110: pulse width control unit
120: Synchronization signal generator 130: Counter
210: rising edge detector

Claims (20)

A pulse width controller for controlling a width of a pulse included in the first input signal;
A simultaneous generation signal generator for generating a signal indicating the simultaneous generation of the pulse included in the first input signal whose width is controlled and the pulse included in the second input signal; And
And a counter for counting the number of pulses included in the signal indicating the generated coincidence,
Wherein the pulse width control unit includes a rising edge detecting unit for detecting a rising edge of a pulse included in the first input signal. The method according to claim 1,
Wherein the rising edge detector comprises a flip-flop. The method according to claim 1,
Wherein the pulse width control unit controls the width of the pulse included in the first input signal according to a user input related to a width of the pulse included in the first input signal. The method of claim 3,
Wherein the pulse width control unit comprises a multiplexer (MUX). The method according to claim 1,
Wherein the pulse width control unit further comprises a pulse delay unit for delaying the output signal of the rising edge detection unit. 6. The method of claim 5,
Wherein the pulse delay unit comprises a delay buffer. The method according to claim 6,
Wherein the pulse width controller controls the width of the pulse included in the first input signal according to the number of the delay buffers. 6. The method of claim 5,
Wherein the pulse width control unit further comprises an EX-OR operation unit for performing an EX-OR operation on the output signal of the rising edge detector and the output signal of the pulse delay unit. The method according to claim 1,
Further comprising an input signal delay unit for delaying the first input signal by a predetermined time and transmitting the delayed first input signal to the pulse width control unit. 10. The method of claim 9,
Wherein the input signal delay unit delays the first input signal according to a user input for the predetermined time. 10. The method of claim 9,
Wherein the input signal delay unit comprises a delay buffer and a multiplexer. The method according to claim 1,
RTI ID = 0.0 > 1, < / RTI > wherein the coincidence signal generator comprises a multiplexer. The method according to claim 1,
Wherein the coincidence signal generator comprises an AND gate,
And the output signal of the pulse width control unit is directly input to the AND gate. Controlling a width of a pulse included in the first input signal;
Generating a signal indicating a simultaneous generation of the pulse included in the first input signal whose width is controlled and the pulse included in the second input signal; And
Counting the number of pulses included in the signal indicating the generated coincidence,
Wherein controlling the width of the pulse included in the first input signal includes detecting a rising edge of a pulse included in the first input signal and outputting a first rising edge detection signal. Counting method. 15. The method of claim 14,
Wherein controlling the width of the pulse included in the first input signal comprises:
Receiving a user input associated with a width of a pulse included in the first input signal; And
And controlling the width of the pulse included in the first input signal according to the received user input. 15. The method of claim 14,
Wherein controlling the width of the pulse included in the first input signal further comprises outputting a second rising edge detection signal by delaying the first rising edge detection signal. 17. The method of claim 16,
The step of outputting the second rising edge detection signal by delaying the first rising edge detection signal includes delaying the first rising edge detection signal by a time shorter than the width of the pulse included in the first rising edge detection signal Characterized by a coincidence counting method. 17. The method of claim 16,
Wherein controlling the width of the pulse included in the first input signal further comprises performing an EX-OR operation on the first rising edge detection signal and the second rising edge detection signal. Generation coefficient method. 15. The method of claim 14,
Before the step of controlling the width of the pulse included in the first input signal,
Further comprising delaying the first input signal by a predetermined time. 20. The method of claim 19,
Wherein the step of delaying the first input signal by a predetermined time comprises:
Receiving user input for the predetermined time; And
And delaying the first input signal according to the user input.

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