KR101546425B1 - Electrophoretic display device and method of fabricating the same - Google Patents

Abstract

A gate wiring and a data wiring which are formed by defining a plurality of pixel regions crossing each other in the display region on a substrate on which a non-display region around the display region is defined; A gate and a data link wiring formed in the non-display area and connected to the gate and the data wiring; A thin film transistor composed of the gate electrode, the gate insulating film, the semiconductor layer, and the source and drain electrodes spaced apart from each other in a stacked manner in each of the plurality of pixel regions; First and second storage electrodes formed in the plurality of pixel regions and formed under and over the gate insulating layer to form a storage capacitor together with the gate insulating layer; A first passivation layer covering the thin film transistor and the storage capacitor and having a drain contact hole having a first thickness as an organic insulating material in the display region and exposing the drain electrode; A buffer layer formed of the same material as the first protective layer and having the same thickness and having a first width in the non-display region; A pixel electrode formed in each of the pixel regions in contact with the drain electrode of the thin film transistor through the drain contact hole on the first protective layer in the display region; And an electrophoretic film having one end on the buffer layer and corresponding to the entire display region over the pixel electrode, and a method of manufacturing the electrophoretic display.

Electrophoretic display, CREC, laminating, EPD, short

Description

[0001] Electrophoretic display device and method for fabricating the same [0002]

The present invention relates to an electrophoretic display device, and more particularly, to an electrophoretic display device capable of preventing occurrence of a crack in a link wiring or a driving device electrode in a non-display area of an array substrate when an electrophoretic film is attached, .

2. Description of the Related Art In general, a liquid crystal display, a plasma display, and an organic electric field display have become mainstream in display devices. However, recently, various types of display devices have been introduced to meet the rapidly diversifying consumer needs.

Especially, it is accelerating the implementation of lightweight, thin, high efficiency, and full color video by enhancing the information utilization environment and portability. As a result, studies on electrophoretic display devices that merely combine the merits of paper and conventional display devices have been actively conducted.

The electrophoretic display device is attracting attention as a next generation display device which has advantages of excellent contrast ratio, visibility, fast response speed, display of natural color, low cost and easy portability.

In addition, the electrophoretic display device does not require a polarizing plate, a backlight unit, a liquid crystal layer, and the like, unlike the liquid crystal display device.

Hereinafter, a conventional electrophoretic display device will be described with reference to the accompanying drawings.

1 is a diagram schematically showing the structure of the electrophoretic display device for explaining the driving principle thereof.

1, the conventional electrophoretic display device 1 includes first and second substrates 11 and 36 and an ink layer 57 interposed between the first and second substrates 11 and 36 . The ink layer 57 includes a plurality of capsules 63 filled with a plurality of white pigments 59 and black pigments 61 charged through a condensation polymerization reaction.

A plurality of pixel electrodes 28 connected to a plurality of thin film transistors (not shown) are formed on the first substrate 11 for each pixel region (not shown). That is, the plurality of pixel electrodes 28 are selectively supplied with a positive voltage or a negative voltage. At this time, when the sizes of the capsules 63 including the white pigment 59 and the black pigment 61 are not constant, only capsules 63 of a predetermined size can be selectively used.

When a voltage having a positive polarity or a negative polarity is applied to the ink layer 57, the charged white pigment and the black pigment 59, 61 in the capsule 63 are attracted toward the opposite polarity . That is, when the black pigment 61 moves upward, black is displayed, and when the white pigment 59 moves upward, white is displayed.

Hereinafter, a conventional electrophoretic display device will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view schematically showing an electrophoretic display device according to the related art, wherein the same reference numerals are used for the same names as in Fig.

As shown in the figure, the electrophoretic display device 1 according to the related art includes first and second substrates 11 and 36 which are adhered to each other, and electrophoresis (electrophoresis) sandwiched between the first and second substrates 11 and 36 Film (60). The electrophoretic film 60 includes an ink layer 57 including a plurality of capsules 63 filled with a plurality of black pigments 61 and white pigments 59 charged through a condensation polymerization reaction, (51, 53) made of a transparent material and a common electrode (55) made of a transparent conductive material between the first and second adhesive layers (51, 53). At this time, the black pigment 61 is charged with (+) polarity and the white pigment 59 is charged with (-) polarity.

The second substrate 36 is made of a transparent plastic material or glass. The first substrate 11 is made of an opaque stainless material. If necessary, a transparent plastic material or a transparent glass material is used .

At this time, a color filter layer 40 composed of red, green, and blue color filter patterns is formed on the lower front surface of the second substrate 36.

On the other hand, a gate wiring (not shown) and a data wiring (not shown) are formed on the first substrate 11 so as to define a pixel region P in a matrix form and the gate wiring (not shown) A thin film transistor Tr, which is a switching element, is formed for each pixel region P at the intersection of wirings (not shown).

The thin film transistor Tr includes a gate electrode 14 extending from a gate wiring (not shown), a gate insulating film 16 covering the gate electrode 14, and an active layer A source electrode 20 which is in contact with the semiconductor layer 18 and extends in a data line (not shown), a source electrode 20 which is in contact with the semiconductor layer 18, And a drain electrode 22 spaced apart.

A protective layer 26 including a drain contact hole 27 exposing the drain electrode 22 is formed on the entire surface of the display region.

A pixel electrode 28 connected to the drain electrode 22 through the drain contact hole 27 is formed on the passivation layer 26 to correspond to each pixel region P. [ The pixel electrode 28 is mainly composed of a transparent conductive material such as indium-tin-oxide (ITO) and indium-zinc-oxide (IZO).

The electrophoretic display device 1 having the above-described configuration uses external light including natural light or room light as a light source and applies a voltage to the pixels (not shown) selectively applied with (+) polarity or The electrode 28 induces a change in the positions of a plurality of white pigments 59 and black pigments 61 filled in the capsule 63 to realize an image.

The electrophoretic display device 1 having the above-described configuration can be largely manufactured by carrying out two processes. The first process is an array process for completing the array substrate 11 constituted by the pixel electrodes 28 including the thin film transistor Tr and the second process is for forming an electrophoretic film 60 on the array substrate 11 And completes the display device 1 by adhering it.

FIG. 3 is a view showing a step of laminating an electrophoretic film on an array substrate in the course of manufacturing a conventional electrophoretic display device. FIG. 4 is a sectional view of a display area and a part of a non-display area of a conventional electrophoretic display device to be.

After the array substrate 11 on which the thin film transistor Tr and the pixel electrode 28 are formed on the insulating substrate 11 is completed, the film 60 including the electrophoretic ink layer 57 is laminated for adhering The process is performed corresponding to a predetermined width of the display area DA of the array substrate 11 and the non-display area NA adjacent thereto. A thin film transistor Tr formed in the display region DA of the array substrate 11 and an external driver circuit substrate (not shown) for driving the pixel electrode 28 are formed in the non-display region NA of the array substrate 11, A gate and a data link wiring 24 for connection between the gate and data pad electrodes (not shown) and the gate and data wiring (not shown) (not shown) A common connection wiring 15 for applying a common voltage, a Vgl wiring (not shown) for applying a gate-low voltage, and a circuit (not shown) for preventing static electricity are formed.

Therefore, there is no substantial component in the non-display area NA that implements the image, and the gate and data pad electrodes (not shown) must remain exposed to connect with the external driver circuit substrate (not shown) The electrophoretic film 60 need not be attached. At this time, the electrophoretic film 60 is attached corresponding to a predetermined width of the non-display area NA adjacent to the display area DA, even if an error occurs during the laminating process, So that the electrophoretic film 60 is completely attached.

However, the gate link wiring 24 in the non-display area NA where the end where the electrophoretic film 60 starts to adhere is formed by the roll 90 (see FIG. 2) on the stage 80 when the electrophoretic film 60 is attached, Or a foreign matter or the like is adhered to the end side surface of the electrophoretic film 60 so that when the roll 90 is first contacted with the upper end of the electrophoretic film 60, A concentrated stress is applied to a portion overlapping with the foreign object, so that a crack is generated in the gate link wiring 24 or the electrode (not shown) of the driving element and the gate insulating film located under these elements In fact.

FIGS. 5A and 5B are photographs of a part of a top view of the array substrate corresponding to a position where the end of the electrophoretic film is positioned, respectively. FIG. 5A shows the state before the electrophoretic film was attached, .

5A, the gate link wiring is in a normal state before laminating the electrophoretic film. However, after the laminating process is completed, as shown in FIG. 5B, Is generated.

Referring to FIG. 4, the gate link wiring 24 in which the cracks are generated is completely cut so that the signal voltage can not be transmitted to the gate or data wiring (not shown) connected to the gate link wiring 24 Or a portion where the cracks are generated may penetrate the gate insulating film 16 located under the gate insulating film 16 to form another wiring such as a common connecting wiring 15 or a Vgl wiring Or the like, resulting in short-circuit defects, which eventually lead to a failure in driving the array substrate 11. [

The cross-sectional structure in the non-display area NA of the conventional electrophoretic display device 1 will now be described with reference to FIG. 4. In the display area DA, a relatively thick 2 to 4 The second protective layer 26 having a thickness of about 1 mu m is formed while the second protective layer 26 made of the organic insulating material is not formed in the non-display area NA.

In order to minimize defects such as cracks occurring in the gate link wiring 24 or the electrodes of the driving element, an electrostatic discharge prevention circuit (not shown) except for the gate link wiring 24 However, the design avoidance condition substantially increases the design, the process margin, or unnecessary design part. By this avoidance design, the non-display area NA is widened It is contrary to the recent trend of minimizing the width of the non-display area NA except for the display area DA. Even if this avoidance design is carried out, it is only limited to the driving elements for the antistatic circuit (not shown), and the gate link wiring 24 is formed in the non-display area NA, Design is impossible.

The present invention has been conceived to solve the above-mentioned problems, and it is an object of the present invention to provide an electrophoretic film having a buffering means for buffering an impact caused by an initial contact of a roll, It is an object of the present invention to provide an electrophoretic display device and a manufacturing method thereof that can prevent the generation of a crack or the like in a wiring or a driving element in a part.

According to another aspect of the present invention, there is provided an electrophoretic display device including a display region including a plurality of pixel regions and a non-display region surrounding the display region, A gate and a data link line formed to connect the gate and the data line to the non-display region, and a gate and a data line line formed to define a plurality of pixel regions crossing each other in the display region; A thin film transistor composed of the gate electrode, the gate insulating film, the semiconductor layer, and the source and drain electrodes spaced apart from each other in a stacked manner in each of the plurality of pixel regions; First and second storage electrodes formed in the plurality of pixel regions and formed under and over the gate insulating layer to form a storage capacitor together with the gate insulating layer; A first passivation layer covering the thin film transistor and the storage capacitor and having a drain contact hole having a first thickness as an organic insulating material in the display region and exposing the drain electrode; A buffer layer formed of the same material as the first protective layer and having the same thickness and having a first width in the non-display region; A pixel electrode formed in each of the pixel regions in contact with the drain electrode of the thin film transistor through the drain contact hole on the first protective layer in the display region; And a non-display region on the buffer electrode, one end of which is located on the buffering pattern, and an electrophoretic film attached corresponding to the entire display region.

The electrophoretic film comprises an ink layer composed of an adhesive layer in contact with the pixel electrode, a plurality of capsules filled with a large number of white pigments and black pigments charged sequentially through a condensation polymerization reaction, and a transparent conductive material And a base film.

A color filter layer including red, green and blue color filter patterns sequentially repeating on the electrophoretic film, and an opposing substrate.

And a second passivation layer between the first passivation layer and the thin film transistor as an inorganic insulating material.

A gate pad electrode connected to one end of the gate link wiring, a data pad electrode connected to one end of the data link wiring, and a thin film transistor formed in the pixel region for implementing an antistatic circuit, Is formed. In this case, a common connection wiring made of the same material is formed in the same layer as the gate wiring in the non-display area, and the gate wiring wiring crosses the common connection wiring and is formed on the gate insulation film.

The first thickness is 2 탆 to 4 탆, and the first width is 0.5 mm to 1 mm. The buffer pattern and the first passivation layer are connected to each other.

And the pixel electrode is formed in the pixel region so as to overlap the thin film transistor, the gate wiring on one side connected thereto, and the data wiring on one side.

A manufacturing method of an electrophoretic display device according to the present invention is a manufacturing method of an electrophoretic display device comprising defining a plurality of pixel regions intersecting each other on a display region composed of a plurality of pixel regions and a non- Forming a gate and a data link wiring connected to the gate and the data wiring in the non-display area; A thin film transistor formed of the gate electrode, the gate insulating film, the semiconductor layer, and the source and drain electrodes spaced apart from each other in a stacked manner in each of the plurality of pixel regions; a first storage electrode, Forming a storage capacitor having a stacked structure of electrodes; Forming a first protective layer covering the thin film transistor and the storage capacitor and having a first thickness as an organic insulating material in the display region and having a drain contact hole exposing the drain electrode, Forming a cushioning pattern having the same thickness and having a first width with the same material forming the protective layer; Forming a pixel electrode in each pixel region in the display region in contact with the drain electrode of the thin film transistor through the drain contact hole over the first passivation layer; Placing the electrophoretic film so that its one end is positioned on the buffering pattern over the pixel electrode and allowing the roll to come into contact with the end of the electrophoretic film located in the buffer pattern through a laminating device having a roll, And attaching the electrophoretic film corresponding to the non-display area where the cushioning pattern is formed and the entire display area by applying pressure.

Forming a color filter layer on the electrophoretic film, attaching a transparent counter substrate to the color filter layer, or forming a color filter layer on the counter substrate and facing the electrophoretic film.

The step of forming the buffer layer and the first passivation layer having the drain contact hole includes: forming an organic insulating material layer on the entire surface of the thin film transistor by applying an organic insulating material to the entire surface; Forming a first organic insulating layer having a second thickness greater than the first thickness and having the drain contact hole exposing the drain electrode in the display region by performing halftone exposure or diffraction exposure on the organic insulating material layer Forming a second organic insulating layer having an organic pattern of the second thickness and a third thickness thinner than the first thickness in the non-display region; Performing dry etching to remove the second organic insulating layer having the third thickness, and reducing the thickness of the first organic insulating layer and the organic pattern to the first thickness.

The first thickness is 2 탆 to 4 탆, and the first width is 0.5 mm to 1 mm.

And forming a second passivation layer on the entire surface of the thin film transistor with an inorganic insulating material before forming the first passivation layer.

Wherein the step of forming the gate and the data wiring and the gate and the data link wiring comprises the steps of: forming a gate pad electrode connected to one end of the gate link wiring in the non-display area, and a data pad electrode connected to one end of the data link wiring Wherein the forming of the thin film transistor includes forming a driving thin film transistor having the same structure as the thin film transistor formed in the pixel region in the non-display region.

And the pixel electrode is formed so as to overlap the thin film transistor, the gate wiring on one side connected to the thin film transistor, and the data wiring on one side in the pixel region.

The step of forming the gate and the data wiring and the gate and the data link wiring may include forming the gate wiring in the display region on the substrate and forming a common connection wiring in the non-display region; Forming the gate insulating film on the entire surface of the gate wiring and the common connection wiring; Patterning the gate insulating layer to form a link contact hole exposing one end of the gate wiring; Forming a data line crossing the gate line on the display region over the gate insulating film provided with the link contact hole and connecting the data line wiring and the link contact hole connected to the data line to the non- And forming the gate link wiring in contact with one end of the gate wiring and intersecting the common connection wiring.

The electrophoretic display device according to the present invention has the effect of suppressing the generation of a crack in a wiring or a drive circuit caused by an impact caused by a roll at the time of attaching the electrophoretic film in a non-display area.

It is not necessary to design a separate avoidance design for preventing the occurrence of a crack in a wiring or a driving circuit which occurs when the electrophoretic film is attached, thereby preventing an increase in the width of the non-display area.

The manufacturing method of the electrophoretic display device according to the present invention does not require any additional process for forming the means for suppressing the occurrence of the cracks in the link wiring or the drive circuit in the non-display area, There is no cost incurred.

Hereinafter, an electrophoretic display device according to the present invention will be described with reference to the accompanying drawings.

FIG. 6 is a plan view of a display region and a part of a non-display region of the electrophoretic display device according to the present invention, and FIG. 7 is a cross-sectional view of a portion taken along line VII-VII of FIG.

As shown in the figure, the electrophoretic display device 100 mainly comprises an array substrate 101 and an electrophoretic film 167 attached thereto.

The array substrate 110 includes a display region DA having a plurality of pixel regions P and a gate and a data pad portion for connecting the display region DA to an external driving circuit substrate (not shown) And a non-display area NA.

A plurality of gate and data lines 107 and 118 are formed in the display area DA to define the pixel region P with the gate insulating film 110 interposed therebetween. A gate link wiring 125 and a gate pad electrode (not shown) connected through the wiring 107 and the link contact hole 117, a data link wiring (not shown) connected to the data wiring 118 and a data pad electrode A common connection wiring 108 for applying a common voltage and a Vgl wiring 109 for applying a gate low voltage are formed in a plurality of common wiring lines 104 provided in the display area DA.

In the drawing, the common wiring 104 and the common connection wiring 108 are formed on the same layer, and the common wiring 104 and the common connection wiring 108 are formed in the form of a branch from the common connection wiring 108 in which the non-display area NA is formed. (Not shown). At this time, the common wiring 104 and the common connection wiring 108 and the gate wiring 107 are made of the same metal material in the same layer. Therefore, since the gate link wiring 125 connected to the gate wiring 107 intersects the common connection wiring 108, the common connection wiring 108 formed in the same layer as the gate wiring 107 108, in order to prevent a short circuit with the gate wiring 107 and the gate wiring 107. [ At this time, the data wiring 118 is formed on a layer different from the common connection wiring 108, so that the data link wiring (not shown) connected to the data wiring 118 does not cause a problem of short circuiting with the common connection wiring 108. Therefore, the data link wiring (not shown) is made of the same metal material on the gate insulating film 110 on which the data lines 118 are formed.

A gate electrode 103, a gate insulating film 110, and an active layer 115a of pure amorphous silicon, which are connected to the gate wiring 107 and the data wiring 118, are formed in one pixel region P, And a thin film transistor Tr which is a switching element composed of a semiconductor layer 115 composed of an ohmic contact layer 115b of impurity amorphous silicon and source and drain electrodes 120 and 122 spaced apart from each other, (Not shown in the drawing), a plurality of driving thin film transistors (not shown) having the above-described structure are formed as driving elements for realizing an antistatic circuit (not shown).

The common wiring 104 is formed in each pixel region P below the gate insulating film 110 in parallel to the gate wiring 107. The common wiring 104 is connected to the drain electrode 122 are extended so as to overlap with each other so that the overlapping common wirings 104 are connected to the first storage electrode 105 and the extended portion of the drain electrode 122 to the second storage electrode 124, And a storage capacitor StgC together with the gate insulating film 110 interposed between the source and drain electrodes.

On the other hand, a first passivation layer 128 is formed as an inorganic insulating material on top of the thin film transistor Tr (not shown) as the switching and driving element. Although not shown in the drawing, the first passivation layer 128 may include a first passivation layer (not shown) for electrically connecting the driving TFTs (not shown) in the non-display area NA to the driving gate electrodes A plurality of contact holes (not shown) are formed to expose corresponding electrodes of the driving source electrode and the driving drain electrode. The gate and data pad contact holes (not shown) corresponding to the gate and data pad electrodes (Not shown) is formed.

Also, in the display area DA, the second passivation layer 130 having a thickness of about 2 탆 to about 4 탆 is formed as an organic insulating material. At this time, the drain electrode 122 of the thin film transistor Tr formed in each pixel region P is formed in the second passivation layer 130 and the first passivation layer 128 under the second passivation layer 130, A drain contact hole 133 is formed to expose the semiconductor substrate.

In the non-display area NA, the organic insulating material is the same as the material of the second passivation layer 130, and the thickness of the electrophoretic film 167 is about 2 to 4 μm. A buffer pattern 131 is formed for alleviating the impact caused by the contact of the roll during the laminating process.

At this time, the width of the cushioning pattern 131 may be set such that the end of the electrophoretic film 167 is always in contact with the edge of the electrophoretic film 167 even if a positional error is tolerated in consideration of a positional error at the time of the laminating process. And is formed to have a sufficient width so as to be positioned above the buffer pattern 131. Since the alignment error of the electrophoretic film 167 during laminating is usually 0.5 mm or less, it is preferable that the alignment error is formed to have a width of about 0.5 mm to 1 mm.

At this time, the cushioning pattern 131 may be spaced apart from the second protective layer 130 formed on the display area DA, or alternatively may be formed on the second protective layer 130 130, respectively.

Therefore, as described above, since the cushioning pattern 131 made of an organic insulating material having a flexibility characteristic to the inorganic insulating material and having elasticity is provided in the non-display area NA, the roll is contacted through the electrophoretic film 167 for the first time So that the occurrence of cracks can be suppressed in the gate link wiring 125, the electrodes (not shown) of the driving elements, and the gate insulating film 110 located under these components. Even if a foreign object is interposed, the buffer pattern 131 has a thickness of about 2 탆 to 4 탆 and has an elastic force, so that cracks caused by the pressing of the foreign object can be suppressed to some extent. Accordingly, the occurrence of such a crack is suppressed, so that the end of the gate link wiring 125 cut by the creping causes the gate insulating film 110 to penetrate and come into contact with the common connection wiring 108 located at a lower portion thereof, It can also be suppressed naturally.

A plurality of capsules 160 filled with a white pigment 156 and a plurality of black pigments 158 and a plurality of black pigments 158 charged through a condensation polymerization reaction corresponding to the array substrate 101 having the above- An adhesive layer 165 made of a transparent material at a lower portion of the ink layer 163 and an adhesive layer 165 made of a transparent conductive material between the ink layer 163 and the base film 150. [ And an electrophoretic film 167 including a common electrode 153 is attached and configured.

In addition, a color filter layer 170 having color filter patterns 170a and 170b (not shown) of red, green, and blue that are repeated in succession is formed on the electrophoretic film 167, 180), thereby forming the electrophoretic display device 100 according to the present invention.

Hereinafter, a method of manufacturing the electrophoretic display device according to the present invention having the above-described structure will be described with reference to the drawings.

FIGS. 8A to 8K are diagrams illustrating an electrophoretic display device according to an embodiment of the present invention. FIG. 8A to FIG. 8K illustrate an electrophoretic display device according to an embodiment of the present invention, in which a pixel region including a portion where a thin film transistor is formed in a display region DA and a portion where a storage capacitor is formed, FIG. 5 is a cross-sectional view showing a part of a non-display region according to a manufacturing step. For convenience of description, a region in which a switching thin film transistor is formed in each pixel region P is defined as a switching region TrA.

8A, a first metal material such as aluminum (Al), an aluminum alloy (AlNd), copper (Cu), a copper alloy A step of forming a first metal layer (not shown) by depositing chromium (Cr), a titanium alloy, and then performing a process such as coating of photoresist, exposure using a mask, development of a photoresist, etching, A gate wiring (not shown) extending in one direction and a common wiring (not shown) extending in parallel thereto are formed in the display region.

At the same time, a gate electrode 103 connected to the gate wiring (not shown) is formed in the first storage electrode 105 and the switching region TrA. At this time, the first storage electrode 105 is branched from the common wiring (not shown) formed in parallel with the gate wiring (not shown), or is formed as the common wiring (not shown) itself.

In the non-display area NA, a common connection wiring 108 connected to the common wiring (not shown) and a Vgl wiring (not shown) are formed apart from the common connection wiring 108. Although not shown in the drawing, a gate electrode (hereinafter referred to as a driving gate electrode) of a driving thin film transistor serving as a driving element to be provided for a circuit configuration for preventing static electricity is formed.

Meanwhile, the first metal layer (not shown) may be formed to have a bilayer structure by continuously depositing different metal materials. When a first metal layer (not shown) having such a bilayer structure is patterned, gate wirings (not shown) having a double layer structure of aluminum alloy (AlNd) / molybdenum (Mo), titanium alloy / copper The gate electrode 103, the first storage electrode 105, the common wiring (not shown), the common connection wiring 108, and the driving gate electrode (not shown). (Not shown), a gate electrode 103, a first storage electrode 105, a common wiring (not shown), a common connection wiring 108 and a driving gate electrode (not shown) having a single- Respectively.

Next, as shown in FIG. 8B, the gate wiring (not shown), the gate electrode 103, the first storage electrode 105, the common wiring (not shown), the common connection wiring 108, An inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN x) is deposited on the entire surface of the substrate 110 (not shown) to form the gate insulating film 110.

Thereafter, a pure amorphous silicon layer (not shown) and an impurity amorphous silicon layer (not shown) are formed continuously by continuously depositing the pure amorphous silicon and the impurity amorphous silicon on the gate insulating film 110, And an active layer 115a and an impurity amorphous silicon pattern 115c are formed on the active layer 115a corresponding to the gate electrode 103 in the switching region TrA. At this time, the active layer 115a and the impurity amorphous silicon pattern 115c have the same shape as the same material, and a driving active layer (not shown) is formed corresponding to a driving gate electrode (not shown) provided in the non- And a driving impurity amorphous silicon pattern (not shown). Although not shown in the figure, the gate insulating layer 110 is patterned at the boundary of the display area DA to form a link contact hole (not shown) exposing one end of the gate interconnects (not shown). This is to connect the gate link wiring (not shown) and the gate pad electrode (not shown) and the gate wiring (not shown) to be formed in a subsequent process.

Next, as shown in FIG. 8C, a second metal material such as molybdenum (Mo) or copper (Cu) is formed on the active layer 115a, the impurity amorphous silicon pattern ), A titanium alloy, and an aluminum alloy (AlNd) are deposited to form a second metal layer (not shown) on the entire surface of the substrate. At this time, the second metal layer (not shown) may be formed by continuously depositing two or three of the second metal materials to have a double layer structure of, for example, a titanium alloy / copper (Cu) or a molybdenum / Layer structure of aluminum alloy (AlNd) / molybdenum (Mo). In the drawings, one having a single layer structure is shown as an example.

Thereafter, the data line 118 defining the pixel region P is formed in the display region DA by patterning the second metal layer (not shown) so as to intersect the gate line (not shown) (Not shown) connected to the data line 118 in the display area NA, a data pad electrode (not shown) at the end thereof, and a gate wiring (not shown) through the link contact hole And a gate pad electrode (not shown) connected to the other end of the gate link wiring 125 are formed.

At the same time, source and drain electrodes 120 and 122 are formed in the switching region TrA in each pixel region P so as to be spaced from each other above the impurity amorphous silicon pattern 115c (FIG. 8B) 122 are extended to form a second storage electrode 124 overlapping the first storage electrode 105. At this time, the source electrode 120 is connected to the data line 118.

Although not shown in the figure, driving source electrodes (not shown) and driving drain electrodes (not shown) are formed in the non-display area NA to correspond to the driving impurity amorphous pattern (not shown).

Thereafter, dry etching is performed to remove the impurity amorphous silicon pattern (115c in FIG. 8B) between the source and drain electrodes 120 and 122, thereby forming the active layer 115a between the source and drain electrodes 120 and 122 And an ohmic contact layer 115b of impurity amorphous silicon is formed on the active layer 115a in contact with the source and drain electrodes 120 and 122 and spaced apart from each other. At this time, the active layer 115a and the ohmic contact layer 115b, which are separated from each other on the active layer 115a, constitute the semiconductor layer 115. At this time, the same process is also performed in the non-display area NA to form a driving ohmic contact layer (not shown) below the driving source and drain electrodes (not shown) An electrode (not shown), a gate insulating layer 110, a driving active layer (not shown), a driving ohmic contact layer (not shown), a driving source and a drain electrode (not shown) constitute driving thin film transistors (not shown).

Meanwhile, the above-described steps of forming the semiconductor layer 115 and the source and drain electrodes 120 and 122 are performed through two different mask processes, respectively. However, although not shown in the drawings as a modification, a pure water and an impurity amorphous silicon layer are formed on the gate insulating film 110, and the second metal layer is formed on the impurity amorphous silicon layer before the patterning, The semiconductor layer and the source and drain electrodes may be formed through a single mask process characterized in that a photoresist pattern having different thicknesses is formed by performing a mask process using a halftone exposure technique. In this case, a semiconductor pattern is formed under the data line and the data pad electrode as the same material as the semiconductor layer.

Next, as shown in FIG. 8D, the data wiring (not shown), the source and drain electrodes 120 and 122, the second storage electrode 124, the data link wiring (not shown), and the data pad electrode For example, silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the entire surface of the gate wiring line 125, the gate pad electrode (not shown), the driving source and the drain electrode A first passivation layer 128 is formed. At this time, in the case of the first passivation layer 128, deposition is not performed corresponding to the portions corresponding to the gate and data pad electrodes (not shown) due to the shadow frame during deposition thereof, so that the gate and the data pad electrodes ) Is in an exposed state.

Next, an organic insulating material such as photo acryl or benzocyclobutene (BCB) is applied on the first passivation layer 128 to have a thickness of about 3 탆 to about 5 탆 and a flat surface An organic insulating layer (not shown) is formed.

Thereafter, diffraction exposure or halftone exposure is performed on the organic insulation layer (not shown) and the development is performed so that the display area DA composed of a plurality of pixel areas P is formed to a thickness of about 3 to 5 mu m The first organic insulating pattern 129a having the first thickness of the electrophoretic film 167 corresponding to the portion where the end of the electrophoretic film 167 is to be positioned in the subsequent process corresponding to the non- And the second organic insulating pattern is formed so as to have a second thickness of about 1 mu m which is thinner than the first thickness corresponding to the other non-display area (NA) (129b).

A first hole 133 is formed in the pixel region P corresponding to each of the drain electrodes 122 to expose the first passivation layer 128 located thereon. A second hole (not shown) is formed to expose the first passivation layer 128 formed on the upper portion of the plurality of driving source and drain electrodes (not shown) or the driving gate electrode (not shown).

Thereafter, as shown in FIG. 8E, the first dry etching is performed in the first gas atmosphere to form a first protective layer (not shown) made of an inorganic insulating material corresponding to the first and second holes 132 128 are removed to form a drain contact hole 133 and a plurality of first contact holes (not shown) exposing the drain electrode 122 of the switching region TrA.

  Next, as shown in FIG. 8F, the second dry etching is performed in the second gas atmosphere to remove the second organic insulation pattern (129b in FIG. 8E) formed in the non-display area NA with the second thickness . By the second dry etching in the second gas atmosphere, the thickness of the first organic insulation pattern (129a in FIG. 8E) in the display area DA is reduced, and the thickness of the first organic insulation pattern 2 protective layer 130. At the same time, the thickness of the non-display area NA is reduced by about 1 占 퐉 to form a buffer pattern 131 having a thickness of about 2 占 퐉 to about 4 占 퐉. In addition, the gate and the data pad electrode (not shown) are exposed in the non-display area NA by the second dry etching.

The reason why the second protective layer 130 is formed as an organic insulating material so as to have a thickness of about 2 탆 to 4 탆 in the display area DA is that the gate wiring (not shown) and the data wiring 118 To minimize the parasitic capacitance generated by the pixel electrode (not shown) formed so as to overlap the pixel electrode (not shown), and to have a flat surface.

The reason for not forming the second passivation layer 130 made of the organic insulating material in the non-display area NA is that the electrodes (not shown) of the driving thin film transistor (not shown) The driving source and drain electrodes (not shown) of these driving thin film transistors have a very small area, and it is necessary to form a connection pattern with a transparent conductive material in a subsequent process through a first contact hole (not shown) , The thickness of the second passivation layer 130 is too thick as compared with the area of the first contact hole (not shown), so that the driving electrodes (not shown) So that this problem is solved. Since the drain contact hole 133 has a larger area than the driving source and drain electrodes (not shown) of the driving thin film transistor (not shown) in the display area DA, the drain contact hole 133 is sufficiently The problem of disconnection or the like described above does not occur.

In addition, when the second protective layer 130 made of the organic insulating material is formed on the entire surface of the non-display area NA, the thickness of the second protective layer 130 is too thick and flexibility and elasticity The second protective layer 130 made of the organic insulating material is not formed in the non-display area NA in order to solve such a problem.

On the other hand, in the present invention, the buffering pattern 131 is formed of an organic insulating material having an elastic force in the non-display area NA, but it has a width of 0.5 mm to 1 mm corresponding to the vicinity of the display area DA So that there is no problem in cutting.

Next, as shown in FIG. 8G, a transparent conductive material such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO), and indium-tin- (ITZO) to form a conductive material layer (not shown) on the entire surface. Thereafter, the conductive material layer (not shown) is patterned to make contact with the drain electrode 122 through the drain contact hole 133 in each pixel region P, The pixel electrode 140 is formed so as to completely overlap the gate wiring (not shown) in contact with the switching thin film transistor Tr and the data wiring 118. The reason for forming the pixel electrode 140 in this form is to maximize the aperture ratio.

In the present invention, since the pixel electrode 140 is formed so as to completely overlap with the gate and data lines (not shown) connected to the switching thin film transistor Tr, a problem of parasitic capacitance may occur. In order to minimize the parasitic capacitance, The second protective layer 130 having a thickness of about 2 탆 to about 4 탆 is formed.

On the other hand, in the non-display area NA, the transparent conductive material layer (not shown) is patterned to form a first contact hole (not shown) on the first passivation layer 128 exposed to the outside of the buffer pattern 131 (Not shown) for electrically connecting the electrodes of neighboring driving thin film transistors (not shown) through a gate pad electrode (not shown) and covering the gate and data pad electrodes (not shown) And a data pad pad electrode (not shown).

Next, as shown in Figs. 8H and 8I, a substrate 101 on which pixel electrodes 140 are formed in each pixel region P is placed on a stage (not shown) of the laminating apparatus, and a transparent and flexible A common electrode 153 formed on the entire surface of the base film 150 made of a transparent conductive material and a plurality of white pigments 156 charged through a condensation polymerization reaction An ink layer 163 including a plurality of capsules 160 filled with a black pigment 158 and an electrophoretic film 167 including an adhesive layer 165 under the ink layer 163 And is positioned between the common electrode 153 and the pixel electrode 140 to face the adhesive layer 165 and the pixel electrode 140.

Thereafter, after the end of the electrophoretic film 167 is positioned on the cushioning pattern 131 formed in the non-display area NA, the roll of the laminating device is aligned with the end of the electrophoretic film 167 And the electrophoretic film 167 is attached to the array substrate 101 by proceeding in one direction while applying a constant pressure.

When the laminating process is performed, the end of the electrophoretic film 167, which is initially contacted with the roll 190 of the laminating apparatus, is positioned on the cushioning pattern 131 made of an organic insulating material having elasticity The impact caused by the roll contact is relieved to suppress the generation of cracks in the gate link wiring 125, the driving electrode (not shown), and the gate insulating film 110 located at the lower portion.

On the other hand, when the process up to the above-described process is completed, a black and white electrophoresis apparatus is completed.

The subsequent process is an optional step in the manufacture of an electrophoretic device capable of color implementation.

Next, as shown in FIG. 8J, an electrophoretic film 167 adhered to the display area DA, more precisely one on the entire surface of the display area DA above the base film 150, one of red, For example, by applying a red color resist through a spin coating method to form a red color filter layer (not shown). Then, a transparent region through which light passes and a blocking And then the exposed color resist layer is developed to form a red color filter pattern 170a corresponding to a certain pixel region P. [ At this time, since the color resist layer has a negative property, the light-receiving portion is left, and the light-unexposed portion is removed to form a red color filter pattern 170a corresponding to a certain pixel region (P) do.

The green color filter pattern 170a and the blue color filter pattern 170b are formed on the base film 150 to correspond to some pixel regions P by proceeding in the same manner as the method of forming the red color filter pattern 170a, The filter layer 170 is completed. In this case, the red, green, and blue color filter patterns 170a and 170b (not shown) are sequentially and repeatedly corresponding to the pixel regions P, respectively.

In addition, although the above-described method is an example of forming the color filter layer according to the pigment dispersion method, the three color filter patterns 170a and 170b may also be formed by doting each pixel region P using an ink- The color filter layer 170 may be formed.

Next, as shown in FIG. 8K, an opposing substrate (not shown) made of a transparent and flexible plastic material is placed on the color filter layer 170, and a seal (not shown) is formed along the non-display area NA around the display area DA (Not shown), and the counter substrate 180 is adhered to the array substrate 101 so as to cover the display area DA. In this case, the counter substrate 180 is attached such that the gate and data auxiliary pad electrodes (not shown) are exposed. At this time, the counter substrate 180 may be in the form of a film and attached to the electrophoretic film 167 or the color filter layer 170 via an adhesive layer (not shown). In this case, the seal pattern (not shown) is omitted.

Although the color filter layer 170 is formed on the electrophoretic film 167 as an example, the color filter layer 170 is preferentially formed on the lower surface of the counter substrate 180, It may be bonded to the array substrate 101 provided with the film 167. [

It is to be understood that the invention is not limited to the above-described embodiment and modifications thereof, and that various modifications and changes may be made without departing from the spirit and scope of the present invention.

1 is a view for explaining a driving principle of an electrophoretic display device;

2 is a cross-sectional view schematically showing a conventional electrophoretic display device.

3 is a view showing a step of laminating an electrophoretic film to an array substrate during a process of manufacturing a conventional electrophoretic display device.

4 is a cross-sectional view of a display area and a part of a non-display area of a conventional electrophoretic display device.

FIGS. 5A and 5B are photographs of a part of a top view of the array substrate corresponding to a position where the end of the electrophoretic film is located, respectively. FIG. 5A shows the state before the electrophoretic film was attached, Fig.

6 is a plan view of a display region and a part of a non-display region of the electrophoretic display device according to the present invention.

7 is a cross-sectional view of a portion cut along line VII-VII of FIG. 6;

8A to 8K are cross-sectional views illustrating an electrophoretic display device according to an exemplary embodiment of the present invention. Referring to FIGS. 8A to 8K, a pixel region including a portion where a thin film transistor is formed in a display region and a portion where a storage capacitor is formed, Sectional view of a process step for a portion of a region.

Description of the Related Art

100: electrophoretic display device 101: substrate

103: gate electrode 108: common connection wiring

105: storage first electrode 110: gate insulating film

115: semiconductor layer 115a: active layer

115c: ohmic contact layer 118: data line

120: source electrode 122: drain electrode

124: storage second electrode 125: gate link wiring

128: first protective layer 130: second protective layer

131: buffer pattern 140: pixel electrode

150: base film 153: common electrode

156: White pigment 158: Black pigment

160: capsule 163: ink layer 165: adhesive layer

167: electrophoretic film 170: color filter layer

180: opposing substrate

Claims (17)

A gate wiring and a data wiring formed so as to define a plurality of pixel regions intersecting each other in the display region on a substrate on which a non-display region around the display region is defined, and a display region composed of a plurality of pixel regions, A gate and a data link wiring formed and connected to the gate and the data wiring; A thin film transistor composed of the gate electrode, the gate insulating film, the semiconductor layer, and the source and drain electrodes spaced apart from each other in a stacked manner in each of the plurality of pixel regions; First and second storage electrodes formed in the plurality of pixel regions and formed under and over the gate insulating layer to form a storage capacitor together with the gate insulating layer; A first passivation layer covering the thin film transistor and the storage capacitor and having a drain contact hole having a first thickness as an organic insulating material in the display region and exposing the drain electrode; A buffer layer formed of the same material as the first protective layer and having the same thickness and having a first width in the non-display region;  A pixel electrode formed in each of the pixel regions in contact with the drain electrode of the thin film transistor through the drain contact hole on the first protective layer in the display region; A non-display region where one end of the pixel electrode is located on the cushioning pattern and in which the cushioning pattern is formed, and an electrophoretic film And an electrophoretic display device. The method according to claim 1, Wherein the electrophoretic film comprises: An ink layer composed of an adhesive layer in contact with the pixel electrode, a plurality of capsules filled with a plurality of white pigments and black pigments sequentially charged through a condensation polymerization reaction, and a common electrode made of a transparent conductive material, Wherein the electrophoretic display comprises a film. The method according to claim 1, A color filter layer including red, green, and blue color filter patterns sequentially repeating on the electrophoretic film; and an opposing substrate. The method according to claim 1, And a second protective layer as an inorganic insulating material between the first passivation layer and the thin film transistor. The method according to claim 1, A gate pad electrode connected to one end of the gate link wiring, a data pad electrode connected to one end of the data link wiring, and a thin film transistor formed in the pixel region for implementing an antistatic circuit, The driving thin film transistor having the driving thin film transistor formed thereon. The method according to claim 1, Wherein the first thickness is 2 탆 to 4 탆, and the first width is 0.5 mm to 1 mm. The method according to claim 1, Wherein the buffer pattern and the first passivation layer are connected to each other. The method according to claim 1, Wherein the pixel electrode is formed in the pixel region so as to overlap the thin film transistor, the gate wiring on one side connected thereto, and the data wiring on one side. A gate wiring and a data wiring which intersect with each other in the display area on the substrate on which the non-display area around the display area is defined to define a plurality of pixel areas; Forming a gate and a data link wiring connected to the gate and the data wiring; A thin film transistor formed of the gate electrode, the gate insulating film, the semiconductor layer, and the source and drain electrodes spaced apart from each other in a stacked manner in each of the plurality of pixel regions; a first storage electrode, Forming a storage capacitor having a stacked structure of electrodes; Forming a first protective layer covering the thin film transistor and the storage capacitor and having a first thickness as an organic insulating material in the display region and having a drain contact hole exposing the drain electrode, Forming a cushioning pattern having the same thickness and having a first width with the same material forming the protective layer; Forming a pixel electrode in each pixel region in the display region in contact with the drain electrode of the thin film transistor through the drain contact hole over the first passivation layer; Placing the electrophoretic film so that its one end is positioned on the buffering pattern over the pixel electrode and allowing the roll to come into contact with the end of the electrophoretic film located in the buffer pattern through a laminating device having a roll, A step of attaching the electrophoretic film corresponding to the non-display area where the buffer pattern is formed and the entire display area by applying pressure and transferring And the electrophoretic display device. Claim 10 has been abandoned due to the setting registration fee. 10. The method of claim 9, Forming a color filter layer on the electrophoretic film, adhering a transparent counter substrate, or forming a color filter layer on the counter substrate, and adhering the electrophoretic film so as to face the electrophoretic film . 10. The method of claim 9, Wherein forming the buffer layer and the first passivation layer having the drain contact hole comprises: Applying an organic insulating material over the thin film transistor to form an organic insulating material layer; A first organic insulating layer having a second thickness greater than the first thickness and having the drain contact hole exposing the drain electrode is formed in the display region by performing halftone exposure or diffraction exposure on the organic insulating material layer Forming a second organic insulating layer having an organic pattern of the second thickness and a third thickness thinner than the first thickness in the non-display area; Performing dry etching to remove the second organic insulating layer having the third thickness and reducing the thickness of the first organic insulating layer and the organic pattern to have the first thickness And the electrophoretic display device. Claim 12 is abandoned in setting registration fee. 10. The method of claim 9, Wherein the first thickness is 2 탆 to 4 탆 and the first width is 0.5 mm to 1 mm. Claim 13 has been abandoned due to the set registration fee. 10. The method of claim 9, And forming a second passivation layer on the entire surface of the thin film transistor with an inorganic insulating material before forming the first passivation layer. Claim 14 has been abandoned due to the setting registration fee. 10. The method of claim 9, Wherein forming the gate and the data wiring and the gate and the data link wiring comprises: Forming a gate pad electrode connected to one end of the gate link wiring in the non-display area and a data pad electrode connected to one end of the data link wiring, Wherein the forming of the thin film transistor includes forming a driving thin film transistor having the same structure as the thin film transistor formed in the pixel region in the non-display region. Claim 15 is abandoned in the setting registration fee payment. 10. The method of claim 9, Wherein the pixel electrode is formed in the pixel region so as to overlap the thin film transistor, the gate wiring on one side connected to the thin film transistor, and the data wiring on one side. Claim 16 has been abandoned due to the setting registration fee. 15. The method of claim 14, Wherein forming the gate and the data wiring and the gate and the data link wiring comprises: Forming the gate wiring in a display region on the substrate and forming a common connection wiring in the non-display region; Forming the gate insulating film on the entire surface of the gate wiring and the common connection wiring; Patterning the gate insulating layer to form a link contact hole exposing one end of the gate wiring; Forming a data line crossing the gate line on the display region over the gate insulating film provided with the link contact hole and connecting the data line wiring and the link contact hole connected to the data line to the non- Forming a gate link wiring which contacts one end of the gate wiring and crosses the common connection wiring;  And the electrophoretic display device. 6. The method of claim 5, Wherein a common connection wiring made of the same material is formed in the same layer as the gate wiring in the non-display area, and the gate wiring wiring crosses the common connection wiring and is formed on the gate insulation film.

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